./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/rfi007_pso.oepc_false-unreach-call.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_574140b9-9c06-496f-8dad-f2fe678a2345/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_574140b9-9c06-496f-8dad-f2fe678a2345/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_574140b9-9c06-496f-8dad-f2fe678a2345/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_574140b9-9c06-496f-8dad-f2fe678a2345/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/rfi007_pso.oepc_false-unreach-call.i -s /tmp/vcloud-vcloud-master/worker/working_dir_574140b9-9c06-496f-8dad-f2fe678a2345/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_574140b9-9c06-496f-8dad-f2fe678a2345/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a30a75099bfc7085c3bb0db7d9c1b74b69a69eff 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 14:28:36,893 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 14:28:36,894 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 14:28:36,900 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 14:28:36,901 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 14:28:36,901 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 14:28:36,902 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 14:28:36,903 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 14:28:36,904 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 14:28:36,905 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 14:28:36,906 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 14:28:36,906 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 14:28:36,906 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 14:28:36,907 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 14:28:36,908 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 14:28:36,908 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 14:28:36,909 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 14:28:36,910 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 14:28:36,911 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 14:28:36,912 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 14:28:36,913 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 14:28:36,914 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 14:28:36,916 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 14:28:36,916 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 14:28:36,916 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 14:28:36,917 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 14:28:36,917 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 14:28:36,918 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 14:28:36,918 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 14:28:36,919 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 14:28:36,919 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 14:28:36,919 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 14:28:36,919 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 14:28:36,919 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 14:28:36,920 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 14:28:36,922 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 14:28:36,922 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_574140b9-9c06-496f-8dad-f2fe678a2345/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-23 14:28:36,930 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 14:28:36,930 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 14:28:36,931 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 14:28:36,931 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 14:28:36,931 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 14:28:36,931 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 14:28:36,931 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 14:28:36,931 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 14:28:36,931 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 14:28:36,931 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 14:28:36,931 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 14:28:36,932 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 14:28:36,932 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 14:28:36,932 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 14:28:36,932 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 14:28:36,932 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 14:28:36,932 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 14:28:36,932 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 14:28:36,932 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 14:28:36,932 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 14:28:36,932 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 14:28:36,932 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 14:28:36,932 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 14:28:36,933 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 14:28:36,933 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 14:28:36,933 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 14:28:36,933 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 14:28:36,933 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 14:28:36,933 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 14:28:36,933 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 14:28:36,933 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_574140b9-9c06-496f-8dad-f2fe678a2345/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a30a75099bfc7085c3bb0db7d9c1b74b69a69eff [2018-11-23 14:28:36,956 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 14:28:36,966 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 14:28:36,969 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 14:28:36,970 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 14:28:36,970 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 14:28:36,970 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_574140b9-9c06-496f-8dad-f2fe678a2345/bin-2019/uautomizer/../../sv-benchmarks/c/pthread-wmm/rfi007_pso.oepc_false-unreach-call.i [2018-11-23 14:28:37,009 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_574140b9-9c06-496f-8dad-f2fe678a2345/bin-2019/uautomizer/data/ccba2cae6/b4f9205c13c14c2b9df8e5b88cac4969/FLAG020661b0b [2018-11-23 14:28:37,458 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 14:28:37,458 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_574140b9-9c06-496f-8dad-f2fe678a2345/sv-benchmarks/c/pthread-wmm/rfi007_pso.oepc_false-unreach-call.i [2018-11-23 14:28:37,466 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_574140b9-9c06-496f-8dad-f2fe678a2345/bin-2019/uautomizer/data/ccba2cae6/b4f9205c13c14c2b9df8e5b88cac4969/FLAG020661b0b [2018-11-23 14:28:37,478 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_574140b9-9c06-496f-8dad-f2fe678a2345/bin-2019/uautomizer/data/ccba2cae6/b4f9205c13c14c2b9df8e5b88cac4969 [2018-11-23 14:28:37,480 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 14:28:37,482 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 14:28:37,482 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 14:28:37,482 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 14:28:37,486 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 14:28:37,486 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:28:37" (1/1) ... [2018-11-23 14:28:37,488 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@21114224 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:28:37, skipping insertion in model container [2018-11-23 14:28:37,488 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:28:37" (1/1) ... [2018-11-23 14:28:37,494 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 14:28:37,528 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 14:28:37,761 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 14:28:37,768 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 14:28:37,856 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 14:28:37,900 INFO L195 MainTranslator]: Completed translation [2018-11-23 14:28:37,900 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:28:37 WrapperNode [2018-11-23 14:28:37,901 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 14:28:37,901 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 14:28:37,901 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 14:28:37,901 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 14:28:37,908 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:28:37" (1/1) ... [2018-11-23 14:28:37,918 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:28:37" (1/1) ... [2018-11-23 14:28:37,935 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 14:28:37,935 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 14:28:37,935 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 14:28:37,936 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 14:28:37,942 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:28:37" (1/1) ... [2018-11-23 14:28:37,942 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:28:37" (1/1) ... [2018-11-23 14:28:37,944 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:28:37" (1/1) ... [2018-11-23 14:28:37,945 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:28:37" (1/1) ... [2018-11-23 14:28:37,950 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:28:37" (1/1) ... [2018-11-23 14:28:37,953 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:28:37" (1/1) ... [2018-11-23 14:28:37,955 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:28:37" (1/1) ... [2018-11-23 14:28:37,957 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 14:28:37,957 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 14:28:37,957 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 14:28:37,957 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 14:28:37,958 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:28:37" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_574140b9-9c06-496f-8dad-f2fe678a2345/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 14:28:37,994 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 14:28:37,994 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-23 14:28:37,994 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2018-11-23 14:28:37,994 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 14:28:37,994 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2018-11-23 14:28:37,995 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2018-11-23 14:28:37,995 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2018-11-23 14:28:37,995 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2018-11-23 14:28:37,995 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2018-11-23 14:28:37,995 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 14:28:37,995 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 14:28:37,996 WARN L198 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2018-11-23 14:28:38,496 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 14:28:38,497 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-11-23 14:28:38,497 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:28:38 BoogieIcfgContainer [2018-11-23 14:28:38,497 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 14:28:38,498 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 14:28:38,498 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 14:28:38,500 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 14:28:38,500 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 02:28:37" (1/3) ... [2018-11-23 14:28:38,501 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5352c82e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 02:28:38, skipping insertion in model container [2018-11-23 14:28:38,501 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:28:37" (2/3) ... [2018-11-23 14:28:38,501 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5352c82e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 02:28:38, skipping insertion in model container [2018-11-23 14:28:38,501 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:28:38" (3/3) ... [2018-11-23 14:28:38,503 INFO L112 eAbstractionObserver]: Analyzing ICFG rfi007_pso.oepc_false-unreach-call.i [2018-11-23 14:28:38,529 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,529 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,529 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,529 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,529 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,529 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,530 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,530 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,530 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,530 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,530 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,530 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,531 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,531 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,531 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,531 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,531 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,531 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,531 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,532 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,532 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,532 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,532 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,532 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,532 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,532 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,533 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,533 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,533 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,533 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,533 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,533 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,533 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,534 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,534 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,534 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,534 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,534 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,535 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet11.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,535 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet11.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,535 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,535 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet10.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,535 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,535 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet10.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,535 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet11.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,535 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet10.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,535 WARN L317 ript$VariableManager]: TermVariabe Thread1_P1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,535 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet11.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,536 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet10.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,536 WARN L317 ript$VariableManager]: TermVariabe Thread1_P1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,536 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,536 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,536 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,536 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,539 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,539 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,539 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,539 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,539 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,540 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,540 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,540 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,540 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,540 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,540 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,541 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,541 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,541 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,541 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,541 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,541 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,542 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,542 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,542 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,542 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,542 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,542 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,542 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,543 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,543 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,543 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,543 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,543 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,543 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,543 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,544 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,544 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,544 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,544 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,544 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,544 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,545 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,545 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,545 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,545 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,545 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,545 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,545 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,546 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,546 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,546 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,546 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,546 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,546 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,546 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,547 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,547 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,547 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,547 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,547 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,547 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,547 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,548 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,548 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,548 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,548 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,548 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,548 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,548 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,549 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,549 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,549 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,549 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,549 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,549 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,549 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,550 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,550 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,550 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,550 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,550 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,550 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,550 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,550 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,551 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,551 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,551 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,551 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,551 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,551 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,551 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,552 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,552 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,552 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,552 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,552 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,552 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,553 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,553 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,553 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,553 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,553 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,553 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,553 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,554 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,554 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,554 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,554 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,554 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet39.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,554 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet39.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,554 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,555 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,555 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet39.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,555 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet39.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 14:28:38,566 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2018-11-23 14:28:38,566 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 14:28:38,573 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2018-11-23 14:28:38,587 INFO L257 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2018-11-23 14:28:38,601 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 14:28:38,602 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 14:28:38,602 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 14:28:38,602 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 14:28:38,602 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 14:28:38,602 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 14:28:38,602 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 14:28:38,603 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 14:28:38,603 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 14:28:38,611 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 142places, 180 transitions [2018-11-23 14:28:40,331 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 34806 states. [2018-11-23 14:28:40,333 INFO L276 IsEmpty]: Start isEmpty. Operand 34806 states. [2018-11-23 14:28:40,338 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-11-23 14:28:40,338 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:40,339 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:40,340 INFO L423 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:40,343 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:40,343 INFO L82 PathProgramCache]: Analyzing trace with hash 829463542, now seen corresponding path program 1 times [2018-11-23 14:28:40,345 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:40,345 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:40,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:40,381 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:40,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:40,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:40,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:40,518 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:40,518 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 14:28:40,521 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 14:28:40,529 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 14:28:40,529 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:28:40,531 INFO L87 Difference]: Start difference. First operand 34806 states. Second operand 4 states. [2018-11-23 14:28:41,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:41,278 INFO L93 Difference]: Finished difference Result 60790 states and 234493 transitions. [2018-11-23 14:28:41,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 14:28:41,279 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 33 [2018-11-23 14:28:41,280 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:41,490 INFO L225 Difference]: With dead ends: 60790 [2018-11-23 14:28:41,490 INFO L226 Difference]: Without dead ends: 44270 [2018-11-23 14:28:41,491 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:28:41,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44270 states. [2018-11-23 14:28:42,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44270 to 27338. [2018-11-23 14:28:42,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27338 states. [2018-11-23 14:28:42,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27338 states to 27338 states and 105499 transitions. [2018-11-23 14:28:42,368 INFO L78 Accepts]: Start accepts. Automaton has 27338 states and 105499 transitions. Word has length 33 [2018-11-23 14:28:42,368 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:42,368 INFO L480 AbstractCegarLoop]: Abstraction has 27338 states and 105499 transitions. [2018-11-23 14:28:42,368 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 14:28:42,368 INFO L276 IsEmpty]: Start isEmpty. Operand 27338 states and 105499 transitions. [2018-11-23 14:28:42,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-11-23 14:28:42,374 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:42,376 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:42,376 INFO L423 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:42,377 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:42,377 INFO L82 PathProgramCache]: Analyzing trace with hash 1614500037, now seen corresponding path program 1 times [2018-11-23 14:28:42,377 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:42,377 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:42,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:42,381 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:42,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:42,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:42,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:42,444 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:42,444 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 14:28:42,445 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 14:28:42,445 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 14:28:42,445 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:28:42,446 INFO L87 Difference]: Start difference. First operand 27338 states and 105499 transitions. Second operand 4 states. [2018-11-23 14:28:42,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:42,533 INFO L93 Difference]: Finished difference Result 8528 states and 28344 transitions. [2018-11-23 14:28:42,534 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:28:42,534 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 45 [2018-11-23 14:28:42,534 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:42,548 INFO L225 Difference]: With dead ends: 8528 [2018-11-23 14:28:42,548 INFO L226 Difference]: Without dead ends: 7466 [2018-11-23 14:28:42,549 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:28:42,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7466 states. [2018-11-23 14:28:42,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7466 to 7466. [2018-11-23 14:28:42,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7466 states. [2018-11-23 14:28:42,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7466 states to 7466 states and 24636 transitions. [2018-11-23 14:28:42,642 INFO L78 Accepts]: Start accepts. Automaton has 7466 states and 24636 transitions. Word has length 45 [2018-11-23 14:28:42,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:42,642 INFO L480 AbstractCegarLoop]: Abstraction has 7466 states and 24636 transitions. [2018-11-23 14:28:42,642 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 14:28:42,643 INFO L276 IsEmpty]: Start isEmpty. Operand 7466 states and 24636 transitions. [2018-11-23 14:28:42,644 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-11-23 14:28:42,644 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:42,644 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:42,644 INFO L423 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:42,645 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:42,645 INFO L82 PathProgramCache]: Analyzing trace with hash 2087909407, now seen corresponding path program 1 times [2018-11-23 14:28:42,645 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:42,645 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:42,648 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:42,648 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:42,648 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:42,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:42,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:42,718 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:42,718 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:28:42,718 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:28:42,719 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:28:42,719 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:28:42,719 INFO L87 Difference]: Start difference. First operand 7466 states and 24636 transitions. Second operand 5 states. [2018-11-23 14:28:42,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:42,937 INFO L93 Difference]: Finished difference Result 13998 states and 45805 transitions. [2018-11-23 14:28:42,941 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 14:28:42,941 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 46 [2018-11-23 14:28:42,941 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:42,979 INFO L225 Difference]: With dead ends: 13998 [2018-11-23 14:28:42,979 INFO L226 Difference]: Without dead ends: 13930 [2018-11-23 14:28:42,980 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 14:28:43,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13930 states. [2018-11-23 14:28:43,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13930 to 9441. [2018-11-23 14:28:43,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9441 states. [2018-11-23 14:28:43,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9441 states to 9441 states and 30542 transitions. [2018-11-23 14:28:43,201 INFO L78 Accepts]: Start accepts. Automaton has 9441 states and 30542 transitions. Word has length 46 [2018-11-23 14:28:43,202 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:43,202 INFO L480 AbstractCegarLoop]: Abstraction has 9441 states and 30542 transitions. [2018-11-23 14:28:43,202 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:28:43,202 INFO L276 IsEmpty]: Start isEmpty. Operand 9441 states and 30542 transitions. [2018-11-23 14:28:43,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-23 14:28:43,203 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:43,203 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:43,204 INFO L423 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:43,204 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:43,204 INFO L82 PathProgramCache]: Analyzing trace with hash 1703396709, now seen corresponding path program 1 times [2018-11-23 14:28:43,204 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:43,204 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:43,206 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:43,206 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:43,206 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:43,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:43,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:43,243 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:43,243 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:28:43,243 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:28:43,243 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:28:43,243 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:28:43,243 INFO L87 Difference]: Start difference. First operand 9441 states and 30542 transitions. Second operand 3 states. [2018-11-23 14:28:43,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:43,329 INFO L93 Difference]: Finished difference Result 13279 states and 42641 transitions. [2018-11-23 14:28:43,329 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:28:43,329 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2018-11-23 14:28:43,330 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:43,352 INFO L225 Difference]: With dead ends: 13279 [2018-11-23 14:28:43,352 INFO L226 Difference]: Without dead ends: 13279 [2018-11-23 14:28:43,352 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:28:43,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13279 states. [2018-11-23 14:28:43,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13279 to 9845. [2018-11-23 14:28:43,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9845 states. [2018-11-23 14:28:43,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9845 states to 9845 states and 31508 transitions. [2018-11-23 14:28:43,492 INFO L78 Accepts]: Start accepts. Automaton has 9845 states and 31508 transitions. Word has length 48 [2018-11-23 14:28:43,493 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:43,493 INFO L480 AbstractCegarLoop]: Abstraction has 9845 states and 31508 transitions. [2018-11-23 14:28:43,493 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:28:43,493 INFO L276 IsEmpty]: Start isEmpty. Operand 9845 states and 31508 transitions. [2018-11-23 14:28:43,494 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-11-23 14:28:43,494 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:43,494 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:43,495 INFO L423 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:43,495 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:43,495 INFO L82 PathProgramCache]: Analyzing trace with hash -778746896, now seen corresponding path program 1 times [2018-11-23 14:28:43,495 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:43,495 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:43,497 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:43,497 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:43,497 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:43,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:43,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:43,578 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:43,578 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 14:28:43,578 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 14:28:43,578 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 14:28:43,578 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:28:43,578 INFO L87 Difference]: Start difference. First operand 9845 states and 31508 transitions. Second operand 7 states. [2018-11-23 14:28:44,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:44,006 INFO L93 Difference]: Finished difference Result 12285 states and 38673 transitions. [2018-11-23 14:28:44,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 14:28:44,006 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 52 [2018-11-23 14:28:44,007 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:44,020 INFO L225 Difference]: With dead ends: 12285 [2018-11-23 14:28:44,020 INFO L226 Difference]: Without dead ends: 12213 [2018-11-23 14:28:44,020 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=55, Invalid=155, Unknown=0, NotChecked=0, Total=210 [2018-11-23 14:28:44,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12213 states. [2018-11-23 14:28:44,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12213 to 10849. [2018-11-23 14:28:44,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10849 states. [2018-11-23 14:28:44,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10849 states to 10849 states and 34563 transitions. [2018-11-23 14:28:44,133 INFO L78 Accepts]: Start accepts. Automaton has 10849 states and 34563 transitions. Word has length 52 [2018-11-23 14:28:44,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:44,133 INFO L480 AbstractCegarLoop]: Abstraction has 10849 states and 34563 transitions. [2018-11-23 14:28:44,133 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 14:28:44,133 INFO L276 IsEmpty]: Start isEmpty. Operand 10849 states and 34563 transitions. [2018-11-23 14:28:44,136 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-11-23 14:28:44,136 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:44,136 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:44,136 INFO L423 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:44,137 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:44,137 INFO L82 PathProgramCache]: Analyzing trace with hash -1619956916, now seen corresponding path program 1 times [2018-11-23 14:28:44,137 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:44,137 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:44,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:44,139 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:44,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:44,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:44,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:44,211 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:44,211 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 14:28:44,211 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 14:28:44,212 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 14:28:44,212 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:28:44,212 INFO L87 Difference]: Start difference. First operand 10849 states and 34563 transitions. Second operand 4 states. [2018-11-23 14:28:44,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:44,362 INFO L93 Difference]: Finished difference Result 12396 states and 39572 transitions. [2018-11-23 14:28:44,362 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:28:44,362 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 60 [2018-11-23 14:28:44,362 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:44,375 INFO L225 Difference]: With dead ends: 12396 [2018-11-23 14:28:44,375 INFO L226 Difference]: Without dead ends: 12396 [2018-11-23 14:28:44,376 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:28:44,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12396 states. [2018-11-23 14:28:44,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12396 to 11369. [2018-11-23 14:28:44,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11369 states. [2018-11-23 14:28:44,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11369 states to 11369 states and 36236 transitions. [2018-11-23 14:28:44,501 INFO L78 Accepts]: Start accepts. Automaton has 11369 states and 36236 transitions. Word has length 60 [2018-11-23 14:28:44,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:44,501 INFO L480 AbstractCegarLoop]: Abstraction has 11369 states and 36236 transitions. [2018-11-23 14:28:44,501 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 14:28:44,501 INFO L276 IsEmpty]: Start isEmpty. Operand 11369 states and 36236 transitions. [2018-11-23 14:28:44,504 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-11-23 14:28:44,505 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:44,505 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:44,505 INFO L423 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:44,505 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:44,505 INFO L82 PathProgramCache]: Analyzing trace with hash 122853419, now seen corresponding path program 1 times [2018-11-23 14:28:44,505 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:44,505 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:44,507 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:44,507 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:44,507 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:44,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:44,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:44,580 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:44,580 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 14:28:44,580 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 14:28:44,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 14:28:44,581 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:28:44,581 INFO L87 Difference]: Start difference. First operand 11369 states and 36236 transitions. Second operand 6 states. [2018-11-23 14:28:44,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:44,904 INFO L93 Difference]: Finished difference Result 20969 states and 66486 transitions. [2018-11-23 14:28:44,905 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 14:28:44,905 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 60 [2018-11-23 14:28:44,905 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:44,932 INFO L225 Difference]: With dead ends: 20969 [2018-11-23 14:28:44,932 INFO L226 Difference]: Without dead ends: 20898 [2018-11-23 14:28:44,932 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2018-11-23 14:28:44,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20898 states. [2018-11-23 14:28:45,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20898 to 13755. [2018-11-23 14:28:45,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13755 states. [2018-11-23 14:28:45,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13755 states to 13755 states and 43280 transitions. [2018-11-23 14:28:45,111 INFO L78 Accepts]: Start accepts. Automaton has 13755 states and 43280 transitions. Word has length 60 [2018-11-23 14:28:45,112 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:45,112 INFO L480 AbstractCegarLoop]: Abstraction has 13755 states and 43280 transitions. [2018-11-23 14:28:45,112 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 14:28:45,112 INFO L276 IsEmpty]: Start isEmpty. Operand 13755 states and 43280 transitions. [2018-11-23 14:28:45,117 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-23 14:28:45,117 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:45,117 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:45,117 INFO L423 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:45,117 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:45,117 INFO L82 PathProgramCache]: Analyzing trace with hash 1900874254, now seen corresponding path program 1 times [2018-11-23 14:28:45,117 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:45,118 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:45,119 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:45,119 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:45,119 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:45,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:45,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:45,175 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:45,176 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 14:28:45,176 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 14:28:45,176 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 14:28:45,176 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:28:45,176 INFO L87 Difference]: Start difference. First operand 13755 states and 43280 transitions. Second operand 4 states. [2018-11-23 14:28:45,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:45,427 INFO L93 Difference]: Finished difference Result 23352 states and 74493 transitions. [2018-11-23 14:28:45,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 14:28:45,427 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 64 [2018-11-23 14:28:45,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:45,454 INFO L225 Difference]: With dead ends: 23352 [2018-11-23 14:28:45,454 INFO L226 Difference]: Without dead ends: 23352 [2018-11-23 14:28:45,454 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:28:45,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23352 states. [2018-11-23 14:28:45,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23352 to 14523. [2018-11-23 14:28:45,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14523 states. [2018-11-23 14:28:45,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14523 states to 14523 states and 45664 transitions. [2018-11-23 14:28:45,653 INFO L78 Accepts]: Start accepts. Automaton has 14523 states and 45664 transitions. Word has length 64 [2018-11-23 14:28:45,653 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:45,654 INFO L480 AbstractCegarLoop]: Abstraction has 14523 states and 45664 transitions. [2018-11-23 14:28:45,654 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 14:28:45,654 INFO L276 IsEmpty]: Start isEmpty. Operand 14523 states and 45664 transitions. [2018-11-23 14:28:45,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-23 14:28:45,657 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:45,657 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:45,658 INFO L423 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:45,658 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:45,658 INFO L82 PathProgramCache]: Analyzing trace with hash -2100690035, now seen corresponding path program 1 times [2018-11-23 14:28:45,658 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:45,658 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:45,659 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:45,659 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:45,660 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:45,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:45,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:45,714 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:45,714 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 14:28:45,714 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 14:28:45,714 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 14:28:45,714 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:28:45,715 INFO L87 Difference]: Start difference. First operand 14523 states and 45664 transitions. Second operand 4 states. [2018-11-23 14:28:45,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:45,947 INFO L93 Difference]: Finished difference Result 18411 states and 56991 transitions. [2018-11-23 14:28:45,948 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 14:28:45,948 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 64 [2018-11-23 14:28:45,948 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:45,971 INFO L225 Difference]: With dead ends: 18411 [2018-11-23 14:28:45,971 INFO L226 Difference]: Without dead ends: 18411 [2018-11-23 14:28:45,971 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:28:46,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18411 states. [2018-11-23 14:28:46,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18411 to 16569. [2018-11-23 14:28:46,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16569 states. [2018-11-23 14:28:46,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16569 states to 16569 states and 51537 transitions. [2018-11-23 14:28:46,211 INFO L78 Accepts]: Start accepts. Automaton has 16569 states and 51537 transitions. Word has length 64 [2018-11-23 14:28:46,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:46,212 INFO L480 AbstractCegarLoop]: Abstraction has 16569 states and 51537 transitions. [2018-11-23 14:28:46,212 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 14:28:46,212 INFO L276 IsEmpty]: Start isEmpty. Operand 16569 states and 51537 transitions. [2018-11-23 14:28:46,216 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-23 14:28:46,216 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:46,217 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:46,217 INFO L423 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:46,217 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:46,217 INFO L82 PathProgramCache]: Analyzing trace with hash -1059723442, now seen corresponding path program 1 times [2018-11-23 14:28:46,217 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:46,217 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:46,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:46,218 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:46,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:46,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:46,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:46,256 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:46,256 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:28:46,256 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:28:46,257 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:28:46,257 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:28:46,257 INFO L87 Difference]: Start difference. First operand 16569 states and 51537 transitions. Second operand 3 states. [2018-11-23 14:28:46,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:46,427 INFO L93 Difference]: Finished difference Result 17193 states and 53232 transitions. [2018-11-23 14:28:46,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:28:46,428 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 64 [2018-11-23 14:28:46,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:46,448 INFO L225 Difference]: With dead ends: 17193 [2018-11-23 14:28:46,448 INFO L226 Difference]: Without dead ends: 17193 [2018-11-23 14:28:46,448 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:28:46,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17193 states. [2018-11-23 14:28:46,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17193 to 16901. [2018-11-23 14:28:46,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16901 states. [2018-11-23 14:28:46,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16901 states to 16901 states and 52431 transitions. [2018-11-23 14:28:46,638 INFO L78 Accepts]: Start accepts. Automaton has 16901 states and 52431 transitions. Word has length 64 [2018-11-23 14:28:46,638 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:46,638 INFO L480 AbstractCegarLoop]: Abstraction has 16901 states and 52431 transitions. [2018-11-23 14:28:46,638 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:28:46,638 INFO L276 IsEmpty]: Start isEmpty. Operand 16901 states and 52431 transitions. [2018-11-23 14:28:46,645 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-11-23 14:28:46,645 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:46,645 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:46,645 INFO L423 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:46,646 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:46,646 INFO L82 PathProgramCache]: Analyzing trace with hash 380916983, now seen corresponding path program 1 times [2018-11-23 14:28:46,646 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:46,646 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:46,647 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:46,648 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:46,648 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:46,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:46,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:46,710 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:46,710 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 14:28:46,710 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 14:28:46,710 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 14:28:46,710 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:28:46,710 INFO L87 Difference]: Start difference. First operand 16901 states and 52431 transitions. Second operand 6 states. [2018-11-23 14:28:47,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:47,357 INFO L93 Difference]: Finished difference Result 20789 states and 63395 transitions. [2018-11-23 14:28:47,357 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 14:28:47,357 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2018-11-23 14:28:47,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:47,379 INFO L225 Difference]: With dead ends: 20789 [2018-11-23 14:28:47,379 INFO L226 Difference]: Without dead ends: 20789 [2018-11-23 14:28:47,379 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:28:47,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20789 states. [2018-11-23 14:28:47,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20789 to 19521. [2018-11-23 14:28:47,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19521 states. [2018-11-23 14:28:47,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19521 states to 19521 states and 60007 transitions. [2018-11-23 14:28:47,571 INFO L78 Accepts]: Start accepts. Automaton has 19521 states and 60007 transitions. Word has length 66 [2018-11-23 14:28:47,571 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:47,571 INFO L480 AbstractCegarLoop]: Abstraction has 19521 states and 60007 transitions. [2018-11-23 14:28:47,571 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 14:28:47,571 INFO L276 IsEmpty]: Start isEmpty. Operand 19521 states and 60007 transitions. [2018-11-23 14:28:47,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-11-23 14:28:47,577 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:47,577 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:47,578 INFO L423 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:47,578 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:47,578 INFO L82 PathProgramCache]: Analyzing trace with hash 1342531000, now seen corresponding path program 1 times [2018-11-23 14:28:47,578 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:47,578 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:47,579 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:47,579 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:47,579 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:47,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:47,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:47,685 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:47,685 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 14:28:47,685 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 14:28:47,686 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 14:28:47,686 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:28:47,686 INFO L87 Difference]: Start difference. First operand 19521 states and 60007 transitions. Second operand 6 states. [2018-11-23 14:28:48,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:48,067 INFO L93 Difference]: Finished difference Result 22441 states and 66578 transitions. [2018-11-23 14:28:48,067 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 14:28:48,067 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2018-11-23 14:28:48,068 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:48,095 INFO L225 Difference]: With dead ends: 22441 [2018-11-23 14:28:48,096 INFO L226 Difference]: Without dead ends: 22441 [2018-11-23 14:28:48,096 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-11-23 14:28:48,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22441 states. [2018-11-23 14:28:48,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22441 to 20085. [2018-11-23 14:28:48,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20085 states. [2018-11-23 14:28:48,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20085 states to 20085 states and 60622 transitions. [2018-11-23 14:28:48,319 INFO L78 Accepts]: Start accepts. Automaton has 20085 states and 60622 transitions. Word has length 66 [2018-11-23 14:28:48,320 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:48,320 INFO L480 AbstractCegarLoop]: Abstraction has 20085 states and 60622 transitions. [2018-11-23 14:28:48,320 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 14:28:48,320 INFO L276 IsEmpty]: Start isEmpty. Operand 20085 states and 60622 transitions. [2018-11-23 14:28:48,326 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-11-23 14:28:48,326 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:48,326 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:48,326 INFO L423 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:48,326 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:48,326 INFO L82 PathProgramCache]: Analyzing trace with hash -1707671815, now seen corresponding path program 1 times [2018-11-23 14:28:48,326 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:48,326 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:48,328 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:48,328 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:48,328 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:48,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:48,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:48,399 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:48,399 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:28:48,399 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:28:48,399 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:28:48,399 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:28:48,399 INFO L87 Difference]: Start difference. First operand 20085 states and 60622 transitions. Second operand 5 states. [2018-11-23 14:28:48,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:48,617 INFO L93 Difference]: Finished difference Result 26432 states and 79262 transitions. [2018-11-23 14:28:48,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 14:28:48,617 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 66 [2018-11-23 14:28:48,617 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:48,647 INFO L225 Difference]: With dead ends: 26432 [2018-11-23 14:28:48,647 INFO L226 Difference]: Without dead ends: 26432 [2018-11-23 14:28:48,648 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:28:48,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26432 states. [2018-11-23 14:28:48,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26432 to 23813. [2018-11-23 14:28:48,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23813 states. [2018-11-23 14:28:48,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23813 states to 23813 states and 71372 transitions. [2018-11-23 14:28:48,906 INFO L78 Accepts]: Start accepts. Automaton has 23813 states and 71372 transitions. Word has length 66 [2018-11-23 14:28:48,906 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:48,906 INFO L480 AbstractCegarLoop]: Abstraction has 23813 states and 71372 transitions. [2018-11-23 14:28:48,906 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:28:48,906 INFO L276 IsEmpty]: Start isEmpty. Operand 23813 states and 71372 transitions. [2018-11-23 14:28:48,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-11-23 14:28:48,914 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:48,914 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:48,914 INFO L423 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:48,914 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:48,914 INFO L82 PathProgramCache]: Analyzing trace with hash 2076761304, now seen corresponding path program 1 times [2018-11-23 14:28:48,914 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:48,914 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:48,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:48,916 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:48,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:48,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:48,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:48,979 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:48,979 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:28:48,979 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:28:48,979 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:28:48,979 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:28:48,979 INFO L87 Difference]: Start difference. First operand 23813 states and 71372 transitions. Second operand 5 states. [2018-11-23 14:28:49,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:49,259 INFO L93 Difference]: Finished difference Result 33063 states and 98211 transitions. [2018-11-23 14:28:49,259 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 14:28:49,259 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 66 [2018-11-23 14:28:49,259 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:49,300 INFO L225 Difference]: With dead ends: 33063 [2018-11-23 14:28:49,300 INFO L226 Difference]: Without dead ends: 33063 [2018-11-23 14:28:49,301 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 14:28:49,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33063 states. [2018-11-23 14:28:49,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33063 to 29343. [2018-11-23 14:28:49,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29343 states. [2018-11-23 14:28:49,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29343 states to 29343 states and 87599 transitions. [2018-11-23 14:28:49,694 INFO L78 Accepts]: Start accepts. Automaton has 29343 states and 87599 transitions. Word has length 66 [2018-11-23 14:28:49,695 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:49,695 INFO L480 AbstractCegarLoop]: Abstraction has 29343 states and 87599 transitions. [2018-11-23 14:28:49,695 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:28:49,695 INFO L276 IsEmpty]: Start isEmpty. Operand 29343 states and 87599 transitions. [2018-11-23 14:28:49,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-11-23 14:28:49,705 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:49,705 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:49,706 INFO L423 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:49,706 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:49,706 INFO L82 PathProgramCache]: Analyzing trace with hash 269306841, now seen corresponding path program 1 times [2018-11-23 14:28:49,706 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:49,706 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:49,708 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:49,708 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:49,708 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:49,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:49,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:49,772 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:49,772 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:28:49,773 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:28:49,773 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:28:49,773 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:28:49,773 INFO L87 Difference]: Start difference. First operand 29343 states and 87599 transitions. Second operand 5 states. [2018-11-23 14:28:49,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:49,849 INFO L93 Difference]: Finished difference Result 9075 states and 21914 transitions. [2018-11-23 14:28:49,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:28:49,850 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 66 [2018-11-23 14:28:49,851 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:49,860 INFO L225 Difference]: With dead ends: 9075 [2018-11-23 14:28:49,860 INFO L226 Difference]: Without dead ends: 7223 [2018-11-23 14:28:49,861 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:28:49,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7223 states. [2018-11-23 14:28:49,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7223 to 6120. [2018-11-23 14:28:49,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6120 states. [2018-11-23 14:28:49,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6120 states to 6120 states and 14385 transitions. [2018-11-23 14:28:49,984 INFO L78 Accepts]: Start accepts. Automaton has 6120 states and 14385 transitions. Word has length 66 [2018-11-23 14:28:49,984 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:49,984 INFO L480 AbstractCegarLoop]: Abstraction has 6120 states and 14385 transitions. [2018-11-23 14:28:49,984 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:28:49,984 INFO L276 IsEmpty]: Start isEmpty. Operand 6120 states and 14385 transitions. [2018-11-23 14:28:49,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-11-23 14:28:49,988 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:49,988 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:49,988 INFO L423 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:49,988 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:49,989 INFO L82 PathProgramCache]: Analyzing trace with hash 1563910716, now seen corresponding path program 1 times [2018-11-23 14:28:49,989 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:49,989 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:49,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:49,990 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:49,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:49,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:50,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:50,010 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:50,011 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:28:50,011 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:28:50,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:28:50,011 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:28:50,011 INFO L87 Difference]: Start difference. First operand 6120 states and 14385 transitions. Second operand 3 states. [2018-11-23 14:28:50,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:50,046 INFO L93 Difference]: Finished difference Result 8339 states and 19492 transitions. [2018-11-23 14:28:50,046 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:28:50,046 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2018-11-23 14:28:50,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:50,052 INFO L225 Difference]: With dead ends: 8339 [2018-11-23 14:28:50,052 INFO L226 Difference]: Without dead ends: 8339 [2018-11-23 14:28:50,052 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:28:50,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8339 states. [2018-11-23 14:28:50,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8339 to 6059. [2018-11-23 14:28:50,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6059 states. [2018-11-23 14:28:50,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6059 states to 6059 states and 13925 transitions. [2018-11-23 14:28:50,103 INFO L78 Accepts]: Start accepts. Automaton has 6059 states and 13925 transitions. Word has length 66 [2018-11-23 14:28:50,104 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:50,104 INFO L480 AbstractCegarLoop]: Abstraction has 6059 states and 13925 transitions. [2018-11-23 14:28:50,104 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:28:50,104 INFO L276 IsEmpty]: Start isEmpty. Operand 6059 states and 13925 transitions. [2018-11-23 14:28:50,108 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-23 14:28:50,108 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:50,108 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:50,109 INFO L423 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:50,109 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:50,109 INFO L82 PathProgramCache]: Analyzing trace with hash 1344844335, now seen corresponding path program 1 times [2018-11-23 14:28:50,109 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:50,109 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:50,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:50,110 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:50,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:50,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:50,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:50,185 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:50,185 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:28:50,185 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:28:50,185 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:28:50,185 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:28:50,185 INFO L87 Difference]: Start difference. First operand 6059 states and 13925 transitions. Second operand 5 states. [2018-11-23 14:28:50,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:50,335 INFO L93 Difference]: Finished difference Result 7229 states and 16566 transitions. [2018-11-23 14:28:50,335 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 14:28:50,335 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 72 [2018-11-23 14:28:50,335 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:50,342 INFO L225 Difference]: With dead ends: 7229 [2018-11-23 14:28:50,342 INFO L226 Difference]: Without dead ends: 7229 [2018-11-23 14:28:50,342 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-23 14:28:50,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7229 states. [2018-11-23 14:28:50,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7229 to 6503. [2018-11-23 14:28:50,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6503 states. [2018-11-23 14:28:50,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6503 states to 6503 states and 14929 transitions. [2018-11-23 14:28:50,410 INFO L78 Accepts]: Start accepts. Automaton has 6503 states and 14929 transitions. Word has length 72 [2018-11-23 14:28:50,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:50,410 INFO L480 AbstractCegarLoop]: Abstraction has 6503 states and 14929 transitions. [2018-11-23 14:28:50,410 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:28:50,410 INFO L276 IsEmpty]: Start isEmpty. Operand 6503 states and 14929 transitions. [2018-11-23 14:28:50,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-23 14:28:50,414 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:50,414 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:50,415 INFO L423 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:50,415 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:50,415 INFO L82 PathProgramCache]: Analyzing trace with hash -1207312626, now seen corresponding path program 1 times [2018-11-23 14:28:50,415 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:50,415 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:50,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:50,416 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:50,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:50,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:50,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:50,531 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:50,531 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-23 14:28:50,531 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 14:28:50,531 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 14:28:50,531 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-11-23 14:28:50,532 INFO L87 Difference]: Start difference. First operand 6503 states and 14929 transitions. Second operand 9 states. [2018-11-23 14:28:50,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:50,888 INFO L93 Difference]: Finished difference Result 8529 states and 19410 transitions. [2018-11-23 14:28:50,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 14:28:50,889 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 72 [2018-11-23 14:28:50,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:50,895 INFO L225 Difference]: With dead ends: 8529 [2018-11-23 14:28:50,896 INFO L226 Difference]: Without dead ends: 8410 [2018-11-23 14:28:50,896 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 46 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=74, Invalid=232, Unknown=0, NotChecked=0, Total=306 [2018-11-23 14:28:50,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8410 states. [2018-11-23 14:28:50,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8410 to 6600. [2018-11-23 14:28:50,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6600 states. [2018-11-23 14:28:50,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6600 states to 6600 states and 15022 transitions. [2018-11-23 14:28:50,963 INFO L78 Accepts]: Start accepts. Automaton has 6600 states and 15022 transitions. Word has length 72 [2018-11-23 14:28:50,963 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:50,964 INFO L480 AbstractCegarLoop]: Abstraction has 6600 states and 15022 transitions. [2018-11-23 14:28:50,964 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 14:28:50,964 INFO L276 IsEmpty]: Start isEmpty. Operand 6600 states and 15022 transitions. [2018-11-23 14:28:50,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-11-23 14:28:50,970 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:50,970 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:50,970 INFO L423 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:50,970 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:50,971 INFO L82 PathProgramCache]: Analyzing trace with hash 1119414586, now seen corresponding path program 1 times [2018-11-23 14:28:50,971 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:50,971 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:50,972 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:50,972 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:50,972 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:50,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:51,013 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:51,013 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:51,013 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 14:28:51,013 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 14:28:51,014 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 14:28:51,014 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:28:51,014 INFO L87 Difference]: Start difference. First operand 6600 states and 15022 transitions. Second operand 4 states. [2018-11-23 14:28:51,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:51,189 INFO L93 Difference]: Finished difference Result 10287 states and 23293 transitions. [2018-11-23 14:28:51,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 14:28:51,189 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 91 [2018-11-23 14:28:51,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:51,197 INFO L225 Difference]: With dead ends: 10287 [2018-11-23 14:28:51,197 INFO L226 Difference]: Without dead ends: 10287 [2018-11-23 14:28:51,198 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:28:51,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10287 states. [2018-11-23 14:28:51,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10287 to 7720. [2018-11-23 14:28:51,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7720 states. [2018-11-23 14:28:51,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7720 states to 7720 states and 17356 transitions. [2018-11-23 14:28:51,280 INFO L78 Accepts]: Start accepts. Automaton has 7720 states and 17356 transitions. Word has length 91 [2018-11-23 14:28:51,280 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:51,280 INFO L480 AbstractCegarLoop]: Abstraction has 7720 states and 17356 transitions. [2018-11-23 14:28:51,280 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 14:28:51,280 INFO L276 IsEmpty]: Start isEmpty. Operand 7720 states and 17356 transitions. [2018-11-23 14:28:51,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-11-23 14:28:51,287 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:51,287 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:51,288 INFO L423 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:51,288 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:51,288 INFO L82 PathProgramCache]: Analyzing trace with hash -1265743780, now seen corresponding path program 1 times [2018-11-23 14:28:51,288 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:51,288 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:51,290 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:51,290 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:51,290 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:51,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:51,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:51,345 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:51,345 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 14:28:51,345 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 14:28:51,345 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 14:28:51,346 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:28:51,346 INFO L87 Difference]: Start difference. First operand 7720 states and 17356 transitions. Second operand 4 states. [2018-11-23 14:28:51,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:51,416 INFO L93 Difference]: Finished difference Result 8285 states and 18649 transitions. [2018-11-23 14:28:51,417 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 14:28:51,417 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 91 [2018-11-23 14:28:51,417 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:51,423 INFO L225 Difference]: With dead ends: 8285 [2018-11-23 14:28:51,423 INFO L226 Difference]: Without dead ends: 8285 [2018-11-23 14:28:51,423 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:28:51,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8285 states. [2018-11-23 14:28:51,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8285 to 7626. [2018-11-23 14:28:51,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7626 states. [2018-11-23 14:28:51,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7626 states to 7626 states and 17251 transitions. [2018-11-23 14:28:51,495 INFO L78 Accepts]: Start accepts. Automaton has 7626 states and 17251 transitions. Word has length 91 [2018-11-23 14:28:51,496 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:51,496 INFO L480 AbstractCegarLoop]: Abstraction has 7626 states and 17251 transitions. [2018-11-23 14:28:51,496 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 14:28:51,496 INFO L276 IsEmpty]: Start isEmpty. Operand 7626 states and 17251 transitions. [2018-11-23 14:28:51,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 14:28:51,502 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:51,502 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:51,503 INFO L423 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:51,503 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:51,503 INFO L82 PathProgramCache]: Analyzing trace with hash -248736448, now seen corresponding path program 1 times [2018-11-23 14:28:51,503 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:51,503 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:51,504 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:51,504 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:51,504 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:51,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:51,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:51,587 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:51,587 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 14:28:51,587 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 14:28:51,587 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 14:28:51,587 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:28:51,587 INFO L87 Difference]: Start difference. First operand 7626 states and 17251 transitions. Second operand 7 states. [2018-11-23 14:28:52,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:52,087 INFO L93 Difference]: Finished difference Result 9400 states and 21199 transitions. [2018-11-23 14:28:52,087 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 14:28:52,088 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 93 [2018-11-23 14:28:52,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:52,099 INFO L225 Difference]: With dead ends: 9400 [2018-11-23 14:28:52,099 INFO L226 Difference]: Without dead ends: 9400 [2018-11-23 14:28:52,099 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:28:52,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9400 states. [2018-11-23 14:28:52,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9400 to 7738. [2018-11-23 14:28:52,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7738 states. [2018-11-23 14:28:52,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7738 states to 7738 states and 17571 transitions. [2018-11-23 14:28:52,210 INFO L78 Accepts]: Start accepts. Automaton has 7738 states and 17571 transitions. Word has length 93 [2018-11-23 14:28:52,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:52,210 INFO L480 AbstractCegarLoop]: Abstraction has 7738 states and 17571 transitions. [2018-11-23 14:28:52,211 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 14:28:52,211 INFO L276 IsEmpty]: Start isEmpty. Operand 7738 states and 17571 transitions. [2018-11-23 14:28:52,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 14:28:52,220 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:52,220 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:52,220 INFO L423 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:52,220 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:52,222 INFO L82 PathProgramCache]: Analyzing trace with hash 190059557, now seen corresponding path program 1 times [2018-11-23 14:28:52,222 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:52,223 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:52,224 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:52,224 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:52,224 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:52,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:52,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:52,286 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:52,286 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:28:52,287 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:28:52,287 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:28:52,287 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:28:52,287 INFO L87 Difference]: Start difference. First operand 7738 states and 17571 transitions. Second operand 5 states. [2018-11-23 14:28:52,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:52,407 INFO L93 Difference]: Finished difference Result 8645 states and 19529 transitions. [2018-11-23 14:28:52,407 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 14:28:52,407 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 93 [2018-11-23 14:28:52,408 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:52,414 INFO L225 Difference]: With dead ends: 8645 [2018-11-23 14:28:52,414 INFO L226 Difference]: Without dead ends: 8645 [2018-11-23 14:28:52,415 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:28:52,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8645 states. [2018-11-23 14:28:52,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8645 to 6634. [2018-11-23 14:28:52,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6634 states. [2018-11-23 14:28:52,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6634 states to 6634 states and 15090 transitions. [2018-11-23 14:28:52,480 INFO L78 Accepts]: Start accepts. Automaton has 6634 states and 15090 transitions. Word has length 93 [2018-11-23 14:28:52,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:52,481 INFO L480 AbstractCegarLoop]: Abstraction has 6634 states and 15090 transitions. [2018-11-23 14:28:52,481 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:28:52,481 INFO L276 IsEmpty]: Start isEmpty. Operand 6634 states and 15090 transitions. [2018-11-23 14:28:52,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 14:28:52,487 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:52,487 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:52,487 INFO L423 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:52,487 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:52,488 INFO L82 PathProgramCache]: Analyzing trace with hash -64676988, now seen corresponding path program 1 times [2018-11-23 14:28:52,488 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:52,488 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:52,489 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:52,489 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:52,489 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:52,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:52,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:52,554 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:52,555 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:28:52,555 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:28:52,555 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:28:52,555 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:28:52,555 INFO L87 Difference]: Start difference. First operand 6634 states and 15090 transitions. Second operand 5 states. [2018-11-23 14:28:52,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:52,800 INFO L93 Difference]: Finished difference Result 7882 states and 17730 transitions. [2018-11-23 14:28:52,801 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:28:52,801 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 93 [2018-11-23 14:28:52,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:52,807 INFO L225 Difference]: With dead ends: 7882 [2018-11-23 14:28:52,807 INFO L226 Difference]: Without dead ends: 7751 [2018-11-23 14:28:52,808 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:28:52,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7751 states. [2018-11-23 14:28:52,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7751 to 7373. [2018-11-23 14:28:52,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7373 states. [2018-11-23 14:28:52,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7373 states to 7373 states and 16709 transitions. [2018-11-23 14:28:52,899 INFO L78 Accepts]: Start accepts. Automaton has 7373 states and 16709 transitions. Word has length 93 [2018-11-23 14:28:52,899 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:52,899 INFO L480 AbstractCegarLoop]: Abstraction has 7373 states and 16709 transitions. [2018-11-23 14:28:52,899 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:28:52,899 INFO L276 IsEmpty]: Start isEmpty. Operand 7373 states and 16709 transitions. [2018-11-23 14:28:52,903 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 14:28:52,903 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:52,904 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:52,904 INFO L423 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:52,904 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:52,904 INFO L82 PathProgramCache]: Analyzing trace with hash 1180087493, now seen corresponding path program 1 times [2018-11-23 14:28:52,904 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:52,904 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:52,905 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:52,905 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:52,905 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:52,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:52,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:52,972 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:52,972 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 14:28:52,973 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 14:28:52,973 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 14:28:52,973 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:28:52,973 INFO L87 Difference]: Start difference. First operand 7373 states and 16709 transitions. Second operand 6 states. [2018-11-23 14:28:53,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:53,164 INFO L93 Difference]: Finished difference Result 9406 states and 21103 transitions. [2018-11-23 14:28:53,165 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 14:28:53,165 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 93 [2018-11-23 14:28:53,165 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:53,171 INFO L225 Difference]: With dead ends: 9406 [2018-11-23 14:28:53,171 INFO L226 Difference]: Without dead ends: 9298 [2018-11-23 14:28:53,171 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2018-11-23 14:28:53,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9298 states. [2018-11-23 14:28:53,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9298 to 7200. [2018-11-23 14:28:53,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7200 states. [2018-11-23 14:28:53,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7200 states to 7200 states and 16315 transitions. [2018-11-23 14:28:53,231 INFO L78 Accepts]: Start accepts. Automaton has 7200 states and 16315 transitions. Word has length 93 [2018-11-23 14:28:53,231 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:53,231 INFO L480 AbstractCegarLoop]: Abstraction has 7200 states and 16315 transitions. [2018-11-23 14:28:53,231 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 14:28:53,231 INFO L276 IsEmpty]: Start isEmpty. Operand 7200 states and 16315 transitions. [2018-11-23 14:28:53,236 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 14:28:53,236 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:53,236 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:53,236 INFO L423 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:53,236 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:53,236 INFO L82 PathProgramCache]: Analyzing trace with hash 86477922, now seen corresponding path program 1 times [2018-11-23 14:28:53,236 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:53,236 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:53,237 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:53,237 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:53,237 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:53,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:53,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:53,330 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:53,330 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-23 14:28:53,330 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 14:28:53,330 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 14:28:53,330 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2018-11-23 14:28:53,330 INFO L87 Difference]: Start difference. First operand 7200 states and 16315 transitions. Second operand 9 states. [2018-11-23 14:28:53,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:53,694 INFO L93 Difference]: Finished difference Result 10191 states and 23070 transitions. [2018-11-23 14:28:53,695 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-23 14:28:53,695 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 93 [2018-11-23 14:28:53,695 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:53,702 INFO L225 Difference]: With dead ends: 10191 [2018-11-23 14:28:53,702 INFO L226 Difference]: Without dead ends: 10159 [2018-11-23 14:28:53,702 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=61, Invalid=245, Unknown=0, NotChecked=0, Total=306 [2018-11-23 14:28:53,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10159 states. [2018-11-23 14:28:53,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10159 to 9008. [2018-11-23 14:28:53,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9008 states. [2018-11-23 14:28:53,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9008 states to 9008 states and 20407 transitions. [2018-11-23 14:28:53,772 INFO L78 Accepts]: Start accepts. Automaton has 9008 states and 20407 transitions. Word has length 93 [2018-11-23 14:28:53,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:53,773 INFO L480 AbstractCegarLoop]: Abstraction has 9008 states and 20407 transitions. [2018-11-23 14:28:53,773 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 14:28:53,773 INFO L276 IsEmpty]: Start isEmpty. Operand 9008 states and 20407 transitions. [2018-11-23 14:28:53,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 14:28:53,778 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:53,778 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:53,779 INFO L423 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:53,779 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:53,779 INFO L82 PathProgramCache]: Analyzing trace with hash -1710473437, now seen corresponding path program 1 times [2018-11-23 14:28:53,779 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:53,779 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:53,780 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:53,780 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:53,780 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:53,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:53,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:53,848 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:53,848 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 14:28:53,848 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 14:28:53,848 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 14:28:53,848 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-11-23 14:28:53,848 INFO L87 Difference]: Start difference. First operand 9008 states and 20407 transitions. Second operand 8 states. [2018-11-23 14:28:54,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:54,118 INFO L93 Difference]: Finished difference Result 14357 states and 33169 transitions. [2018-11-23 14:28:54,119 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-23 14:28:54,119 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 93 [2018-11-23 14:28:54,119 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:54,129 INFO L225 Difference]: With dead ends: 14357 [2018-11-23 14:28:54,129 INFO L226 Difference]: Without dead ends: 14357 [2018-11-23 14:28:54,129 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2018-11-23 14:28:54,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14357 states. [2018-11-23 14:28:54,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14357 to 9634. [2018-11-23 14:28:54,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9634 states. [2018-11-23 14:28:54,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9634 states to 9634 states and 22044 transitions. [2018-11-23 14:28:54,227 INFO L78 Accepts]: Start accepts. Automaton has 9634 states and 22044 transitions. Word has length 93 [2018-11-23 14:28:54,227 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:54,227 INFO L480 AbstractCegarLoop]: Abstraction has 9634 states and 22044 transitions. [2018-11-23 14:28:54,227 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 14:28:54,227 INFO L276 IsEmpty]: Start isEmpty. Operand 9634 states and 22044 transitions. [2018-11-23 14:28:54,234 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 14:28:54,234 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:54,234 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:54,234 INFO L423 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:54,235 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:54,235 INFO L82 PathProgramCache]: Analyzing trace with hash -822969756, now seen corresponding path program 1 times [2018-11-23 14:28:54,235 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:54,235 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:54,236 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:54,236 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:54,236 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:54,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:54,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:54,270 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:54,270 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:28:54,270 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:28:54,270 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:28:54,270 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:28:54,271 INFO L87 Difference]: Start difference. First operand 9634 states and 22044 transitions. Second operand 3 states. [2018-11-23 14:28:54,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:54,300 INFO L93 Difference]: Finished difference Result 9378 states and 21228 transitions. [2018-11-23 14:28:54,300 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:28:54,301 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 93 [2018-11-23 14:28:54,301 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:54,308 INFO L225 Difference]: With dead ends: 9378 [2018-11-23 14:28:54,308 INFO L226 Difference]: Without dead ends: 9346 [2018-11-23 14:28:54,308 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:28:54,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9346 states. [2018-11-23 14:28:54,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9346 to 7511. [2018-11-23 14:28:54,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7511 states. [2018-11-23 14:28:54,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7511 states to 7511 states and 16863 transitions. [2018-11-23 14:28:54,380 INFO L78 Accepts]: Start accepts. Automaton has 7511 states and 16863 transitions. Word has length 93 [2018-11-23 14:28:54,380 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:54,380 INFO L480 AbstractCegarLoop]: Abstraction has 7511 states and 16863 transitions. [2018-11-23 14:28:54,380 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:28:54,380 INFO L276 IsEmpty]: Start isEmpty. Operand 7511 states and 16863 transitions. [2018-11-23 14:28:54,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-23 14:28:54,385 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:54,385 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:54,386 INFO L423 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:54,386 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:54,386 INFO L82 PathProgramCache]: Analyzing trace with hash 461346830, now seen corresponding path program 1 times [2018-11-23 14:28:54,386 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:54,386 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:54,387 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:54,387 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:54,387 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:54,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:54,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:54,521 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:54,521 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-23 14:28:54,521 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-23 14:28:54,521 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-23 14:28:54,521 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2018-11-23 14:28:54,522 INFO L87 Difference]: Start difference. First operand 7511 states and 16863 transitions. Second operand 10 states. [2018-11-23 14:28:54,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:54,994 INFO L93 Difference]: Finished difference Result 9932 states and 22168 transitions. [2018-11-23 14:28:54,995 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-23 14:28:54,995 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 95 [2018-11-23 14:28:54,995 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:55,001 INFO L225 Difference]: With dead ends: 9932 [2018-11-23 14:28:55,001 INFO L226 Difference]: Without dead ends: 9932 [2018-11-23 14:28:55,001 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=69, Invalid=273, Unknown=0, NotChecked=0, Total=342 [2018-11-23 14:28:55,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9932 states. [2018-11-23 14:28:55,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9932 to 8732. [2018-11-23 14:28:55,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8732 states. [2018-11-23 14:28:55,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8732 states to 8732 states and 19527 transitions. [2018-11-23 14:28:55,070 INFO L78 Accepts]: Start accepts. Automaton has 8732 states and 19527 transitions. Word has length 95 [2018-11-23 14:28:55,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:55,071 INFO L480 AbstractCegarLoop]: Abstraction has 8732 states and 19527 transitions. [2018-11-23 14:28:55,071 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-23 14:28:55,071 INFO L276 IsEmpty]: Start isEmpty. Operand 8732 states and 19527 transitions. [2018-11-23 14:28:55,076 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-23 14:28:55,076 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:55,076 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:55,076 INFO L423 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:55,076 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:55,076 INFO L82 PathProgramCache]: Analyzing trace with hash 1348850511, now seen corresponding path program 1 times [2018-11-23 14:28:55,076 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:55,076 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:55,077 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:55,077 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:55,077 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:55,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:55,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:55,184 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:55,184 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-23 14:28:55,184 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 14:28:55,185 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 14:28:55,185 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-11-23 14:28:55,185 INFO L87 Difference]: Start difference. First operand 8732 states and 19527 transitions. Second operand 9 states. [2018-11-23 14:28:55,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:55,573 INFO L93 Difference]: Finished difference Result 10680 states and 23668 transitions. [2018-11-23 14:28:55,573 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-23 14:28:55,573 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 95 [2018-11-23 14:28:55,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:55,581 INFO L225 Difference]: With dead ends: 10680 [2018-11-23 14:28:55,581 INFO L226 Difference]: Without dead ends: 10680 [2018-11-23 14:28:55,581 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 3 SyntacticMatches, 5 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 54 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=100, Invalid=320, Unknown=0, NotChecked=0, Total=420 [2018-11-23 14:28:55,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10680 states. [2018-11-23 14:28:55,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10680 to 9212. [2018-11-23 14:28:55,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9212 states. [2018-11-23 14:28:55,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9212 states to 9212 states and 20534 transitions. [2018-11-23 14:28:55,656 INFO L78 Accepts]: Start accepts. Automaton has 9212 states and 20534 transitions. Word has length 95 [2018-11-23 14:28:55,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:55,656 INFO L480 AbstractCegarLoop]: Abstraction has 9212 states and 20534 transitions. [2018-11-23 14:28:55,656 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 14:28:55,656 INFO L276 IsEmpty]: Start isEmpty. Operand 9212 states and 20534 transitions. [2018-11-23 14:28:55,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-23 14:28:55,662 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:55,662 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:55,662 INFO L423 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:55,662 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:55,663 INFO L82 PathProgramCache]: Analyzing trace with hash 672697743, now seen corresponding path program 1 times [2018-11-23 14:28:55,663 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:55,663 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:55,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:55,663 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:55,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:55,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:55,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:55,720 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:55,720 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:28:55,720 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:28:55,720 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:28:55,720 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:28:55,720 INFO L87 Difference]: Start difference. First operand 9212 states and 20534 transitions. Second operand 5 states. [2018-11-23 14:28:55,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:55,763 INFO L93 Difference]: Finished difference Result 9212 states and 20470 transitions. [2018-11-23 14:28:55,763 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:28:55,763 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 95 [2018-11-23 14:28:55,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:55,769 INFO L225 Difference]: With dead ends: 9212 [2018-11-23 14:28:55,769 INFO L226 Difference]: Without dead ends: 9212 [2018-11-23 14:28:55,769 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:28:55,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9212 states. [2018-11-23 14:28:55,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9212 to 6217. [2018-11-23 14:28:55,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6217 states. [2018-11-23 14:28:55,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6217 states to 6217 states and 13837 transitions. [2018-11-23 14:28:55,842 INFO L78 Accepts]: Start accepts. Automaton has 6217 states and 13837 transitions. Word has length 95 [2018-11-23 14:28:55,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:55,842 INFO L480 AbstractCegarLoop]: Abstraction has 6217 states and 13837 transitions. [2018-11-23 14:28:55,842 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:28:55,842 INFO L276 IsEmpty]: Start isEmpty. Operand 6217 states and 13837 transitions. [2018-11-23 14:28:55,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-23 14:28:55,847 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:55,847 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:55,847 INFO L423 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:55,847 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:55,847 INFO L82 PathProgramCache]: Analyzing trace with hash 1560201424, now seen corresponding path program 1 times [2018-11-23 14:28:55,848 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:55,848 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:55,848 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:55,849 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:55,849 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:55,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:56,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:56,040 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:56,041 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-11-23 14:28:56,041 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-23 14:28:56,041 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-23 14:28:56,041 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-11-23 14:28:56,041 INFO L87 Difference]: Start difference. First operand 6217 states and 13837 transitions. Second operand 11 states. [2018-11-23 14:28:57,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:57,120 INFO L93 Difference]: Finished difference Result 11284 states and 25232 transitions. [2018-11-23 14:28:57,120 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 14:28:57,120 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 95 [2018-11-23 14:28:57,120 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:57,148 INFO L225 Difference]: With dead ends: 11284 [2018-11-23 14:28:57,148 INFO L226 Difference]: Without dead ends: 7970 [2018-11-23 14:28:57,149 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 44 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=86, Invalid=376, Unknown=0, NotChecked=0, Total=462 [2018-11-23 14:28:57,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7970 states. [2018-11-23 14:28:57,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7970 to 6049. [2018-11-23 14:28:57,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6049 states. [2018-11-23 14:28:57,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6049 states to 6049 states and 13423 transitions. [2018-11-23 14:28:57,193 INFO L78 Accepts]: Start accepts. Automaton has 6049 states and 13423 transitions. Word has length 95 [2018-11-23 14:28:57,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:57,193 INFO L480 AbstractCegarLoop]: Abstraction has 6049 states and 13423 transitions. [2018-11-23 14:28:57,193 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-23 14:28:57,193 INFO L276 IsEmpty]: Start isEmpty. Operand 6049 states and 13423 transitions. [2018-11-23 14:28:57,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-23 14:28:57,197 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:57,197 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:57,197 INFO L423 AbstractCegarLoop]: === Iteration 32 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:57,197 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:57,197 INFO L82 PathProgramCache]: Analyzing trace with hash -1172529568, now seen corresponding path program 1 times [2018-11-23 14:28:57,197 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:57,197 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:57,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:57,198 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:57,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:57,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:57,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:57,301 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:57,302 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 14:28:57,302 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 14:28:57,302 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 14:28:57,302 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:28:57,302 INFO L87 Difference]: Start difference. First operand 6049 states and 13423 transitions. Second operand 7 states. [2018-11-23 14:28:57,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:57,594 INFO L93 Difference]: Finished difference Result 7475 states and 16378 transitions. [2018-11-23 14:28:57,594 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 14:28:57,594 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 95 [2018-11-23 14:28:57,594 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:57,599 INFO L225 Difference]: With dead ends: 7475 [2018-11-23 14:28:57,599 INFO L226 Difference]: Without dead ends: 7437 [2018-11-23 14:28:57,599 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=39, Invalid=93, Unknown=0, NotChecked=0, Total=132 [2018-11-23 14:28:57,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7437 states. [2018-11-23 14:28:57,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7437 to 6381. [2018-11-23 14:28:57,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6381 states. [2018-11-23 14:28:57,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6381 states to 6381 states and 14093 transitions. [2018-11-23 14:28:57,648 INFO L78 Accepts]: Start accepts. Automaton has 6381 states and 14093 transitions. Word has length 95 [2018-11-23 14:28:57,648 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:57,648 INFO L480 AbstractCegarLoop]: Abstraction has 6381 states and 14093 transitions. [2018-11-23 14:28:57,648 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 14:28:57,648 INFO L276 IsEmpty]: Start isEmpty. Operand 6381 states and 14093 transitions. [2018-11-23 14:28:57,652 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-23 14:28:57,652 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:57,652 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:57,652 INFO L423 AbstractCegarLoop]: === Iteration 33 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:57,652 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:57,652 INFO L82 PathProgramCache]: Analyzing trace with hash -1509000320, now seen corresponding path program 2 times [2018-11-23 14:28:57,652 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:57,652 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:57,653 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:57,653 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:57,653 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:57,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:57,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:57,775 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:57,775 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 14:28:57,775 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 14:28:57,775 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 14:28:57,775 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:28:57,776 INFO L87 Difference]: Start difference. First operand 6381 states and 14093 transitions. Second operand 7 states. [2018-11-23 14:28:58,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:58,093 INFO L93 Difference]: Finished difference Result 8569 states and 18644 transitions. [2018-11-23 14:28:58,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 14:28:58,094 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 95 [2018-11-23 14:28:58,094 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:58,101 INFO L225 Difference]: With dead ends: 8569 [2018-11-23 14:28:58,101 INFO L226 Difference]: Without dead ends: 8569 [2018-11-23 14:28:58,102 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=57, Invalid=125, Unknown=0, NotChecked=0, Total=182 [2018-11-23 14:28:58,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8569 states. [2018-11-23 14:28:58,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8569 to 6937. [2018-11-23 14:28:58,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6937 states. [2018-11-23 14:28:58,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6937 states to 6937 states and 15331 transitions. [2018-11-23 14:28:58,162 INFO L78 Accepts]: Start accepts. Automaton has 6937 states and 15331 transitions. Word has length 95 [2018-11-23 14:28:58,162 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:58,162 INFO L480 AbstractCegarLoop]: Abstraction has 6937 states and 15331 transitions. [2018-11-23 14:28:58,162 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 14:28:58,162 INFO L276 IsEmpty]: Start isEmpty. Operand 6937 states and 15331 transitions. [2018-11-23 14:28:58,167 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-23 14:28:58,167 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:58,167 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:58,167 INFO L423 AbstractCegarLoop]: === Iteration 34 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:58,167 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:58,168 INFO L82 PathProgramCache]: Analyzing trace with hash -1297649407, now seen corresponding path program 1 times [2018-11-23 14:28:58,168 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:58,168 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:58,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:58,169 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:28:58,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:58,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:58,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:58,220 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:58,221 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 14:28:58,221 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 14:28:58,221 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 14:28:58,221 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:28:58,221 INFO L87 Difference]: Start difference. First operand 6937 states and 15331 transitions. Second operand 6 states. [2018-11-23 14:28:58,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:58,337 INFO L93 Difference]: Finished difference Result 7396 states and 16259 transitions. [2018-11-23 14:28:58,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 14:28:58,337 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 95 [2018-11-23 14:28:58,337 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:58,342 INFO L225 Difference]: With dead ends: 7396 [2018-11-23 14:28:58,342 INFO L226 Difference]: Without dead ends: 7396 [2018-11-23 14:28:58,342 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-11-23 14:28:58,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7396 states. [2018-11-23 14:28:58,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7396 to 6782. [2018-11-23 14:28:58,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6782 states. [2018-11-23 14:28:58,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6782 states to 6782 states and 14968 transitions. [2018-11-23 14:28:58,393 INFO L78 Accepts]: Start accepts. Automaton has 6782 states and 14968 transitions. Word has length 95 [2018-11-23 14:28:58,394 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:58,394 INFO L480 AbstractCegarLoop]: Abstraction has 6782 states and 14968 transitions. [2018-11-23 14:28:58,394 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 14:28:58,394 INFO L276 IsEmpty]: Start isEmpty. Operand 6782 states and 14968 transitions. [2018-11-23 14:28:58,398 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-23 14:28:58,398 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:58,398 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:58,398 INFO L423 AbstractCegarLoop]: === Iteration 35 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:58,398 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:58,398 INFO L82 PathProgramCache]: Analyzing trace with hash -842763807, now seen corresponding path program 2 times [2018-11-23 14:28:58,398 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:58,398 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:58,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:58,399 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:28:58,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:58,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:28:58,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:28:58,493 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:28:58,493 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 14:28:58,494 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 14:28:58,494 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 14:28:58,494 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-11-23 14:28:58,494 INFO L87 Difference]: Start difference. First operand 6782 states and 14968 transitions. Second operand 8 states. [2018-11-23 14:28:58,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:28:58,731 INFO L93 Difference]: Finished difference Result 8474 states and 18527 transitions. [2018-11-23 14:28:58,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-23 14:28:58,731 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 95 [2018-11-23 14:28:58,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:28:58,737 INFO L225 Difference]: With dead ends: 8474 [2018-11-23 14:28:58,737 INFO L226 Difference]: Without dead ends: 8474 [2018-11-23 14:28:58,737 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 2 SyntacticMatches, 5 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=53, Invalid=157, Unknown=0, NotChecked=0, Total=210 [2018-11-23 14:28:58,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8474 states. [2018-11-23 14:28:58,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8474 to 6846. [2018-11-23 14:28:58,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6846 states. [2018-11-23 14:28:58,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6846 states to 6846 states and 15125 transitions. [2018-11-23 14:28:58,792 INFO L78 Accepts]: Start accepts. Automaton has 6846 states and 15125 transitions. Word has length 95 [2018-11-23 14:28:58,792 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:28:58,792 INFO L480 AbstractCegarLoop]: Abstraction has 6846 states and 15125 transitions. [2018-11-23 14:28:58,792 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 14:28:58,792 INFO L276 IsEmpty]: Start isEmpty. Operand 6846 states and 15125 transitions. [2018-11-23 14:28:58,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-23 14:28:58,797 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:28:58,797 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:28:58,797 INFO L423 AbstractCegarLoop]: === Iteration 36 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:28:58,797 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:28:58,798 INFO L82 PathProgramCache]: Analyzing trace with hash -631412894, now seen corresponding path program 2 times [2018-11-23 14:28:58,798 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:28:58,798 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:28:58,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:58,799 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:28:58,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:28:58,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:28:58,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:28:58,840 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [478] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [358] L-1-->L671: Formula: (= |v_#valid_9| (store |v_#valid_10| 0 0)) InVars {#valid=|v_#valid_10|} OutVars{#valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [517] L671-->L673: Formula: (= v_~__unbuffered_cnt~0_6 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [381] L673-->L675: Formula: (= v_~__unbuffered_p1_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [422] L675-->L676: Formula: (= v_~__unbuffered_p1_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 [350] L676-->L677: Formula: (= v_~main$tmp_guard0~0_3 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 [482] L677-->L679: Formula: (= v_~main$tmp_guard1~0_1 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_1} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [524] L679-->L680: Formula: (= v_~x~0_11 0) InVars {} OutVars{~x~0=v_~x~0_11} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [464] L680-->L681: Formula: (= v_~x$flush_delayed~0_5 0) InVars {} OutVars{~x$flush_delayed~0=v_~x$flush_delayed~0_5} AuxVars[] AssignedVars[~x$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 [386] L681-->L682: Formula: (= v_~x$mem_tmp~0_3 0) InVars {} OutVars{~x$mem_tmp~0=v_~x$mem_tmp~0_3} AuxVars[] AssignedVars[~x$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 [514] L682-->L683: Formula: (= v_~x$r_buff0_thd0~0_2 0) InVars {} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_2} AuxVars[] AssignedVars[~x$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 [453] L683-->L684: Formula: (= v_~x$r_buff0_thd1~0_14 0) InVars {} OutVars{~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_14} AuxVars[] AssignedVars[~x$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 [380] L684-->L685: Formula: (= v_~x$r_buff0_thd2~0_43 0) InVars {} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_43} AuxVars[] AssignedVars[~x$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 [492] L685-->L686: Formula: (= v_~x$r_buff1_thd0~0_2 0) InVars {} OutVars{~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_2} AuxVars[] AssignedVars[~x$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 [419] L686-->L687: Formula: (= v_~x$r_buff1_thd1~0_9 0) InVars {} OutVars{~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_9} AuxVars[] AssignedVars[~x$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 [373] L687-->L688: Formula: (= v_~x$r_buff1_thd2~0_25 0) InVars {} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_25} AuxVars[] AssignedVars[~x$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 [481] L688-->L689: Formula: (= v_~x$read_delayed~0_1 0) InVars {} OutVars{~x$read_delayed~0=v_~x$read_delayed~0_1} AuxVars[] AssignedVars[~x$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 [416] L689-->L690: Formula: (and (= v_~x$read_delayed_var~0.offset_1 0) (= v_~x$read_delayed_var~0.base_1 0)) InVars {} OutVars{~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_1, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~x$read_delayed_var~0.offset, ~x$read_delayed_var~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 [523] L690-->L691: Formula: (= v_~x$w_buff0~0_11 0) InVars {} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_11} AuxVars[] AssignedVars[~x$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 [461] L691-->L692: Formula: (= v_~x$w_buff0_used~0_55 0) InVars {} OutVars{~x$w_buff0_used~0=v_~x$w_buff0_used~0_55} AuxVars[] AssignedVars[~x$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 [385] L692-->L693: Formula: (= v_~x$w_buff1~0_10 0) InVars {} OutVars{~x$w_buff1~0=v_~x$w_buff1~0_10} AuxVars[] AssignedVars[~x$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 [512] L693-->L695: Formula: (= v_~x$w_buff1_used~0_32 0) InVars {} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_32} AuxVars[] AssignedVars[~x$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 [379] L695-->L696: Formula: (= v_~y~0_3 0) InVars {} OutVars{~y~0=v_~y~0_3} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [491] L696-->L697: Formula: (= v_~weak$$choice0~0_2 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_2} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [418] L697-->L-1-1: Formula: (= v_~weak$$choice2~0_14 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_14} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [513] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [511] L-1-2-->L773: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_1|, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_1|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_1|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_1|, ULTIMATE.start_main_~#t1712~0.offset=|v_ULTIMATE.start_main_~#t1712~0.offset_1|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_1|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_1|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_1|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_1|, ULTIMATE.start_main_~#t1712~0.base=|v_ULTIMATE.start_main_~#t1712~0.base_1|, ULTIMATE.start_main_~#t1711~0.base=|v_ULTIMATE.start_main_~#t1711~0.base_1|, ULTIMATE.start_main_~#t1711~0.offset=|v_ULTIMATE.start_main_~#t1711~0.offset_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet40, ULTIMATE.start_main_#t~nondet41, ULTIMATE.start_main_~#t1712~0.base, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_~#t1712~0.offset, ULTIMATE.start_main_~#t1711~0.base, ULTIMATE.start_main_~#t1711~0.offset, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [503] L773-->L773-1: Formula: (and (= (store |v_#length_2| |v_ULTIMATE.start_main_~#t1711~0.base_2| 4) |v_#length_1|) (= (select |v_#valid_2| |v_ULTIMATE.start_main_~#t1711~0.base_2|) 0) (= |v_ULTIMATE.start_main_~#t1711~0.offset_2| 0) (not (= 0 |v_ULTIMATE.start_main_~#t1711~0.base_2|)) (= |v_#valid_1| (store |v_#valid_2| |v_ULTIMATE.start_main_~#t1711~0.base_2| 1))) InVars {#length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#length=|v_#length_1|, ULTIMATE.start_main_~#t1711~0.base=|v_ULTIMATE.start_main_~#t1711~0.base_2|, ULTIMATE.start_main_~#t1711~0.offset=|v_ULTIMATE.start_main_~#t1711~0.offset_2|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1711~0.base, ULTIMATE.start_main_~#t1711~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [485] L773-1-->L774: Formula: (= (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1711~0.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1711~0.base_3|) |v_ULTIMATE.start_main_~#t1711~0.offset_3| 0)) |v_#memory_int_1|) InVars {#memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t1711~0.base=|v_ULTIMATE.start_main_~#t1711~0.base_3|, ULTIMATE.start_main_~#t1711~0.offset=|v_ULTIMATE.start_main_~#t1711~0.offset_3|} OutVars{#memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t1711~0.base=|v_ULTIMATE.start_main_~#t1711~0.base_3|, ULTIMATE.start_main_~#t1711~0.offset=|v_ULTIMATE.start_main_~#t1711~0.offset_3|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 [642] L774-->P0ENTRY: Formula: (and (= 0 |v_Thread0_P0_#in~arg.offset_3|) (= 0 v_Thread0_P0_thidvar0_2) (= 0 |v_Thread0_P0_#in~arg.base_3|)) InVars {} OutVars{Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_3|, Thread0_P0_thidvar0=v_Thread0_P0_thidvar0_2, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P0_#in~arg.base, Thread0_P0_thidvar0, Thread0_P0_#in~arg.offset] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [530] P0ENTRY-->L4: Formula: (and (= v_Thread0_P0_~arg.base_1 |v_Thread0_P0_#in~arg.base_1|) (= v_Thread0_P0_~arg.offset_1 |v_Thread0_P0_#in~arg.offset_1|) (= v_~x$w_buff0~0_1 1) (= v_Thread0_P0___VERIFIER_assert_~expression_1 |v_Thread0_P0___VERIFIER_assert_#in~expression_1|) (= v_~x$w_buff1~0_1 v_~x$w_buff0~0_2) (= v_~x$w_buff1_used~0_1 v_~x$w_buff0_used~0_2) (= v_~x$w_buff0_used~0_1 1) (= |v_Thread0_P0___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= 0 (mod v_~x$w_buff1_used~0_1 256))) (not (= (mod v_~x$w_buff0_used~0_1 256) 0)))) 1 0))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_2, Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_2} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_1, Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_1, Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_~arg.offset=v_Thread0_P0_~arg.offset_1, ~x$w_buff1~0=v_~x$w_buff1~0_1, Thread0_P0_~arg.base=v_Thread0_P0_~arg.base_1, Thread0_P0___VERIFIER_assert_#in~expression=|v_Thread0_P0___VERIFIER_assert_#in~expression_1|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_1, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_1} AuxVars[] AssignedVars[~x$w_buff0~0, Thread0_P0___VERIFIER_assert_~expression, Thread0_P0_~arg.offset, ~x$w_buff1~0, Thread0_P0_~arg.base, Thread0_P0___VERIFIER_assert_#in~expression, ~x$w_buff1_used~0, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [532] L4-->L4-3: Formula: (not (= 0 v_Thread0_P0___VERIFIER_assert_~expression_3)) InVars {Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_3} OutVars{Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [439] L774-1-->L775: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet40] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [535] L4-3-->L715: Formula: (and (= v_~x$r_buff0_thd1~0_1 1) (= v_~x$r_buff1_thd0~0_1 v_~x$r_buff0_thd0~0_1) (= v_~x$r_buff1_thd2~0_1 v_~x$r_buff0_thd2~0_1) (= v_~x$r_buff1_thd1~0_1 v_~x$r_buff0_thd1~0_2) (= v_~y~0_1 1)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_2, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_1, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_1, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_1, ~y~0=v_~y~0_1, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_1} AuxVars[] AssignedVars[~x$r_buff0_thd1~0, ~x$r_buff1_thd2~0, ~x$r_buff1_thd1~0, ~y~0, ~x$r_buff1_thd0~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 0 [536] L715-->L715-5: Formula: (and (not (= 0 (mod v_~x$w_buff0_used~0_3 256))) (= |v_Thread0_P0_#t~ite4_1| v_~x$w_buff0~0_3) (not (= 0 (mod v_~x$r_buff0_thd1~0_3 256)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_3, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_3, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_3, Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_3, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} AuxVars[] AssignedVars[Thread0_P0_#t~ite4] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] -1 [363] L775-->L775-1: Formula: (and (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t1712~0.base_2| 4)) (= |v_#valid_3| (store |v_#valid_4| |v_ULTIMATE.start_main_~#t1712~0.base_2| 1)) (= |v_ULTIMATE.start_main_~#t1712~0.offset_2| 0) (not (= 0 |v_ULTIMATE.start_main_~#t1712~0.base_2|)) (= 0 (select |v_#valid_4| |v_ULTIMATE.start_main_~#t1712~0.base_2|))) InVars {#length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{#length=|v_#length_3|, ULTIMATE.start_main_~#t1712~0.base=|v_ULTIMATE.start_main_~#t1712~0.base_2|, ULTIMATE.start_main_~#t1712~0.offset=|v_ULTIMATE.start_main_~#t1712~0.offset_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1712~0.base, #valid, #length, ULTIMATE.start_main_~#t1712~0.offset] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] -1 [366] L775-1-->L776: Formula: (= |v_#memory_int_3| (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1712~0.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1712~0.base_3|) |v_ULTIMATE.start_main_~#t1712~0.offset_3| 1))) InVars {#memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t1712~0.base=|v_ULTIMATE.start_main_~#t1712~0.base_3|, ULTIMATE.start_main_~#t1712~0.offset=|v_ULTIMATE.start_main_~#t1712~0.offset_3|} OutVars{#memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t1712~0.base=|v_ULTIMATE.start_main_~#t1712~0.base_3|, ULTIMATE.start_main_~#t1712~0.offset=|v_ULTIMATE.start_main_~#t1712~0.offset_3|} AuxVars[] AssignedVars[#memory_int] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] FORK -1 [643] L776-->P1ENTRY: Formula: (and (= 0 |v_Thread1_P1_#in~arg.base_3|) (= 0 |v_Thread1_P1_#in~arg.offset_3|) (= 1 v_Thread1_P1_thidvar0_2)) InVars {} OutVars{Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_3|, Thread1_P1_thidvar0=v_Thread1_P1_thidvar0_2, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread1_P1_#in~arg.base, Thread1_P1_thidvar0, Thread1_P1_#in~arg.offset] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 1 [557] P1ENTRY-->L739: Formula: (and (= v_Thread1_P1_~arg.offset_1 |v_Thread1_P1_#in~arg.offset_1|) (= v_Thread1_P1_~arg.base_1 |v_Thread1_P1_#in~arg.base_1|) (= v_~y~0_2 2) (= v_~__unbuffered_p1_EAX~0_1 v_~y~0_2) (= v_~x$flush_delayed~0_1 v_~weak$$choice2~0_7) (= v_~weak$$choice0~0_1 (ite (= 0 (+ |v_Thread1_P1_#t~nondet10.base_1| |v_Thread1_P1_#t~nondet10.offset_1|)) 0 1)) (= v_~x$mem_tmp~0_1 v_~x~0_3) (= v_~weak$$choice2~0_7 (ite (= (+ |v_Thread1_P1_#t~nondet11.offset_1| |v_Thread1_P1_#t~nondet11.base_1|) 0) 0 1))) InVars {Thread1_P1_#t~nondet10.offset=|v_Thread1_P1_#t~nondet10.offset_1|, Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_#t~nondet10.base=|v_Thread1_P1_#t~nondet10.base_1|, Thread1_P1_#t~nondet11.base=|v_Thread1_P1_#t~nondet11.base_1|, Thread1_P1_#t~nondet11.offset=|v_Thread1_P1_#t~nondet11.offset_1|, ~x~0=v_~x~0_3, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|} OutVars{Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_~arg.offset=v_Thread1_P1_~arg.offset_1, Thread1_P1_#t~nondet10.base=|v_Thread1_P1_#t~nondet10.base_2|, ~x$flush_delayed~0=v_~x$flush_delayed~0_1, ~x$mem_tmp~0=v_~x$mem_tmp~0_1, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|, Thread1_P1_#t~nondet10.offset=|v_Thread1_P1_#t~nondet10.offset_2|, ~weak$$choice0~0=v_~weak$$choice0~0_1, Thread1_P1_~arg.base=v_Thread1_P1_~arg.base_1, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, Thread1_P1_#t~nondet11.base=|v_Thread1_P1_#t~nondet11.base_2|, ~weak$$choice2~0=v_~weak$$choice2~0_7, ~y~0=v_~y~0_2, Thread1_P1_#t~nondet11.offset=|v_Thread1_P1_#t~nondet11.offset_2|, ~x~0=v_~x~0_3} AuxVars[] AssignedVars[Thread1_P1_#t~nondet10.offset, ~weak$$choice0~0, Thread1_P1_~arg.offset, Thread1_P1_#t~nondet10.base, Thread1_P1_~arg.base, ~__unbuffered_p1_EAX~0, ~x$flush_delayed~0, Thread1_P1_#t~nondet11.base, ~x$mem_tmp~0, ~weak$$choice2~0, ~y~0, Thread1_P1_#t~nondet11.offset] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [558] L739-->L739-5: Formula: (and (= |v_Thread1_P1_#t~ite13_1| v_~x~0_4) (let ((.cse0 (= (mod v_~x$r_buff0_thd2~0_15 256) 0))) (or (and .cse0 (= (mod v_~x$w_buff1_used~0_17 256) 0)) (= (mod v_~x$w_buff0_used~0_26 256) 0) (and (= 0 (mod v_~x$r_buff1_thd2~0_9 256)) .cse0)))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_17, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_9, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_15, ~x~0=v_~x~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_26} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_17, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_9, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_15, ~x~0=v_~x~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_26} AuxVars[] AssignedVars[Thread1_P1_#t~ite13] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite13|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [560] L739-5-->L740: Formula: (= v_~x~0_6 |v_Thread1_P1_#t~ite13_2|) InVars {Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_2|} OutVars{Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_1|, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_3|, ~x~0=v_~x~0_6} AuxVars[] AssignedVars[Thread1_P1_#t~ite12, Thread1_P1_#t~ite13, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [563] L740-->L740-8: Formula: (and (not (= (mod v_~weak$$choice2~0_8 256) 0)) (= |v_Thread1_P1_#t~ite16_1| v_~x$w_buff0~0_5)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_5, ~weak$$choice2~0=v_~weak$$choice2~0_8} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_5, ~weak$$choice2~0=v_~weak$$choice2~0_8, Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite16] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite16|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [566] L740-8-->L741: Formula: (= v_~x$w_buff0~0_10 |v_Thread1_P1_#t~ite16_2|) InVars {Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_2|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_10, Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_1|, Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_3|, Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_1|} AuxVars[] AssignedVars[~x$w_buff0~0, Thread1_P1_#t~ite14, Thread1_P1_#t~ite16, Thread1_P1_#t~ite15] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [569] L741-->L741-8: Formula: (and (not (= (mod v_~weak$$choice2~0_10 256) 0)) (= |v_Thread1_P1_#t~ite19_1| v_~x$w_buff1~0_5)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_10, ~x$w_buff1~0=v_~x$w_buff1~0_5} OutVars{Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_1|, ~weak$$choice2~0=v_~weak$$choice2~0_10, ~x$w_buff1~0=v_~x$w_buff1~0_5} AuxVars[] AssignedVars[Thread1_P1_#t~ite19] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite19|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [574] L741-8-->L742: Formula: (= v_~x$w_buff1~0_9 |v_Thread1_P1_#t~ite19_2|) InVars {Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_2|} OutVars{Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_3|, Thread1_P1_#t~ite18=|v_Thread1_P1_#t~ite18_1|, ~x$w_buff1~0=v_~x$w_buff1~0_9, Thread1_P1_#t~ite17=|v_Thread1_P1_#t~ite17_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite19, ~x$w_buff1~0, Thread1_P1_#t~ite18, Thread1_P1_#t~ite17] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [578] L742-->L742-8: Formula: (and (not (= (mod v_~weak$$choice2~0_12 256) 0)) (= |v_Thread1_P1_#t~ite22_1| v_~x$w_buff0_used~0_50)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_12, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_50} OutVars{Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_1|, ~weak$$choice2~0=v_~weak$$choice2~0_12, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_50} AuxVars[] AssignedVars[Thread1_P1_#t~ite22] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite22|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [583] L742-8-->L743: Formula: (= v_~x$w_buff0_used~0_15 |v_Thread1_P1_#t~ite22_2|) InVars {Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_2|} OutVars{Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_3|, Thread1_P1_#t~ite21=|v_Thread1_P1_#t~ite21_1|, Thread1_P1_#t~ite20=|v_Thread1_P1_#t~ite20_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_15} AuxVars[] AssignedVars[Thread1_P1_#t~ite21, Thread1_P1_#t~ite20, Thread1_P1_#t~ite22, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [587] L743-->L743-8: Formula: (and (= |v_Thread1_P1_#t~ite25_1| v_~x$w_buff1_used~0_9) (not (= (mod v_~weak$$choice2~0_1 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_1, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_9} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_9, Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_1|, ~weak$$choice2~0=v_~weak$$choice2~0_1} AuxVars[] AssignedVars[Thread1_P1_#t~ite25] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite25|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [592] L743-8-->L744: Formula: (= v_~x$w_buff1_used~0_12 |v_Thread1_P1_#t~ite25_2|) InVars {Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_2|} OutVars{Thread1_P1_#t~ite23=|v_Thread1_P1_#t~ite23_1|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_12, Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_3|, Thread1_P1_#t~ite24=|v_Thread1_P1_#t~ite24_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite23, ~x$w_buff1_used~0, Thread1_P1_#t~ite25, Thread1_P1_#t~ite24] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [596] L744-->L744-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_3 256))) (= |v_Thread1_P1_#t~ite28_1| v_~x$r_buff0_thd2~0_7)) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_7, ~weak$$choice2~0=v_~weak$$choice2~0_3} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_7, ~weak$$choice2~0=v_~weak$$choice2~0_3, Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite28] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite28|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [601] L744-8-->L745: Formula: (= v_~x$r_buff0_thd2~0_12 |v_Thread1_P1_#t~ite28_2|) InVars {Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_2|} OutVars{Thread1_P1_#t~ite27=|v_Thread1_P1_#t~ite27_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_12, Thread1_P1_#t~ite26=|v_Thread1_P1_#t~ite26_1|, Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_3|} AuxVars[] AssignedVars[Thread1_P1_#t~ite27, ~x$r_buff0_thd2~0, Thread1_P1_#t~ite26, Thread1_P1_#t~ite28] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [605] L745-->L745-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_5 256))) (= |v_Thread1_P1_#t~ite31_1| v_~x$r_buff1_thd2~0_6)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_5, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6, Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_1|, ~weak$$choice2~0=v_~weak$$choice2~0_5} AuxVars[] AssignedVars[Thread1_P1_#t~ite31] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite31|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [610] L745-8-->L747: Formula: (and (= v_~x$r_buff1_thd2~0_11 |v_Thread1_P1_#t~ite31_2|) (= v_~__unbuffered_p1_EBX~0_1 v_~x~0_5)) InVars {Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_2|, ~x~0=v_~x~0_5} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_1, Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_3|, Thread1_P1_#t~ite30=|v_Thread1_P1_#t~ite30_1|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_11, ~x~0=v_~x~0_5, Thread1_P1_#t~ite29=|v_Thread1_P1_#t~ite29_1|} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0, Thread1_P1_#t~ite31, Thread1_P1_#t~ite30, ~x$r_buff1_thd2~0, Thread1_P1_#t~ite29] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [614] L747-->L747-2: Formula: (and (= |v_Thread1_P1_#t~ite32_1| v_~x$mem_tmp~0_2) (not (= (mod v_~x$flush_delayed~0_2 256) 0))) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_2, ~x$mem_tmp~0=v_~x$mem_tmp~0_2} OutVars{~x$mem_tmp~0=v_~x$mem_tmp~0_2, ~x$flush_delayed~0=v_~x$flush_delayed~0_2, Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite32] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [538] L715-5-->L716: Formula: (= v_~x~0_2 |v_Thread0_P0_#t~ite4_2|) InVars {Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_2|} OutVars{Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_3|, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_1|, ~x~0=v_~x~0_2} AuxVars[] AssignedVars[Thread0_P0_#t~ite4, Thread0_P0_#t~ite3, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [619] L747-2-->L751: Formula: (and (= v_~x~0_8 |v_Thread1_P1_#t~ite32_3|) (= v_~x$flush_delayed~0_4 0)) InVars {Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_3|} OutVars{~x$flush_delayed~0=v_~x$flush_delayed~0_4, Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_4|, ~x~0=v_~x~0_8} AuxVars[] AssignedVars[~x$flush_delayed~0, Thread1_P1_#t~ite32, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [541] L716-->L716-2: Formula: (and (= |v_Thread0_P0_#t~ite5_1| 0) (not (= 0 (mod v_~x$r_buff0_thd1~0_5 256))) (not (= (mod v_~x$w_buff0_used~0_5 256) 0))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} AuxVars[] AssignedVars[Thread0_P0_#t~ite5] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite5|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [544] L716-2-->L717: Formula: (= v_~x$w_buff0_used~0_7 |v_Thread0_P0_#t~ite5_3|) InVars {Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_3|} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_7} AuxVars[] AssignedVars[Thread0_P0_#t~ite5, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [546] L717-->L717-2: Formula: (and (= |v_Thread0_P0_#t~ite6_2| v_~x$w_buff1_used~0_5) (or (= 0 (mod v_~x$r_buff1_thd1~0_5 256)) (= 0 (mod v_~x$w_buff1_used~0_5 256))) (or (= (mod v_~x$w_buff0_used~0_9 256) 0) (= (mod v_~x$r_buff0_thd1~0_8 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_5, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_9} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_5, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_5, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_9} AuxVars[] AssignedVars[Thread0_P0_#t~ite6] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite6|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [547] L717-2-->L718: Formula: (= v_~x$w_buff1_used~0_6 |v_Thread0_P0_#t~ite6_3|) InVars {Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_3|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_6, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, Thread0_P0_#t~ite6] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [549] L718-->L718-2: Formula: (and (= |v_Thread0_P0_#t~ite7_2| v_~x$r_buff0_thd1~0_10) (or (= (mod v_~x$w_buff0_used~0_11 256) 0) (= (mod v_~x$r_buff0_thd1~0_10 256) 0))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_11} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_2|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_11} AuxVars[] AssignedVars[Thread0_P0_#t~ite7] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite7|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [550] L718-2-->L719: Formula: (= v_~x$r_buff0_thd1~0_11 |v_Thread0_P0_#t~ite7_3|) InVars {Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_3|} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_4|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_11} AuxVars[] AssignedVars[~x$r_buff0_thd1~0, Thread0_P0_#t~ite7] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [552] L719-->L719-2: Formula: (and (or (= 0 (mod v_~x$w_buff0_used~0_13 256)) (= (mod v_~x$r_buff0_thd1~0_13 256) 0)) (= |v_Thread0_P0_#t~ite8_2| v_~x$r_buff1_thd1~0_7) (or (= (mod v_~x$r_buff1_thd1~0_7 256) 0) (= 0 (mod v_~x$w_buff1_used~0_8 256)))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_8, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_13, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_13} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_8, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_13, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_13} AuxVars[] AssignedVars[Thread0_P0_#t~ite8] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite8|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [553] L719-2-->L724: Formula: (and (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1)) (= v_~x$r_buff1_thd1~0_8 |v_Thread0_P0_#t~ite8_3|)) InVars {Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_8, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_4|} AuxVars[] AssignedVars[~__unbuffered_cnt~0, ~x$r_buff1_thd1~0, Thread0_P0_#t~ite8] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [622] L751-->L751-2: Formula: (or (= 0 (mod v_~x$w_buff0_used~0_35 256)) (= 0 (mod v_~x$r_buff0_thd2~0_24 256))) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_24, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_35} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_24, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_35} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [625] L751-2-->L751-4: Formula: (and (= |v_Thread1_P1_#t~ite33_3| v_~x~0_9) (or (= 0 (mod v_~x$w_buff1_used~0_22 256)) (= (mod v_~x$r_buff1_thd2~0_15 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_22, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_15, ~x~0=v_~x~0_9} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_22, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_15, Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_3|, ~x~0=v_~x~0_9} AuxVars[] AssignedVars[Thread1_P1_#t~ite33] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite33|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [628] L751-4-->L751-5: Formula: (= |v_Thread1_P1_#t~ite34_4| |v_Thread1_P1_#t~ite33_4|) InVars {Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_4|} OutVars{Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_4|, Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_4|} AuxVars[] AssignedVars[Thread1_P1_#t~ite34] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite33|=0, |Thread1_P1_#t~ite34|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [623] L751-5-->L752: Formula: (= v_~x~0_10 |v_Thread1_P1_#t~ite34_2|) InVars {Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_2|} OutVars{Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_1|, Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_3|, ~x~0=v_~x~0_10} AuxVars[] AssignedVars[Thread1_P1_#t~ite33, Thread1_P1_#t~ite34, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [627] L752-->L752-2: Formula: (and (or (= 0 (mod v_~x$r_buff0_thd2~0_28 256)) (= (mod v_~x$w_buff0_used~0_39 256) 0)) (= |v_Thread1_P1_#t~ite35_2| v_~x$w_buff0_used~0_39)) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_28, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_39} OutVars{Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_28, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_39} AuxVars[] AssignedVars[Thread1_P1_#t~ite35] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite35|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [629] L752-2-->L753: Formula: (= v_~x$w_buff0_used~0_40 |v_Thread1_P1_#t~ite35_3|) InVars {Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_3|} OutVars{Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_40} AuxVars[] AssignedVars[Thread1_P1_#t~ite35, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [631] L753-->L753-2: Formula: (and (= |v_Thread1_P1_#t~ite36_2| v_~x$w_buff1_used~0_26) (or (= 0 (mod v_~x$r_buff0_thd2~0_32 256)) (= (mod v_~x$w_buff0_used~0_44 256) 0)) (or (= 0 (mod v_~x$r_buff1_thd2~0_19 256)) (= (mod v_~x$w_buff1_used~0_26 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_26, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_19, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_32, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_44} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_26, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_19, Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_32, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_44} AuxVars[] AssignedVars[Thread1_P1_#t~ite36] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite36|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [632] L753-2-->L754: Formula: (= v_~x$w_buff1_used~0_27 |v_Thread1_P1_#t~ite36_3|) InVars {Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_3|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_27, Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, Thread1_P1_#t~ite36] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [634] L754-->L754-2: Formula: (and (= |v_Thread1_P1_#t~ite37_2| v_~x$r_buff0_thd2~0_36) (or (= (mod v_~x$w_buff0_used~0_48 256) 0) (= (mod v_~x$r_buff0_thd2~0_36 256) 0))) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_36, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_48} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_36, Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_48} AuxVars[] AssignedVars[Thread1_P1_#t~ite37] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite37|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [635] L754-2-->L755: Formula: (= v_~x$r_buff0_thd2~0_37 |v_Thread1_P1_#t~ite37_3|) InVars {Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_3|} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_37, Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_4|} AuxVars[] AssignedVars[~x$r_buff0_thd2~0, Thread1_P1_#t~ite37] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [637] L755-->L755-2: Formula: (and (= |v_Thread1_P1_#t~ite38_2| v_~x$r_buff1_thd2~0_21) (or (= (mod v_~x$r_buff0_thd2~0_39 256) 0) (= (mod v_~x$w_buff0_used~0_51 256) 0)) (or (= (mod v_~x$r_buff1_thd2~0_21 256) 0) (= (mod v_~x$w_buff1_used~0_29 256) 0))) InVars {~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_21, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_29, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_39, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_51} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_21, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_29, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_39, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_51} AuxVars[] AssignedVars[Thread1_P1_#t~ite38] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite38|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [638] L755-2-->L760: Formula: (and (= v_~x$r_buff1_thd2~0_22 |v_Thread1_P1_#t~ite38_3|) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_3|} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_22, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_4|} AuxVars[] AssignedVars[~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, Thread1_P1_#t~ite38] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [480] L776-1-->L780: Formula: (= v_~main$tmp_guard0~0_1 (ite (= (ite (= v_~__unbuffered_cnt~0_5 2) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_2|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet41, ~main$tmp_guard0~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [405] L780-->L782: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_2 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [445] L782-->L782-2: Formula: (or (= 0 (mod v_~x$w_buff0_used~0_57 256)) (= (mod v_~x$r_buff0_thd0~0_4 256) 0)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_57} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_57} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [450] L782-2-->L782-4: Formula: (and (= |v_ULTIMATE.start_main_#t~ite42_3| v_~x~0_12) (or (= 0 (mod v_~x$w_buff1_used~0_34 256)) (= 0 (mod v_~x$r_buff1_thd0~0_4 256)))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_34, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_4, ~x~0=v_~x~0_12} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_34, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_4, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_3|, ~x~0=v_~x~0_12} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite42] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [456] L782-4-->L782-5: Formula: (= |v_ULTIMATE.start_main_#t~ite43_3| |v_ULTIMATE.start_main_#t~ite42_4|) InVars {ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} OutVars{ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_3|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [429] L782-5-->L783: Formula: (= v_~x~0_13 |v_ULTIMATE.start_main_#t~ite43_5|) InVars {ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_5|} OutVars{ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_4|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_5|, ~x~0=v_~x~0_13} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [400] L783-->L783-2: Formula: (and (or (= (mod v_~x$r_buff0_thd0~0_6 256) 0) (= 0 (mod v_~x$w_buff0_used~0_59 256))) (= |v_ULTIMATE.start_main_#t~ite44_3| v_~x$w_buff0_used~0_59)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_59} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_59} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite44] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [378] L783-2-->L784: Formula: (= v_~x$w_buff0_used~0_60 |v_ULTIMATE.start_main_#t~ite44_5|) InVars {ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_5|} OutVars{ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_60} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite44, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [501] L784-->L784-2: Formula: (and (or (= (mod v_~x$r_buff0_thd0~0_8 256) 0) (= (mod v_~x$w_buff0_used~0_62 256) 0)) (= |v_ULTIMATE.start_main_#t~ite45_3| v_~x$w_buff1_used~0_36) (or (= (mod v_~x$r_buff1_thd0~0_6 256) 0) (= (mod v_~x$w_buff1_used~0_36 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_8, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_36, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_62} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_8, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_36, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_62} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite45] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [488] L784-2-->L785: Formula: (= v_~x$w_buff1_used~0_37 |v_ULTIMATE.start_main_#t~ite45_5|) InVars {ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_5|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_37, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite45] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [433] L785-->L785-2: Formula: (and (or (= 0 (mod v_~x$r_buff0_thd0~0_10 256)) (= 0 (mod v_~x$w_buff0_used~0_64 256))) (= |v_ULTIMATE.start_main_#t~ite46_3| v_~x$r_buff0_thd0~0_10)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_64} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_10, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_64} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [441] L785-2-->L786: Formula: (= v_~x$r_buff0_thd0~0_11 |v_ULTIMATE.start_main_#t~ite46_5|) InVars {ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_5|} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_11, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_4|} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite46] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [360] L786-->L786-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite47_3| v_~x$r_buff1_thd0~0_8) (or (= 0 (mod v_~x$r_buff0_thd0~0_13 256)) (= (mod v_~x$w_buff0_used~0_66 256) 0)) (or (= 0 (mod v_~x$r_buff1_thd0~0_8 256)) (= 0 (mod v_~x$w_buff1_used~0_39 256)))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_13, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_39, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_66} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_3|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_13, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_39, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_66} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [367] L786-2-->L791: Formula: (and (= v_~x$r_buff1_thd0~0_9 |v_ULTIMATE.start_main_#t~ite47_5|) (= v_~main$tmp_guard1~0_2 (ite (= (ite (not (and (= 2 v_~y~0_4) (= 2 v_~__unbuffered_p1_EAX~0_2) (= 0 v_~__unbuffered_p1_EBX~0_2))) 1 0) 0) 0 1))) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_5|, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~y~0=v_~y~0_4} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_4|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_2, ~y~0=v_~y~0_4, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_9} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ~main$tmp_guard1~0, ~x$r_buff1_thd0~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [404] L791-->L791-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_3 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [408] L791-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [401] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [395] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [392] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1711~0.base, main_~#t1711~0.offset, main_~#t1712~0.base, main_~#t1712~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t1711~0.base, main_~#t1711~0.offset := #Ultimate.alloc(4); srcloc: L773 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t1711~0.base, main_~#t1711~0.offset, 4); srcloc: L773-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 1;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet40; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd1~0 := 1;~y~0 := 1; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite4 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] -1 SUMMARY for call main_~#t1712~0.base, main_~#t1712~0.offset := #Ultimate.alloc(4); srcloc: L775 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] -1 SUMMARY for call write~int(1, main_~#t1712~0.base, main_~#t1712~0.offset, 4); srcloc: L775-1 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] FORK -1 fork 1 P1(0, 0); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 2;~__unbuffered_p1_EAX~0 := ~y~0;~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1);havoc #t~nondet10.base, #t~nondet10.offset;~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~x$flush_delayed~0 := ~weak$$choice2~0;~x$mem_tmp~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256);#t~ite13 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x~0 := #t~ite13;havoc #t~ite13;havoc #t~ite12; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff0~0 := #t~ite16;havoc #t~ite16;havoc #t~ite15;havoc #t~ite14; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~x$w_buff1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff1~0 := #t~ite19;havoc #t~ite19;havoc #t~ite17;havoc #t~ite18; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff0_used~0 := #t~ite22;havoc #t~ite20;havoc #t~ite22;havoc #t~ite21; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff1_used~0 := #t~ite25;havoc #t~ite25;havoc #t~ite24;havoc #t~ite23; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite28 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite28|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$r_buff0_thd2~0 := #t~ite28;havoc #t~ite26;havoc #t~ite27;havoc #t~ite28; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite31 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite31|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$r_buff1_thd2~0 := #t~ite31;havoc #t~ite30;havoc #t~ite29;havoc #t~ite31;~__unbuffered_p1_EBX~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~x$flush_delayed~0 % 256;#t~ite32 := ~x$mem_tmp~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x~0 := #t~ite4;havoc #t~ite4;havoc #t~ite3; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 ~x~0 := #t~ite32;havoc #t~ite32;~x$flush_delayed~0 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite5 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite6 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite7 := ~x$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite8 := ~x$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256);#t~ite33 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 #t~ite34 := #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |P1_#t~ite34|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x~0 := #t~ite34;havoc #t~ite34;havoc #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite35 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff0_used~0 := #t~ite35;havoc #t~ite35; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite36 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite36|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff1_used~0 := #t~ite36;havoc #t~ite36; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite37 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite37|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$r_buff0_thd2~0 := #t~ite37;havoc #t~ite37; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite38 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite38|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$r_buff1_thd2~0 := #t~ite38;havoc #t~ite38;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 havoc main_#t~nondet41;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);main_#t~ite42 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 main_#t~ite43 := main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x~0 := main_#t~ite43;havoc main_#t~ite43;havoc main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite44 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x$w_buff0_used~0 := main_#t~ite44;havoc main_#t~ite44; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite45 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x$w_buff1_used~0 := main_#t~ite45;havoc main_#t~ite45; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite46;havoc main_#t~ite46; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite47;havoc main_#t~ite47;~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 2 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1711~0.base, main_~#t1711~0.offset, main_~#t1712~0.base, main_~#t1712~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t1711~0.base, main_~#t1711~0.offset := #Ultimate.alloc(4); srcloc: L773 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t1711~0.base, main_~#t1711~0.offset, 4); srcloc: L773-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 1;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet40; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd1~0 := 1;~y~0 := 1; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite4 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] -1 SUMMARY for call main_~#t1712~0.base, main_~#t1712~0.offset := #Ultimate.alloc(4); srcloc: L775 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] -1 SUMMARY for call write~int(1, main_~#t1712~0.base, main_~#t1712~0.offset, 4); srcloc: L775-1 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] FORK -1 fork 1 P1(0, 0); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 2;~__unbuffered_p1_EAX~0 := ~y~0;~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1);havoc #t~nondet10.base, #t~nondet10.offset;~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~x$flush_delayed~0 := ~weak$$choice2~0;~x$mem_tmp~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256);#t~ite13 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x~0 := #t~ite13;havoc #t~ite13;havoc #t~ite12; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff0~0 := #t~ite16;havoc #t~ite16;havoc #t~ite15;havoc #t~ite14; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~x$w_buff1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff1~0 := #t~ite19;havoc #t~ite19;havoc #t~ite17;havoc #t~ite18; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff0_used~0 := #t~ite22;havoc #t~ite20;havoc #t~ite22;havoc #t~ite21; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff1_used~0 := #t~ite25;havoc #t~ite25;havoc #t~ite24;havoc #t~ite23; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite28 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite28|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$r_buff0_thd2~0 := #t~ite28;havoc #t~ite26;havoc #t~ite27;havoc #t~ite28; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite31 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite31|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$r_buff1_thd2~0 := #t~ite31;havoc #t~ite30;havoc #t~ite29;havoc #t~ite31;~__unbuffered_p1_EBX~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~x$flush_delayed~0 % 256;#t~ite32 := ~x$mem_tmp~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x~0 := #t~ite4;havoc #t~ite4;havoc #t~ite3; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 ~x~0 := #t~ite32;havoc #t~ite32;~x$flush_delayed~0 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite5 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite6 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite7 := ~x$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite8 := ~x$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256);#t~ite33 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 #t~ite34 := #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |P1_#t~ite34|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x~0 := #t~ite34;havoc #t~ite34;havoc #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite35 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff0_used~0 := #t~ite35;havoc #t~ite35; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite36 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite36|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff1_used~0 := #t~ite36;havoc #t~ite36; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite37 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite37|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$r_buff0_thd2~0 := #t~ite37;havoc #t~ite37; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite38 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite38|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$r_buff1_thd2~0 := #t~ite38;havoc #t~ite38;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 havoc main_#t~nondet41;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);main_#t~ite42 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 main_#t~ite43 := main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x~0 := main_#t~ite43;havoc main_#t~ite43;havoc main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite44 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x$w_buff0_used~0 := main_#t~ite44;havoc main_#t~ite44; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite45 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x$w_buff1_used~0 := main_#t~ite45;havoc main_#t~ite45; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite46;havoc main_#t~ite46; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite47;havoc main_#t~ite47;~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 2 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1711~0.base, main_~#t1711~0.offset, main_~#t1712~0.base, main_~#t1712~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L773] -1 call main_~#t1711~0.base, main_~#t1711~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] -1 call write~int(0, main_~#t1711~0.base, main_~#t1711~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L698-L725] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L701] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L702] 0 ~x$w_buff0~0 := 1; [L703] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L704] 0 ~x$w_buff0_used~0 := 1; [L705] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L705] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] -1 havoc main_#t~nondet40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L706] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L707] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L708] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L709] 0 ~x$r_buff0_thd1~0 := 1; [L712] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L715] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L715] 0 #t~ite4 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L775] -1 call main_~#t1712~0.base, main_~#t1712~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] -1 call write~int(1, main_~#t1712~0.base, main_~#t1712~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L726-L761] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L729] 1 ~y~0 := 2; [L732] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L735] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1); [L735] 1 havoc #t~nondet10.base, #t~nondet10.offset; [L736] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L736] 1 havoc #t~nondet11.base, #t~nondet11.offset; [L737] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L738] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] 1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256); [L739] 1 #t~ite13 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] 1 ~x~0 := #t~ite13; [L739] 1 havoc #t~ite13; [L739] 1 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] 1 assume 0 != ~weak$$choice2~0 % 256; [L740] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] 1 ~x$w_buff0~0 := #t~ite16; [L740] 1 havoc #t~ite16; [L740] 1 havoc #t~ite15; [L740] 1 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] 1 assume 0 != ~weak$$choice2~0 % 256; [L741] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] 1 ~x$w_buff1~0 := #t~ite19; [L741] 1 havoc #t~ite19; [L741] 1 havoc #t~ite17; [L741] 1 havoc #t~ite18; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] 1 assume 0 != ~weak$$choice2~0 % 256; [L742] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] 1 ~x$w_buff0_used~0 := #t~ite22; [L742] 1 havoc #t~ite20; [L742] 1 havoc #t~ite22; [L742] 1 havoc #t~ite21; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] 1 assume 0 != ~weak$$choice2~0 % 256; [L743] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] 1 ~x$w_buff1_used~0 := #t~ite25; [L743] 1 havoc #t~ite25; [L743] 1 havoc #t~ite24; [L743] 1 havoc #t~ite23; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] 1 assume 0 != ~weak$$choice2~0 % 256; [L744] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L744] 1 havoc #t~ite26; [L744] 1 havoc #t~ite27; [L744] 1 havoc #t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] 1 assume 0 != ~weak$$choice2~0 % 256; [L745] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L745] 1 havoc #t~ite30; [L745] 1 havoc #t~ite29; [L745] 1 havoc #t~ite31; [L746] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L747] 1 assume 0 != ~x$flush_delayed~0 % 256; [L747] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L715] 0 ~x~0 := #t~ite4; [L715] 0 havoc #t~ite4; [L715] 0 havoc #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L747] 1 ~x~0 := #t~ite32; [L747] 1 havoc #t~ite32; [L748] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L716] 0 #t~ite5 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] 0 ~x$w_buff0_used~0 := #t~ite5; [L716] 0 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L717] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] 0 ~x$w_buff1_used~0 := #t~ite6; [L717] 0 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L718] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L718] 0 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L719] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L719] 0 havoc #t~ite8; [L722] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256); [L751] 1 #t~ite33 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 #t~ite34 := #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 ~x~0 := #t~ite34; [L751] 1 havoc #t~ite34; [L751] 1 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L752] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] 1 ~x$w_buff0_used~0 := #t~ite35; [L752] 1 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L753] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] 1 ~x$w_buff1_used~0 := #t~ite36; [L753] 1 havoc #t~ite36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L754] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L754] 1 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L755] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L755] 1 havoc #t~ite38; [L758] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L776] -1 havoc main_#t~nondet41; [L778] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L780] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L782] -1 main_#t~ite42 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 ~x~0 := main_#t~ite43; [L782] -1 havoc main_#t~ite43; [L782] -1 havoc main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L783] -1 main_#t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] -1 ~x$w_buff0_used~0 := main_#t~ite44; [L783] -1 havoc main_#t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L784] -1 main_#t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] -1 ~x$w_buff1_used~0 := main_#t~ite45; [L784] -1 havoc main_#t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L785] -1 main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] -1 ~x$r_buff0_thd0~0 := main_#t~ite46; [L785] -1 havoc main_#t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L786] -1 main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] -1 ~x$r_buff1_thd0~0 := main_#t~ite47; [L786] -1 havoc main_#t~ite47; [L789] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 2 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L791] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L791] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1711~0.base, main_~#t1711~0.offset, main_~#t1712~0.base, main_~#t1712~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L773] -1 call main_~#t1711~0.base, main_~#t1711~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] -1 call write~int(0, main_~#t1711~0.base, main_~#t1711~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L698-L725] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L701] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L702] 0 ~x$w_buff0~0 := 1; [L703] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L704] 0 ~x$w_buff0_used~0 := 1; [L705] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L705] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] -1 havoc main_#t~nondet40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L706] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L707] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L708] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L709] 0 ~x$r_buff0_thd1~0 := 1; [L712] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L715] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L715] 0 #t~ite4 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L775] -1 call main_~#t1712~0.base, main_~#t1712~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] -1 call write~int(1, main_~#t1712~0.base, main_~#t1712~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L726-L761] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L729] 1 ~y~0 := 2; [L732] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L735] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1); [L735] 1 havoc #t~nondet10.base, #t~nondet10.offset; [L736] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L736] 1 havoc #t~nondet11.base, #t~nondet11.offset; [L737] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L738] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] 1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256); [L739] 1 #t~ite13 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] 1 ~x~0 := #t~ite13; [L739] 1 havoc #t~ite13; [L739] 1 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] 1 assume 0 != ~weak$$choice2~0 % 256; [L740] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] 1 ~x$w_buff0~0 := #t~ite16; [L740] 1 havoc #t~ite16; [L740] 1 havoc #t~ite15; [L740] 1 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] 1 assume 0 != ~weak$$choice2~0 % 256; [L741] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] 1 ~x$w_buff1~0 := #t~ite19; [L741] 1 havoc #t~ite19; [L741] 1 havoc #t~ite17; [L741] 1 havoc #t~ite18; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] 1 assume 0 != ~weak$$choice2~0 % 256; [L742] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] 1 ~x$w_buff0_used~0 := #t~ite22; [L742] 1 havoc #t~ite20; [L742] 1 havoc #t~ite22; [L742] 1 havoc #t~ite21; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] 1 assume 0 != ~weak$$choice2~0 % 256; [L743] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] 1 ~x$w_buff1_used~0 := #t~ite25; [L743] 1 havoc #t~ite25; [L743] 1 havoc #t~ite24; [L743] 1 havoc #t~ite23; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] 1 assume 0 != ~weak$$choice2~0 % 256; [L744] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L744] 1 havoc #t~ite26; [L744] 1 havoc #t~ite27; [L744] 1 havoc #t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] 1 assume 0 != ~weak$$choice2~0 % 256; [L745] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L745] 1 havoc #t~ite30; [L745] 1 havoc #t~ite29; [L745] 1 havoc #t~ite31; [L746] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L747] 1 assume 0 != ~x$flush_delayed~0 % 256; [L747] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L715] 0 ~x~0 := #t~ite4; [L715] 0 havoc #t~ite4; [L715] 0 havoc #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L747] 1 ~x~0 := #t~ite32; [L747] 1 havoc #t~ite32; [L748] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L716] 0 #t~ite5 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] 0 ~x$w_buff0_used~0 := #t~ite5; [L716] 0 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L717] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] 0 ~x$w_buff1_used~0 := #t~ite6; [L717] 0 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L718] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L718] 0 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L719] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L719] 0 havoc #t~ite8; [L722] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256); [L751] 1 #t~ite33 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 #t~ite34 := #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 ~x~0 := #t~ite34; [L751] 1 havoc #t~ite34; [L751] 1 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L752] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] 1 ~x$w_buff0_used~0 := #t~ite35; [L752] 1 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L753] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] 1 ~x$w_buff1_used~0 := #t~ite36; [L753] 1 havoc #t~ite36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L754] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L754] 1 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L755] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L755] 1 havoc #t~ite38; [L758] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L776] -1 havoc main_#t~nondet41; [L778] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L780] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L782] -1 main_#t~ite42 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 ~x~0 := main_#t~ite43; [L782] -1 havoc main_#t~ite43; [L782] -1 havoc main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L783] -1 main_#t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] -1 ~x$w_buff0_used~0 := main_#t~ite44; [L783] -1 havoc main_#t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L784] -1 main_#t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] -1 ~x$w_buff1_used~0 := main_#t~ite45; [L784] -1 havoc main_#t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L785] -1 main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] -1 ~x$r_buff0_thd0~0 := main_#t~ite46; [L785] -1 havoc main_#t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L786] -1 main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] -1 ~x$r_buff1_thd0~0 := main_#t~ite47; [L786] -1 havoc main_#t~ite47; [L789] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 2 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L791] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L791] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1711~0, main_~#t1712~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L773] FCALL -1 call main_~#t1711~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FCALL -1 call write~int(0, main_~#t1711~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L698-L725] 0 ~arg := #in~arg; [L701] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L702] 0 ~x$w_buff0~0 := 1; [L703] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L704] 0 ~x$w_buff0_used~0 := 1; [L705] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L705] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] -1 havoc main_#t~nondet40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L706] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L707] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L708] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L709] 0 ~x$r_buff0_thd1~0 := 1; [L712] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L715] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L715] 0 #t~ite4 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L775] FCALL -1 call main_~#t1712~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FCALL -1 call write~int(1, main_~#t1712~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L726-L761] 1 ~arg := #in~arg; [L729] 1 ~y~0 := 2; [L732] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L735] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L735] 1 havoc #t~nondet10; [L736] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L736] 1 havoc #t~nondet11; [L737] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L738] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] COND TRUE 1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256) [L739] 1 #t~ite13 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] 1 ~x~0 := #t~ite13; [L739] 1 havoc #t~ite13; [L739] 1 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L740] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] 1 ~x$w_buff0~0 := #t~ite16; [L740] 1 havoc #t~ite16; [L740] 1 havoc #t~ite15; [L740] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L741] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] 1 ~x$w_buff1~0 := #t~ite19; [L741] 1 havoc #t~ite19; [L741] 1 havoc #t~ite17; [L741] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L742] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] 1 ~x$w_buff0_used~0 := #t~ite22; [L742] 1 havoc #t~ite20; [L742] 1 havoc #t~ite22; [L742] 1 havoc #t~ite21; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L743] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] 1 ~x$w_buff1_used~0 := #t~ite25; [L743] 1 havoc #t~ite25; [L743] 1 havoc #t~ite24; [L743] 1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L744] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L744] 1 havoc #t~ite26; [L744] 1 havoc #t~ite27; [L744] 1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L745] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L745] 1 havoc #t~ite30; [L745] 1 havoc #t~ite29; [L745] 1 havoc #t~ite31; [L746] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L747] COND TRUE 1 0 != ~x$flush_delayed~0 % 256 [L747] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L715] 0 ~x~0 := #t~ite4; [L715] 0 havoc #t~ite4; [L715] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L747] 1 ~x~0 := #t~ite32; [L747] 1 havoc #t~ite32; [L748] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L716] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] 0 ~x$w_buff0_used~0 := #t~ite5; [L716] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L717] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] 0 ~x$w_buff1_used~0 := #t~ite6; [L717] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L718] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L718] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L719] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L719] 0 havoc #t~ite8; [L722] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L751] 1 #t~ite33 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 ~x~0 := #t~ite34; [L751] 1 havoc #t~ite34; [L751] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L752] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] 1 ~x$w_buff0_used~0 := #t~ite35; [L752] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L753] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] 1 ~x$w_buff1_used~0 := #t~ite36; [L753] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L754] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L754] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L755] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L755] 1 havoc #t~ite38; [L758] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L776] -1 havoc main_#t~nondet41; [L778] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L780] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L782] -1 main_#t~ite42 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 ~x~0 := main_#t~ite43; [L782] -1 havoc main_#t~ite43; [L782] -1 havoc main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L783] -1 main_#t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] -1 ~x$w_buff0_used~0 := main_#t~ite44; [L783] -1 havoc main_#t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L784] -1 main_#t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] -1 ~x$w_buff1_used~0 := main_#t~ite45; [L784] -1 havoc main_#t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L785] -1 main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] -1 ~x$r_buff0_thd0~0 := main_#t~ite46; [L785] -1 havoc main_#t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L786] -1 main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] -1 ~x$r_buff1_thd0~0 := main_#t~ite47; [L786] -1 havoc main_#t~ite47; [L789] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 2 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L791] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L791] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1711~0, main_~#t1712~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L773] FCALL -1 call main_~#t1711~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FCALL -1 call write~int(0, main_~#t1711~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L698-L725] 0 ~arg := #in~arg; [L701] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L702] 0 ~x$w_buff0~0 := 1; [L703] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L704] 0 ~x$w_buff0_used~0 := 1; [L705] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L705] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] -1 havoc main_#t~nondet40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L706] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L707] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L708] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L709] 0 ~x$r_buff0_thd1~0 := 1; [L712] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L715] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L715] 0 #t~ite4 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L775] FCALL -1 call main_~#t1712~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FCALL -1 call write~int(1, main_~#t1712~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L726-L761] 1 ~arg := #in~arg; [L729] 1 ~y~0 := 2; [L732] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L735] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L735] 1 havoc #t~nondet10; [L736] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L736] 1 havoc #t~nondet11; [L737] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L738] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] COND TRUE 1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256) [L739] 1 #t~ite13 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] 1 ~x~0 := #t~ite13; [L739] 1 havoc #t~ite13; [L739] 1 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L740] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] 1 ~x$w_buff0~0 := #t~ite16; [L740] 1 havoc #t~ite16; [L740] 1 havoc #t~ite15; [L740] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L741] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] 1 ~x$w_buff1~0 := #t~ite19; [L741] 1 havoc #t~ite19; [L741] 1 havoc #t~ite17; [L741] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L742] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] 1 ~x$w_buff0_used~0 := #t~ite22; [L742] 1 havoc #t~ite20; [L742] 1 havoc #t~ite22; [L742] 1 havoc #t~ite21; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L743] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] 1 ~x$w_buff1_used~0 := #t~ite25; [L743] 1 havoc #t~ite25; [L743] 1 havoc #t~ite24; [L743] 1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L744] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L744] 1 havoc #t~ite26; [L744] 1 havoc #t~ite27; [L744] 1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L745] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L745] 1 havoc #t~ite30; [L745] 1 havoc #t~ite29; [L745] 1 havoc #t~ite31; [L746] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L747] COND TRUE 1 0 != ~x$flush_delayed~0 % 256 [L747] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L715] 0 ~x~0 := #t~ite4; [L715] 0 havoc #t~ite4; [L715] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L747] 1 ~x~0 := #t~ite32; [L747] 1 havoc #t~ite32; [L748] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L716] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] 0 ~x$w_buff0_used~0 := #t~ite5; [L716] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L717] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] 0 ~x$w_buff1_used~0 := #t~ite6; [L717] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L718] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L718] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L719] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L719] 0 havoc #t~ite8; [L722] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L751] 1 #t~ite33 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 ~x~0 := #t~ite34; [L751] 1 havoc #t~ite34; [L751] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L752] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] 1 ~x$w_buff0_used~0 := #t~ite35; [L752] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L753] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] 1 ~x$w_buff1_used~0 := #t~ite36; [L753] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L754] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L754] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L755] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L755] 1 havoc #t~ite38; [L758] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L776] -1 havoc main_#t~nondet41; [L778] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L780] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L782] -1 main_#t~ite42 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 ~x~0 := main_#t~ite43; [L782] -1 havoc main_#t~ite43; [L782] -1 havoc main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L783] -1 main_#t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] -1 ~x$w_buff0_used~0 := main_#t~ite44; [L783] -1 havoc main_#t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L784] -1 main_#t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] -1 ~x$w_buff1_used~0 := main_#t~ite45; [L784] -1 havoc main_#t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L785] -1 main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] -1 ~x$r_buff0_thd0~0 := main_#t~ite46; [L785] -1 havoc main_#t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L786] -1 main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] -1 ~x$r_buff1_thd0~0 := main_#t~ite47; [L786] -1 havoc main_#t~ite47; [L789] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 2 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L791] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L791] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L773] FCALL -1 call ~#t1711~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FCALL -1 call write~int(0, ~#t1711~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L698-L725] 0 ~arg := #in~arg; [L701] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L702] 0 ~x$w_buff0~0 := 1; [L703] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L704] 0 ~x$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] -1 havoc #t~nondet40; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L706] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L707] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L708] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L709] 0 ~x$r_buff0_thd1~0 := 1; [L712] 0 ~y~0 := 1; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L715] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L715] 0 #t~ite4 := ~x$w_buff0~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L775] FCALL -1 call ~#t1712~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FCALL -1 call write~int(1, ~#t1712~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L726-L761] 1 ~arg := #in~arg; [L729] 1 ~y~0 := 2; [L732] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L735] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L735] 1 havoc #t~nondet10; [L736] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L736] 1 havoc #t~nondet11; [L737] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L738] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] COND TRUE 1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256) [L739] 1 #t~ite13 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] 1 ~x~0 := #t~ite13; [L739] 1 havoc #t~ite13; [L739] 1 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L740] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] 1 ~x$w_buff0~0 := #t~ite16; [L740] 1 havoc #t~ite16; [L740] 1 havoc #t~ite15; [L740] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L741] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] 1 ~x$w_buff1~0 := #t~ite19; [L741] 1 havoc #t~ite19; [L741] 1 havoc #t~ite17; [L741] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L742] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] 1 ~x$w_buff0_used~0 := #t~ite22; [L742] 1 havoc #t~ite20; [L742] 1 havoc #t~ite22; [L742] 1 havoc #t~ite21; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L743] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] 1 ~x$w_buff1_used~0 := #t~ite25; [L743] 1 havoc #t~ite25; [L743] 1 havoc #t~ite24; [L743] 1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L744] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L744] 1 havoc #t~ite26; [L744] 1 havoc #t~ite27; [L744] 1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L745] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L745] 1 havoc #t~ite30; [L745] 1 havoc #t~ite29; [L745] 1 havoc #t~ite31; [L746] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L747] COND TRUE 1 0 != ~x$flush_delayed~0 % 256 [L747] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L715] 0 ~x~0 := #t~ite4; [L715] 0 havoc #t~ite4; [L715] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L747] 1 ~x~0 := #t~ite32; [L747] 1 havoc #t~ite32; [L748] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L716] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] 0 ~x$w_buff0_used~0 := #t~ite5; [L716] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L717] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] 0 ~x$w_buff1_used~0 := #t~ite6; [L717] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L718] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L718] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L719] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L719] 0 havoc #t~ite8; [L722] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L751] 1 #t~ite33 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 ~x~0 := #t~ite34; [L751] 1 havoc #t~ite34; [L751] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L752] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] 1 ~x$w_buff0_used~0 := #t~ite35; [L752] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L753] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] 1 ~x$w_buff1_used~0 := #t~ite36; [L753] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L754] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L754] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L755] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L755] 1 havoc #t~ite38; [L758] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L776] -1 havoc #t~nondet41; [L778] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L780] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L782] -1 #t~ite42 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 #t~ite43 := #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 ~x~0 := #t~ite43; [L782] -1 havoc #t~ite43; [L782] -1 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L783] -1 #t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] -1 ~x$w_buff0_used~0 := #t~ite44; [L783] -1 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L784] -1 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] -1 ~x$w_buff1_used~0 := #t~ite45; [L784] -1 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L785] -1 #t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] -1 ~x$r_buff0_thd0~0 := #t~ite46; [L785] -1 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L786] -1 #t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] -1 ~x$r_buff1_thd0~0 := #t~ite47; [L786] -1 havoc #t~ite47; [L789] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 2 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L773] FCALL -1 call ~#t1711~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FCALL -1 call write~int(0, ~#t1711~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L698-L725] 0 ~arg := #in~arg; [L701] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L702] 0 ~x$w_buff0~0 := 1; [L703] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L704] 0 ~x$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] -1 havoc #t~nondet40; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L706] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L707] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L708] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L709] 0 ~x$r_buff0_thd1~0 := 1; [L712] 0 ~y~0 := 1; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L715] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L715] 0 #t~ite4 := ~x$w_buff0~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L775] FCALL -1 call ~#t1712~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FCALL -1 call write~int(1, ~#t1712~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L726-L761] 1 ~arg := #in~arg; [L729] 1 ~y~0 := 2; [L732] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L735] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L735] 1 havoc #t~nondet10; [L736] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L736] 1 havoc #t~nondet11; [L737] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L738] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] COND TRUE 1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256) [L739] 1 #t~ite13 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] 1 ~x~0 := #t~ite13; [L739] 1 havoc #t~ite13; [L739] 1 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L740] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] 1 ~x$w_buff0~0 := #t~ite16; [L740] 1 havoc #t~ite16; [L740] 1 havoc #t~ite15; [L740] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L741] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] 1 ~x$w_buff1~0 := #t~ite19; [L741] 1 havoc #t~ite19; [L741] 1 havoc #t~ite17; [L741] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L742] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] 1 ~x$w_buff0_used~0 := #t~ite22; [L742] 1 havoc #t~ite20; [L742] 1 havoc #t~ite22; [L742] 1 havoc #t~ite21; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L743] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] 1 ~x$w_buff1_used~0 := #t~ite25; [L743] 1 havoc #t~ite25; [L743] 1 havoc #t~ite24; [L743] 1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L744] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L744] 1 havoc #t~ite26; [L744] 1 havoc #t~ite27; [L744] 1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L745] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L745] 1 havoc #t~ite30; [L745] 1 havoc #t~ite29; [L745] 1 havoc #t~ite31; [L746] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L747] COND TRUE 1 0 != ~x$flush_delayed~0 % 256 [L747] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L715] 0 ~x~0 := #t~ite4; [L715] 0 havoc #t~ite4; [L715] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L747] 1 ~x~0 := #t~ite32; [L747] 1 havoc #t~ite32; [L748] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L716] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] 0 ~x$w_buff0_used~0 := #t~ite5; [L716] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L717] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] 0 ~x$w_buff1_used~0 := #t~ite6; [L717] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L718] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L718] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L719] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L719] 0 havoc #t~ite8; [L722] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L751] 1 #t~ite33 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 ~x~0 := #t~ite34; [L751] 1 havoc #t~ite34; [L751] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L752] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] 1 ~x$w_buff0_used~0 := #t~ite35; [L752] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L753] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] 1 ~x$w_buff1_used~0 := #t~ite36; [L753] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L754] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L754] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L755] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L755] 1 havoc #t~ite38; [L758] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L776] -1 havoc #t~nondet41; [L778] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L780] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L782] -1 #t~ite42 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 #t~ite43 := #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 ~x~0 := #t~ite43; [L782] -1 havoc #t~ite43; [L782] -1 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L783] -1 #t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] -1 ~x$w_buff0_used~0 := #t~ite44; [L783] -1 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L784] -1 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] -1 ~x$w_buff1_used~0 := #t~ite45; [L784] -1 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L785] -1 #t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] -1 ~x$r_buff0_thd0~0 := #t~ite46; [L785] -1 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L786] -1 #t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] -1 ~x$r_buff1_thd0~0 := #t~ite47; [L786] -1 havoc #t~ite47; [L789] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 2 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0] [L675] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L676] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0] [L677] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0] [L679] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L680] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0] [L681] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0] [L682] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L683] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L684] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L685] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L686] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L687] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L688] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L689] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L690] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L691] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L692] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L693] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L695] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L696] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L697] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L773] -1 pthread_t t1711; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L774] FCALL, FORK -1 pthread_create(&t1711, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L701] 0 x$w_buff1 = x$w_buff0 [L702] 0 x$w_buff0 = 1 [L703] 0 x$w_buff1_used = x$w_buff0_used [L704] 0 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0] [L706] 0 x$r_buff1_thd0 = x$r_buff0_thd0 [L707] 0 x$r_buff1_thd1 = x$r_buff0_thd1 [L708] 0 x$r_buff1_thd2 = x$r_buff0_thd2 [L709] 0 x$r_buff0_thd1 = (_Bool)1 [L712] 0 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L715] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L775] -1 pthread_t t1712; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L776] FCALL, FORK -1 pthread_create(&t1712, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L729] 1 y = 2 [L732] 1 __unbuffered_p1_EAX = y [L735] 1 weak$$choice0 = __VERIFIER_nondet_pointer() [L736] 1 weak$$choice2 = __VERIFIER_nondet_pointer() [L737] 1 x$flush_delayed = weak$$choice2 [L738] 1 x$mem_tmp = x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L739] EXPR 1 !x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1) VAL [!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L739] 1 x = !x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1) [L740] EXPR 1 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0))=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L740] 1 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)) [L741] EXPR 1 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L741] 1 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)) [L742] EXPR 1 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used))=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L742] 1 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used)) [L743] EXPR 1 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L743] 1 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L744] EXPR 1 weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L744] 1 x$r_buff0_thd2 = weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2)) [L745] EXPR 1 weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L745] 1 x$r_buff1_thd2 = weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L746] 1 __unbuffered_p1_EBX = x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L747] EXPR 1 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=1, x$flush_delayed ? x$mem_tmp : x=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L715] 0 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L747] 1 x = x$flush_delayed ? x$mem_tmp : x [L748] 1 x$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L716] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L716] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L717] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L717] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L718] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L718] 0 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L719] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L719] 0 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L722] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L751] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L751] EXPR 1 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=2] [L751] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x)=0, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=2] [L751] 1 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L752] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L752] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L753] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L753] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L754] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L754] 1 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L755] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L755] 1 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L758] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L778] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L782] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L782] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L782] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L782] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L783] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L783] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L784] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L784] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L785] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L785] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L786] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L786] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L789] -1 main$tmp_guard1 = !(y == 2 && __unbuffered_p1_EAX == 2 && __unbuffered_p1_EBX == 0) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] ----- [2018-11-23 14:29:00,796 INFO L305 ceAbstractionStarter]: Did not count any witness invariants because Icfg is not BoogieIcfg [2018-11-23 14:29:00,797 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 02:29:00 BasicIcfg [2018-11-23 14:29:00,797 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 14:29:00,798 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 14:29:00,798 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 14:29:00,798 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 14:29:00,798 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:28:38" (3/4) ... [2018-11-23 14:29:00,801 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [478] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [358] L-1-->L671: Formula: (= |v_#valid_9| (store |v_#valid_10| 0 0)) InVars {#valid=|v_#valid_10|} OutVars{#valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [517] L671-->L673: Formula: (= v_~__unbuffered_cnt~0_6 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [381] L673-->L675: Formula: (= v_~__unbuffered_p1_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [422] L675-->L676: Formula: (= v_~__unbuffered_p1_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 [350] L676-->L677: Formula: (= v_~main$tmp_guard0~0_3 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 [482] L677-->L679: Formula: (= v_~main$tmp_guard1~0_1 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_1} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [524] L679-->L680: Formula: (= v_~x~0_11 0) InVars {} OutVars{~x~0=v_~x~0_11} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [464] L680-->L681: Formula: (= v_~x$flush_delayed~0_5 0) InVars {} OutVars{~x$flush_delayed~0=v_~x$flush_delayed~0_5} AuxVars[] AssignedVars[~x$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 [386] L681-->L682: Formula: (= v_~x$mem_tmp~0_3 0) InVars {} OutVars{~x$mem_tmp~0=v_~x$mem_tmp~0_3} AuxVars[] AssignedVars[~x$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 [514] L682-->L683: Formula: (= v_~x$r_buff0_thd0~0_2 0) InVars {} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_2} AuxVars[] AssignedVars[~x$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 [453] L683-->L684: Formula: (= v_~x$r_buff0_thd1~0_14 0) InVars {} OutVars{~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_14} AuxVars[] AssignedVars[~x$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 [380] L684-->L685: Formula: (= v_~x$r_buff0_thd2~0_43 0) InVars {} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_43} AuxVars[] AssignedVars[~x$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 [492] L685-->L686: Formula: (= v_~x$r_buff1_thd0~0_2 0) InVars {} OutVars{~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_2} AuxVars[] AssignedVars[~x$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 [419] L686-->L687: Formula: (= v_~x$r_buff1_thd1~0_9 0) InVars {} OutVars{~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_9} AuxVars[] AssignedVars[~x$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 [373] L687-->L688: Formula: (= v_~x$r_buff1_thd2~0_25 0) InVars {} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_25} AuxVars[] AssignedVars[~x$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 [481] L688-->L689: Formula: (= v_~x$read_delayed~0_1 0) InVars {} OutVars{~x$read_delayed~0=v_~x$read_delayed~0_1} AuxVars[] AssignedVars[~x$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 [416] L689-->L690: Formula: (and (= v_~x$read_delayed_var~0.offset_1 0) (= v_~x$read_delayed_var~0.base_1 0)) InVars {} OutVars{~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_1, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~x$read_delayed_var~0.offset, ~x$read_delayed_var~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 [523] L690-->L691: Formula: (= v_~x$w_buff0~0_11 0) InVars {} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_11} AuxVars[] AssignedVars[~x$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 [461] L691-->L692: Formula: (= v_~x$w_buff0_used~0_55 0) InVars {} OutVars{~x$w_buff0_used~0=v_~x$w_buff0_used~0_55} AuxVars[] AssignedVars[~x$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 [385] L692-->L693: Formula: (= v_~x$w_buff1~0_10 0) InVars {} OutVars{~x$w_buff1~0=v_~x$w_buff1~0_10} AuxVars[] AssignedVars[~x$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 [512] L693-->L695: Formula: (= v_~x$w_buff1_used~0_32 0) InVars {} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_32} AuxVars[] AssignedVars[~x$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 [379] L695-->L696: Formula: (= v_~y~0_3 0) InVars {} OutVars{~y~0=v_~y~0_3} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [491] L696-->L697: Formula: (= v_~weak$$choice0~0_2 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_2} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [418] L697-->L-1-1: Formula: (= v_~weak$$choice2~0_14 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_14} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [513] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [511] L-1-2-->L773: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_1|, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_1|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_1|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_1|, ULTIMATE.start_main_~#t1712~0.offset=|v_ULTIMATE.start_main_~#t1712~0.offset_1|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_1|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_1|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_1|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_1|, ULTIMATE.start_main_~#t1712~0.base=|v_ULTIMATE.start_main_~#t1712~0.base_1|, ULTIMATE.start_main_~#t1711~0.base=|v_ULTIMATE.start_main_~#t1711~0.base_1|, ULTIMATE.start_main_~#t1711~0.offset=|v_ULTIMATE.start_main_~#t1711~0.offset_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet40, ULTIMATE.start_main_#t~nondet41, ULTIMATE.start_main_~#t1712~0.base, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_~#t1712~0.offset, ULTIMATE.start_main_~#t1711~0.base, ULTIMATE.start_main_~#t1711~0.offset, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [503] L773-->L773-1: Formula: (and (= (store |v_#length_2| |v_ULTIMATE.start_main_~#t1711~0.base_2| 4) |v_#length_1|) (= (select |v_#valid_2| |v_ULTIMATE.start_main_~#t1711~0.base_2|) 0) (= |v_ULTIMATE.start_main_~#t1711~0.offset_2| 0) (not (= 0 |v_ULTIMATE.start_main_~#t1711~0.base_2|)) (= |v_#valid_1| (store |v_#valid_2| |v_ULTIMATE.start_main_~#t1711~0.base_2| 1))) InVars {#length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#length=|v_#length_1|, ULTIMATE.start_main_~#t1711~0.base=|v_ULTIMATE.start_main_~#t1711~0.base_2|, ULTIMATE.start_main_~#t1711~0.offset=|v_ULTIMATE.start_main_~#t1711~0.offset_2|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1711~0.base, ULTIMATE.start_main_~#t1711~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [485] L773-1-->L774: Formula: (= (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1711~0.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1711~0.base_3|) |v_ULTIMATE.start_main_~#t1711~0.offset_3| 0)) |v_#memory_int_1|) InVars {#memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t1711~0.base=|v_ULTIMATE.start_main_~#t1711~0.base_3|, ULTIMATE.start_main_~#t1711~0.offset=|v_ULTIMATE.start_main_~#t1711~0.offset_3|} OutVars{#memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t1711~0.base=|v_ULTIMATE.start_main_~#t1711~0.base_3|, ULTIMATE.start_main_~#t1711~0.offset=|v_ULTIMATE.start_main_~#t1711~0.offset_3|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 [642] L774-->P0ENTRY: Formula: (and (= 0 |v_Thread0_P0_#in~arg.offset_3|) (= 0 v_Thread0_P0_thidvar0_2) (= 0 |v_Thread0_P0_#in~arg.base_3|)) InVars {} OutVars{Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_3|, Thread0_P0_thidvar0=v_Thread0_P0_thidvar0_2, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P0_#in~arg.base, Thread0_P0_thidvar0, Thread0_P0_#in~arg.offset] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [530] P0ENTRY-->L4: Formula: (and (= v_Thread0_P0_~arg.base_1 |v_Thread0_P0_#in~arg.base_1|) (= v_Thread0_P0_~arg.offset_1 |v_Thread0_P0_#in~arg.offset_1|) (= v_~x$w_buff0~0_1 1) (= v_Thread0_P0___VERIFIER_assert_~expression_1 |v_Thread0_P0___VERIFIER_assert_#in~expression_1|) (= v_~x$w_buff1~0_1 v_~x$w_buff0~0_2) (= v_~x$w_buff1_used~0_1 v_~x$w_buff0_used~0_2) (= v_~x$w_buff0_used~0_1 1) (= |v_Thread0_P0___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= 0 (mod v_~x$w_buff1_used~0_1 256))) (not (= (mod v_~x$w_buff0_used~0_1 256) 0)))) 1 0))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_2, Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_2} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_1, Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_1, Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_~arg.offset=v_Thread0_P0_~arg.offset_1, ~x$w_buff1~0=v_~x$w_buff1~0_1, Thread0_P0_~arg.base=v_Thread0_P0_~arg.base_1, Thread0_P0___VERIFIER_assert_#in~expression=|v_Thread0_P0___VERIFIER_assert_#in~expression_1|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_1, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_1} AuxVars[] AssignedVars[~x$w_buff0~0, Thread0_P0___VERIFIER_assert_~expression, Thread0_P0_~arg.offset, ~x$w_buff1~0, Thread0_P0_~arg.base, Thread0_P0___VERIFIER_assert_#in~expression, ~x$w_buff1_used~0, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [532] L4-->L4-3: Formula: (not (= 0 v_Thread0_P0___VERIFIER_assert_~expression_3)) InVars {Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_3} OutVars{Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [439] L774-1-->L775: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet40] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [535] L4-3-->L715: Formula: (and (= v_~x$r_buff0_thd1~0_1 1) (= v_~x$r_buff1_thd0~0_1 v_~x$r_buff0_thd0~0_1) (= v_~x$r_buff1_thd2~0_1 v_~x$r_buff0_thd2~0_1) (= v_~x$r_buff1_thd1~0_1 v_~x$r_buff0_thd1~0_2) (= v_~y~0_1 1)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_2, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_1, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_1, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_1, ~y~0=v_~y~0_1, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_1} AuxVars[] AssignedVars[~x$r_buff0_thd1~0, ~x$r_buff1_thd2~0, ~x$r_buff1_thd1~0, ~y~0, ~x$r_buff1_thd0~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 0 [536] L715-->L715-5: Formula: (and (not (= 0 (mod v_~x$w_buff0_used~0_3 256))) (= |v_Thread0_P0_#t~ite4_1| v_~x$w_buff0~0_3) (not (= 0 (mod v_~x$r_buff0_thd1~0_3 256)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_3, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_3, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_3, Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_3, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} AuxVars[] AssignedVars[Thread0_P0_#t~ite4] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] -1 [363] L775-->L775-1: Formula: (and (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t1712~0.base_2| 4)) (= |v_#valid_3| (store |v_#valid_4| |v_ULTIMATE.start_main_~#t1712~0.base_2| 1)) (= |v_ULTIMATE.start_main_~#t1712~0.offset_2| 0) (not (= 0 |v_ULTIMATE.start_main_~#t1712~0.base_2|)) (= 0 (select |v_#valid_4| |v_ULTIMATE.start_main_~#t1712~0.base_2|))) InVars {#length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{#length=|v_#length_3|, ULTIMATE.start_main_~#t1712~0.base=|v_ULTIMATE.start_main_~#t1712~0.base_2|, ULTIMATE.start_main_~#t1712~0.offset=|v_ULTIMATE.start_main_~#t1712~0.offset_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1712~0.base, #valid, #length, ULTIMATE.start_main_~#t1712~0.offset] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] -1 [366] L775-1-->L776: Formula: (= |v_#memory_int_3| (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1712~0.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1712~0.base_3|) |v_ULTIMATE.start_main_~#t1712~0.offset_3| 1))) InVars {#memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t1712~0.base=|v_ULTIMATE.start_main_~#t1712~0.base_3|, ULTIMATE.start_main_~#t1712~0.offset=|v_ULTIMATE.start_main_~#t1712~0.offset_3|} OutVars{#memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t1712~0.base=|v_ULTIMATE.start_main_~#t1712~0.base_3|, ULTIMATE.start_main_~#t1712~0.offset=|v_ULTIMATE.start_main_~#t1712~0.offset_3|} AuxVars[] AssignedVars[#memory_int] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] FORK -1 [643] L776-->P1ENTRY: Formula: (and (= 0 |v_Thread1_P1_#in~arg.base_3|) (= 0 |v_Thread1_P1_#in~arg.offset_3|) (= 1 v_Thread1_P1_thidvar0_2)) InVars {} OutVars{Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_3|, Thread1_P1_thidvar0=v_Thread1_P1_thidvar0_2, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread1_P1_#in~arg.base, Thread1_P1_thidvar0, Thread1_P1_#in~arg.offset] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 1 [557] P1ENTRY-->L739: Formula: (and (= v_Thread1_P1_~arg.offset_1 |v_Thread1_P1_#in~arg.offset_1|) (= v_Thread1_P1_~arg.base_1 |v_Thread1_P1_#in~arg.base_1|) (= v_~y~0_2 2) (= v_~__unbuffered_p1_EAX~0_1 v_~y~0_2) (= v_~x$flush_delayed~0_1 v_~weak$$choice2~0_7) (= v_~weak$$choice0~0_1 (ite (= 0 (+ |v_Thread1_P1_#t~nondet10.base_1| |v_Thread1_P1_#t~nondet10.offset_1|)) 0 1)) (= v_~x$mem_tmp~0_1 v_~x~0_3) (= v_~weak$$choice2~0_7 (ite (= (+ |v_Thread1_P1_#t~nondet11.offset_1| |v_Thread1_P1_#t~nondet11.base_1|) 0) 0 1))) InVars {Thread1_P1_#t~nondet10.offset=|v_Thread1_P1_#t~nondet10.offset_1|, Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_#t~nondet10.base=|v_Thread1_P1_#t~nondet10.base_1|, Thread1_P1_#t~nondet11.base=|v_Thread1_P1_#t~nondet11.base_1|, Thread1_P1_#t~nondet11.offset=|v_Thread1_P1_#t~nondet11.offset_1|, ~x~0=v_~x~0_3, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|} OutVars{Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_~arg.offset=v_Thread1_P1_~arg.offset_1, Thread1_P1_#t~nondet10.base=|v_Thread1_P1_#t~nondet10.base_2|, ~x$flush_delayed~0=v_~x$flush_delayed~0_1, ~x$mem_tmp~0=v_~x$mem_tmp~0_1, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|, Thread1_P1_#t~nondet10.offset=|v_Thread1_P1_#t~nondet10.offset_2|, ~weak$$choice0~0=v_~weak$$choice0~0_1, Thread1_P1_~arg.base=v_Thread1_P1_~arg.base_1, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, Thread1_P1_#t~nondet11.base=|v_Thread1_P1_#t~nondet11.base_2|, ~weak$$choice2~0=v_~weak$$choice2~0_7, ~y~0=v_~y~0_2, Thread1_P1_#t~nondet11.offset=|v_Thread1_P1_#t~nondet11.offset_2|, ~x~0=v_~x~0_3} AuxVars[] AssignedVars[Thread1_P1_#t~nondet10.offset, ~weak$$choice0~0, Thread1_P1_~arg.offset, Thread1_P1_#t~nondet10.base, Thread1_P1_~arg.base, ~__unbuffered_p1_EAX~0, ~x$flush_delayed~0, Thread1_P1_#t~nondet11.base, ~x$mem_tmp~0, ~weak$$choice2~0, ~y~0, Thread1_P1_#t~nondet11.offset] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [558] L739-->L739-5: Formula: (and (= |v_Thread1_P1_#t~ite13_1| v_~x~0_4) (let ((.cse0 (= (mod v_~x$r_buff0_thd2~0_15 256) 0))) (or (and .cse0 (= (mod v_~x$w_buff1_used~0_17 256) 0)) (= (mod v_~x$w_buff0_used~0_26 256) 0) (and (= 0 (mod v_~x$r_buff1_thd2~0_9 256)) .cse0)))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_17, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_9, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_15, ~x~0=v_~x~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_26} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_17, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_9, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_15, ~x~0=v_~x~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_26} AuxVars[] AssignedVars[Thread1_P1_#t~ite13] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite13|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [560] L739-5-->L740: Formula: (= v_~x~0_6 |v_Thread1_P1_#t~ite13_2|) InVars {Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_2|} OutVars{Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_1|, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_3|, ~x~0=v_~x~0_6} AuxVars[] AssignedVars[Thread1_P1_#t~ite12, Thread1_P1_#t~ite13, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [563] L740-->L740-8: Formula: (and (not (= (mod v_~weak$$choice2~0_8 256) 0)) (= |v_Thread1_P1_#t~ite16_1| v_~x$w_buff0~0_5)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_5, ~weak$$choice2~0=v_~weak$$choice2~0_8} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_5, ~weak$$choice2~0=v_~weak$$choice2~0_8, Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite16] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite16|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [566] L740-8-->L741: Formula: (= v_~x$w_buff0~0_10 |v_Thread1_P1_#t~ite16_2|) InVars {Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_2|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_10, Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_1|, Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_3|, Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_1|} AuxVars[] AssignedVars[~x$w_buff0~0, Thread1_P1_#t~ite14, Thread1_P1_#t~ite16, Thread1_P1_#t~ite15] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [569] L741-->L741-8: Formula: (and (not (= (mod v_~weak$$choice2~0_10 256) 0)) (= |v_Thread1_P1_#t~ite19_1| v_~x$w_buff1~0_5)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_10, ~x$w_buff1~0=v_~x$w_buff1~0_5} OutVars{Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_1|, ~weak$$choice2~0=v_~weak$$choice2~0_10, ~x$w_buff1~0=v_~x$w_buff1~0_5} AuxVars[] AssignedVars[Thread1_P1_#t~ite19] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite19|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [574] L741-8-->L742: Formula: (= v_~x$w_buff1~0_9 |v_Thread1_P1_#t~ite19_2|) InVars {Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_2|} OutVars{Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_3|, Thread1_P1_#t~ite18=|v_Thread1_P1_#t~ite18_1|, ~x$w_buff1~0=v_~x$w_buff1~0_9, Thread1_P1_#t~ite17=|v_Thread1_P1_#t~ite17_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite19, ~x$w_buff1~0, Thread1_P1_#t~ite18, Thread1_P1_#t~ite17] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [578] L742-->L742-8: Formula: (and (not (= (mod v_~weak$$choice2~0_12 256) 0)) (= |v_Thread1_P1_#t~ite22_1| v_~x$w_buff0_used~0_50)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_12, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_50} OutVars{Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_1|, ~weak$$choice2~0=v_~weak$$choice2~0_12, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_50} AuxVars[] AssignedVars[Thread1_P1_#t~ite22] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite22|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [583] L742-8-->L743: Formula: (= v_~x$w_buff0_used~0_15 |v_Thread1_P1_#t~ite22_2|) InVars {Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_2|} OutVars{Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_3|, Thread1_P1_#t~ite21=|v_Thread1_P1_#t~ite21_1|, Thread1_P1_#t~ite20=|v_Thread1_P1_#t~ite20_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_15} AuxVars[] AssignedVars[Thread1_P1_#t~ite21, Thread1_P1_#t~ite20, Thread1_P1_#t~ite22, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [587] L743-->L743-8: Formula: (and (= |v_Thread1_P1_#t~ite25_1| v_~x$w_buff1_used~0_9) (not (= (mod v_~weak$$choice2~0_1 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_1, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_9} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_9, Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_1|, ~weak$$choice2~0=v_~weak$$choice2~0_1} AuxVars[] AssignedVars[Thread1_P1_#t~ite25] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite25|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [592] L743-8-->L744: Formula: (= v_~x$w_buff1_used~0_12 |v_Thread1_P1_#t~ite25_2|) InVars {Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_2|} OutVars{Thread1_P1_#t~ite23=|v_Thread1_P1_#t~ite23_1|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_12, Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_3|, Thread1_P1_#t~ite24=|v_Thread1_P1_#t~ite24_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite23, ~x$w_buff1_used~0, Thread1_P1_#t~ite25, Thread1_P1_#t~ite24] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [596] L744-->L744-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_3 256))) (= |v_Thread1_P1_#t~ite28_1| v_~x$r_buff0_thd2~0_7)) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_7, ~weak$$choice2~0=v_~weak$$choice2~0_3} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_7, ~weak$$choice2~0=v_~weak$$choice2~0_3, Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite28] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite28|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [601] L744-8-->L745: Formula: (= v_~x$r_buff0_thd2~0_12 |v_Thread1_P1_#t~ite28_2|) InVars {Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_2|} OutVars{Thread1_P1_#t~ite27=|v_Thread1_P1_#t~ite27_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_12, Thread1_P1_#t~ite26=|v_Thread1_P1_#t~ite26_1|, Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_3|} AuxVars[] AssignedVars[Thread1_P1_#t~ite27, ~x$r_buff0_thd2~0, Thread1_P1_#t~ite26, Thread1_P1_#t~ite28] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [605] L745-->L745-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_5 256))) (= |v_Thread1_P1_#t~ite31_1| v_~x$r_buff1_thd2~0_6)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_5, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6, Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_1|, ~weak$$choice2~0=v_~weak$$choice2~0_5} AuxVars[] AssignedVars[Thread1_P1_#t~ite31] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite31|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [610] L745-8-->L747: Formula: (and (= v_~x$r_buff1_thd2~0_11 |v_Thread1_P1_#t~ite31_2|) (= v_~__unbuffered_p1_EBX~0_1 v_~x~0_5)) InVars {Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_2|, ~x~0=v_~x~0_5} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_1, Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_3|, Thread1_P1_#t~ite30=|v_Thread1_P1_#t~ite30_1|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_11, ~x~0=v_~x~0_5, Thread1_P1_#t~ite29=|v_Thread1_P1_#t~ite29_1|} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0, Thread1_P1_#t~ite31, Thread1_P1_#t~ite30, ~x$r_buff1_thd2~0, Thread1_P1_#t~ite29] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [614] L747-->L747-2: Formula: (and (= |v_Thread1_P1_#t~ite32_1| v_~x$mem_tmp~0_2) (not (= (mod v_~x$flush_delayed~0_2 256) 0))) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_2, ~x$mem_tmp~0=v_~x$mem_tmp~0_2} OutVars{~x$mem_tmp~0=v_~x$mem_tmp~0_2, ~x$flush_delayed~0=v_~x$flush_delayed~0_2, Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite32] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [538] L715-5-->L716: Formula: (= v_~x~0_2 |v_Thread0_P0_#t~ite4_2|) InVars {Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_2|} OutVars{Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_3|, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_1|, ~x~0=v_~x~0_2} AuxVars[] AssignedVars[Thread0_P0_#t~ite4, Thread0_P0_#t~ite3, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [619] L747-2-->L751: Formula: (and (= v_~x~0_8 |v_Thread1_P1_#t~ite32_3|) (= v_~x$flush_delayed~0_4 0)) InVars {Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_3|} OutVars{~x$flush_delayed~0=v_~x$flush_delayed~0_4, Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_4|, ~x~0=v_~x~0_8} AuxVars[] AssignedVars[~x$flush_delayed~0, Thread1_P1_#t~ite32, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [541] L716-->L716-2: Formula: (and (= |v_Thread0_P0_#t~ite5_1| 0) (not (= 0 (mod v_~x$r_buff0_thd1~0_5 256))) (not (= (mod v_~x$w_buff0_used~0_5 256) 0))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} AuxVars[] AssignedVars[Thread0_P0_#t~ite5] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite5|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [544] L716-2-->L717: Formula: (= v_~x$w_buff0_used~0_7 |v_Thread0_P0_#t~ite5_3|) InVars {Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_3|} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_7} AuxVars[] AssignedVars[Thread0_P0_#t~ite5, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [546] L717-->L717-2: Formula: (and (= |v_Thread0_P0_#t~ite6_2| v_~x$w_buff1_used~0_5) (or (= 0 (mod v_~x$r_buff1_thd1~0_5 256)) (= 0 (mod v_~x$w_buff1_used~0_5 256))) (or (= (mod v_~x$w_buff0_used~0_9 256) 0) (= (mod v_~x$r_buff0_thd1~0_8 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_5, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_9} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_5, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_5, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_9} AuxVars[] AssignedVars[Thread0_P0_#t~ite6] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite6|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [547] L717-2-->L718: Formula: (= v_~x$w_buff1_used~0_6 |v_Thread0_P0_#t~ite6_3|) InVars {Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_3|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_6, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, Thread0_P0_#t~ite6] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [549] L718-->L718-2: Formula: (and (= |v_Thread0_P0_#t~ite7_2| v_~x$r_buff0_thd1~0_10) (or (= (mod v_~x$w_buff0_used~0_11 256) 0) (= (mod v_~x$r_buff0_thd1~0_10 256) 0))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_11} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_2|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_11} AuxVars[] AssignedVars[Thread0_P0_#t~ite7] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite7|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [550] L718-2-->L719: Formula: (= v_~x$r_buff0_thd1~0_11 |v_Thread0_P0_#t~ite7_3|) InVars {Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_3|} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_4|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_11} AuxVars[] AssignedVars[~x$r_buff0_thd1~0, Thread0_P0_#t~ite7] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [552] L719-->L719-2: Formula: (and (or (= 0 (mod v_~x$w_buff0_used~0_13 256)) (= (mod v_~x$r_buff0_thd1~0_13 256) 0)) (= |v_Thread0_P0_#t~ite8_2| v_~x$r_buff1_thd1~0_7) (or (= (mod v_~x$r_buff1_thd1~0_7 256) 0) (= 0 (mod v_~x$w_buff1_used~0_8 256)))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_8, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_13, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_13} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_8, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_13, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_13} AuxVars[] AssignedVars[Thread0_P0_#t~ite8] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite8|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 [553] L719-2-->L724: Formula: (and (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1)) (= v_~x$r_buff1_thd1~0_8 |v_Thread0_P0_#t~ite8_3|)) InVars {Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_8, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_4|} AuxVars[] AssignedVars[~__unbuffered_cnt~0, ~x$r_buff1_thd1~0, Thread0_P0_#t~ite8] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [622] L751-->L751-2: Formula: (or (= 0 (mod v_~x$w_buff0_used~0_35 256)) (= 0 (mod v_~x$r_buff0_thd2~0_24 256))) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_24, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_35} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_24, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_35} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [625] L751-2-->L751-4: Formula: (and (= |v_Thread1_P1_#t~ite33_3| v_~x~0_9) (or (= 0 (mod v_~x$w_buff1_used~0_22 256)) (= (mod v_~x$r_buff1_thd2~0_15 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_22, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_15, ~x~0=v_~x~0_9} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_22, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_15, Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_3|, ~x~0=v_~x~0_9} AuxVars[] AssignedVars[Thread1_P1_#t~ite33] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite33|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [628] L751-4-->L751-5: Formula: (= |v_Thread1_P1_#t~ite34_4| |v_Thread1_P1_#t~ite33_4|) InVars {Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_4|} OutVars{Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_4|, Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_4|} AuxVars[] AssignedVars[Thread1_P1_#t~ite34] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite33|=0, |Thread1_P1_#t~ite34|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [623] L751-5-->L752: Formula: (= v_~x~0_10 |v_Thread1_P1_#t~ite34_2|) InVars {Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_2|} OutVars{Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_1|, Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_3|, ~x~0=v_~x~0_10} AuxVars[] AssignedVars[Thread1_P1_#t~ite33, Thread1_P1_#t~ite34, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [627] L752-->L752-2: Formula: (and (or (= 0 (mod v_~x$r_buff0_thd2~0_28 256)) (= (mod v_~x$w_buff0_used~0_39 256) 0)) (= |v_Thread1_P1_#t~ite35_2| v_~x$w_buff0_used~0_39)) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_28, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_39} OutVars{Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_28, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_39} AuxVars[] AssignedVars[Thread1_P1_#t~ite35] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite35|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [629] L752-2-->L753: Formula: (= v_~x$w_buff0_used~0_40 |v_Thread1_P1_#t~ite35_3|) InVars {Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_3|} OutVars{Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_40} AuxVars[] AssignedVars[Thread1_P1_#t~ite35, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [631] L753-->L753-2: Formula: (and (= |v_Thread1_P1_#t~ite36_2| v_~x$w_buff1_used~0_26) (or (= 0 (mod v_~x$r_buff0_thd2~0_32 256)) (= (mod v_~x$w_buff0_used~0_44 256) 0)) (or (= 0 (mod v_~x$r_buff1_thd2~0_19 256)) (= (mod v_~x$w_buff1_used~0_26 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_26, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_19, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_32, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_44} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_26, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_19, Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_32, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_44} AuxVars[] AssignedVars[Thread1_P1_#t~ite36] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite36|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [632] L753-2-->L754: Formula: (= v_~x$w_buff1_used~0_27 |v_Thread1_P1_#t~ite36_3|) InVars {Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_3|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_27, Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, Thread1_P1_#t~ite36] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [634] L754-->L754-2: Formula: (and (= |v_Thread1_P1_#t~ite37_2| v_~x$r_buff0_thd2~0_36) (or (= (mod v_~x$w_buff0_used~0_48 256) 0) (= (mod v_~x$r_buff0_thd2~0_36 256) 0))) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_36, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_48} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_36, Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_48} AuxVars[] AssignedVars[Thread1_P1_#t~ite37] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite37|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [635] L754-2-->L755: Formula: (= v_~x$r_buff0_thd2~0_37 |v_Thread1_P1_#t~ite37_3|) InVars {Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_3|} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_37, Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_4|} AuxVars[] AssignedVars[~x$r_buff0_thd2~0, Thread1_P1_#t~ite37] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [637] L755-->L755-2: Formula: (and (= |v_Thread1_P1_#t~ite38_2| v_~x$r_buff1_thd2~0_21) (or (= (mod v_~x$r_buff0_thd2~0_39 256) 0) (= (mod v_~x$w_buff0_used~0_51 256) 0)) (or (= (mod v_~x$r_buff1_thd2~0_21 256) 0) (= (mod v_~x$w_buff1_used~0_29 256) 0))) InVars {~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_21, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_29, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_39, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_51} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_21, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_29, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_39, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_51} AuxVars[] AssignedVars[Thread1_P1_#t~ite38] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite38|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 [638] L755-2-->L760: Formula: (and (= v_~x$r_buff1_thd2~0_22 |v_Thread1_P1_#t~ite38_3|) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_3|} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_22, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_4|} AuxVars[] AssignedVars[~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, Thread1_P1_#t~ite38] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [480] L776-1-->L780: Formula: (= v_~main$tmp_guard0~0_1 (ite (= (ite (= v_~__unbuffered_cnt~0_5 2) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_2|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet41, ~main$tmp_guard0~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [405] L780-->L782: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_2 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [445] L782-->L782-2: Formula: (or (= 0 (mod v_~x$w_buff0_used~0_57 256)) (= (mod v_~x$r_buff0_thd0~0_4 256) 0)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_57} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_57} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [450] L782-2-->L782-4: Formula: (and (= |v_ULTIMATE.start_main_#t~ite42_3| v_~x~0_12) (or (= 0 (mod v_~x$w_buff1_used~0_34 256)) (= 0 (mod v_~x$r_buff1_thd0~0_4 256)))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_34, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_4, ~x~0=v_~x~0_12} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_34, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_4, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_3|, ~x~0=v_~x~0_12} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite42] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [456] L782-4-->L782-5: Formula: (= |v_ULTIMATE.start_main_#t~ite43_3| |v_ULTIMATE.start_main_#t~ite42_4|) InVars {ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} OutVars{ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_3|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [429] L782-5-->L783: Formula: (= v_~x~0_13 |v_ULTIMATE.start_main_#t~ite43_5|) InVars {ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_5|} OutVars{ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_4|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_5|, ~x~0=v_~x~0_13} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [400] L783-->L783-2: Formula: (and (or (= (mod v_~x$r_buff0_thd0~0_6 256) 0) (= 0 (mod v_~x$w_buff0_used~0_59 256))) (= |v_ULTIMATE.start_main_#t~ite44_3| v_~x$w_buff0_used~0_59)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_59} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_59} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite44] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [378] L783-2-->L784: Formula: (= v_~x$w_buff0_used~0_60 |v_ULTIMATE.start_main_#t~ite44_5|) InVars {ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_5|} OutVars{ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_60} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite44, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [501] L784-->L784-2: Formula: (and (or (= (mod v_~x$r_buff0_thd0~0_8 256) 0) (= (mod v_~x$w_buff0_used~0_62 256) 0)) (= |v_ULTIMATE.start_main_#t~ite45_3| v_~x$w_buff1_used~0_36) (or (= (mod v_~x$r_buff1_thd0~0_6 256) 0) (= (mod v_~x$w_buff1_used~0_36 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_8, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_36, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_62} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_8, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_36, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_62} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite45] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [488] L784-2-->L785: Formula: (= v_~x$w_buff1_used~0_37 |v_ULTIMATE.start_main_#t~ite45_5|) InVars {ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_5|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_37, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite45] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [433] L785-->L785-2: Formula: (and (or (= 0 (mod v_~x$r_buff0_thd0~0_10 256)) (= 0 (mod v_~x$w_buff0_used~0_64 256))) (= |v_ULTIMATE.start_main_#t~ite46_3| v_~x$r_buff0_thd0~0_10)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_64} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_10, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_64} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [441] L785-2-->L786: Formula: (= v_~x$r_buff0_thd0~0_11 |v_ULTIMATE.start_main_#t~ite46_5|) InVars {ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_5|} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_11, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_4|} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite46] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [360] L786-->L786-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite47_3| v_~x$r_buff1_thd0~0_8) (or (= 0 (mod v_~x$r_buff0_thd0~0_13 256)) (= (mod v_~x$w_buff0_used~0_66 256) 0)) (or (= 0 (mod v_~x$r_buff1_thd0~0_8 256)) (= 0 (mod v_~x$w_buff1_used~0_39 256)))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_13, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_39, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_66} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_3|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_13, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_39, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_66} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [367] L786-2-->L791: Formula: (and (= v_~x$r_buff1_thd0~0_9 |v_ULTIMATE.start_main_#t~ite47_5|) (= v_~main$tmp_guard1~0_2 (ite (= (ite (not (and (= 2 v_~y~0_4) (= 2 v_~__unbuffered_p1_EAX~0_2) (= 0 v_~__unbuffered_p1_EBX~0_2))) 1 0) 0) 0 1))) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_5|, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~y~0=v_~y~0_4} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_4|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_2, ~y~0=v_~y~0_4, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_9} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ~main$tmp_guard1~0, ~x$r_buff1_thd0~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [404] L791-->L791-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_3 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [408] L791-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [401] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [395] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 [392] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1711~0.base, main_~#t1711~0.offset, main_~#t1712~0.base, main_~#t1712~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t1711~0.base, main_~#t1711~0.offset := #Ultimate.alloc(4); srcloc: L773 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t1711~0.base, main_~#t1711~0.offset, 4); srcloc: L773-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 1;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet40; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd1~0 := 1;~y~0 := 1; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite4 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] -1 SUMMARY for call main_~#t1712~0.base, main_~#t1712~0.offset := #Ultimate.alloc(4); srcloc: L775 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] -1 SUMMARY for call write~int(1, main_~#t1712~0.base, main_~#t1712~0.offset, 4); srcloc: L775-1 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] FORK -1 fork 1 P1(0, 0); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 2;~__unbuffered_p1_EAX~0 := ~y~0;~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1);havoc #t~nondet10.base, #t~nondet10.offset;~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~x$flush_delayed~0 := ~weak$$choice2~0;~x$mem_tmp~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256);#t~ite13 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x~0 := #t~ite13;havoc #t~ite13;havoc #t~ite12; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff0~0 := #t~ite16;havoc #t~ite16;havoc #t~ite15;havoc #t~ite14; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~x$w_buff1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff1~0 := #t~ite19;havoc #t~ite19;havoc #t~ite17;havoc #t~ite18; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff0_used~0 := #t~ite22;havoc #t~ite20;havoc #t~ite22;havoc #t~ite21; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff1_used~0 := #t~ite25;havoc #t~ite25;havoc #t~ite24;havoc #t~ite23; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite28 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite28|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$r_buff0_thd2~0 := #t~ite28;havoc #t~ite26;havoc #t~ite27;havoc #t~ite28; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite31 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite31|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$r_buff1_thd2~0 := #t~ite31;havoc #t~ite30;havoc #t~ite29;havoc #t~ite31;~__unbuffered_p1_EBX~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~x$flush_delayed~0 % 256;#t~ite32 := ~x$mem_tmp~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x~0 := #t~ite4;havoc #t~ite4;havoc #t~ite3; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 ~x~0 := #t~ite32;havoc #t~ite32;~x$flush_delayed~0 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite5 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite6 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite7 := ~x$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite8 := ~x$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256);#t~ite33 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 #t~ite34 := #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |P1_#t~ite34|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x~0 := #t~ite34;havoc #t~ite34;havoc #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite35 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff0_used~0 := #t~ite35;havoc #t~ite35; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite36 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite36|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff1_used~0 := #t~ite36;havoc #t~ite36; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite37 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite37|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$r_buff0_thd2~0 := #t~ite37;havoc #t~ite37; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite38 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite38|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$r_buff1_thd2~0 := #t~ite38;havoc #t~ite38;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 havoc main_#t~nondet41;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);main_#t~ite42 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 main_#t~ite43 := main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x~0 := main_#t~ite43;havoc main_#t~ite43;havoc main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite44 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x$w_buff0_used~0 := main_#t~ite44;havoc main_#t~ite44; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite45 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x$w_buff1_used~0 := main_#t~ite45;havoc main_#t~ite45; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite46;havoc main_#t~ite46; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite47;havoc main_#t~ite47;~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 2 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1711~0.base, main_~#t1711~0.offset, main_~#t1712~0.base, main_~#t1712~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t1711~0.base, main_~#t1711~0.offset := #Ultimate.alloc(4); srcloc: L773 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t1711~0.base, main_~#t1711~0.offset, 4); srcloc: L773-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 1;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet40; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd1~0 := 1;~y~0 := 1; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite4 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] -1 SUMMARY for call main_~#t1712~0.base, main_~#t1712~0.offset := #Ultimate.alloc(4); srcloc: L775 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] -1 SUMMARY for call write~int(1, main_~#t1712~0.base, main_~#t1712~0.offset, 4); srcloc: L775-1 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] FORK -1 fork 1 P1(0, 0); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 2;~__unbuffered_p1_EAX~0 := ~y~0;~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1);havoc #t~nondet10.base, #t~nondet10.offset;~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~x$flush_delayed~0 := ~weak$$choice2~0;~x$mem_tmp~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256);#t~ite13 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x~0 := #t~ite13;havoc #t~ite13;havoc #t~ite12; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff0~0 := #t~ite16;havoc #t~ite16;havoc #t~ite15;havoc #t~ite14; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~x$w_buff1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff1~0 := #t~ite19;havoc #t~ite19;havoc #t~ite17;havoc #t~ite18; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=1, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff0_used~0 := #t~ite22;havoc #t~ite20;havoc #t~ite22;havoc #t~ite21; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff1_used~0 := #t~ite25;havoc #t~ite25;havoc #t~ite24;havoc #t~ite23; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite28 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite28|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$r_buff0_thd2~0 := #t~ite28;havoc #t~ite26;havoc #t~ite27;havoc #t~ite28; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite31 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite31|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$r_buff1_thd2~0 := #t~ite31;havoc #t~ite30;havoc #t~ite29;havoc #t~ite31;~__unbuffered_p1_EBX~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume 0 != ~x$flush_delayed~0 % 256;#t~ite32 := ~x$mem_tmp~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x~0 := #t~ite4;havoc #t~ite4;havoc #t~ite3; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 ~x~0 := #t~ite32;havoc #t~ite32;~x$flush_delayed~0 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite5 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite6 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite7 := ~x$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite8 := ~x$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 0 ~x$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256);#t~ite33 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 #t~ite34 := #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |P1_#t~ite34|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x~0 := #t~ite34;havoc #t~ite34;havoc #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite35 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff0_used~0 := #t~ite35;havoc #t~ite35; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite36 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite36|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$w_buff1_used~0 := #t~ite36;havoc #t~ite36; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite37 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite37|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$r_buff0_thd2~0 := #t~ite37;havoc #t~ite37; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite38 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite38|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] 1 ~x$r_buff1_thd2~0 := #t~ite38;havoc #t~ite38;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 havoc main_#t~nondet41;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);main_#t~ite42 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 main_#t~ite43 := main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x~0 := main_#t~ite43;havoc main_#t~ite43;havoc main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite44 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x$w_buff0_used~0 := main_#t~ite44;havoc main_#t~ite44; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite45 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x$w_buff1_used~0 := main_#t~ite45;havoc main_#t~ite45; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite46;havoc main_#t~ite46; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite47;havoc main_#t~ite47;~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 2 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1711~0.base|=6, |ULTIMATE.start_main_~#t1711~0.offset|=0, |ULTIMATE.start_main_~#t1712~0.base|=5, |ULTIMATE.start_main_~#t1712~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1711~0.base, main_~#t1711~0.offset, main_~#t1712~0.base, main_~#t1712~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L773] -1 call main_~#t1711~0.base, main_~#t1711~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] -1 call write~int(0, main_~#t1711~0.base, main_~#t1711~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L698-L725] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L701] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L702] 0 ~x$w_buff0~0 := 1; [L703] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L704] 0 ~x$w_buff0_used~0 := 1; [L705] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L705] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] -1 havoc main_#t~nondet40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L706] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L707] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L708] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L709] 0 ~x$r_buff0_thd1~0 := 1; [L712] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L715] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L715] 0 #t~ite4 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L775] -1 call main_~#t1712~0.base, main_~#t1712~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] -1 call write~int(1, main_~#t1712~0.base, main_~#t1712~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L726-L761] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L729] 1 ~y~0 := 2; [L732] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L735] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1); [L735] 1 havoc #t~nondet10.base, #t~nondet10.offset; [L736] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L736] 1 havoc #t~nondet11.base, #t~nondet11.offset; [L737] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L738] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] 1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256); [L739] 1 #t~ite13 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] 1 ~x~0 := #t~ite13; [L739] 1 havoc #t~ite13; [L739] 1 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] 1 assume 0 != ~weak$$choice2~0 % 256; [L740] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] 1 ~x$w_buff0~0 := #t~ite16; [L740] 1 havoc #t~ite16; [L740] 1 havoc #t~ite15; [L740] 1 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] 1 assume 0 != ~weak$$choice2~0 % 256; [L741] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] 1 ~x$w_buff1~0 := #t~ite19; [L741] 1 havoc #t~ite19; [L741] 1 havoc #t~ite17; [L741] 1 havoc #t~ite18; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] 1 assume 0 != ~weak$$choice2~0 % 256; [L742] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] 1 ~x$w_buff0_used~0 := #t~ite22; [L742] 1 havoc #t~ite20; [L742] 1 havoc #t~ite22; [L742] 1 havoc #t~ite21; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] 1 assume 0 != ~weak$$choice2~0 % 256; [L743] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] 1 ~x$w_buff1_used~0 := #t~ite25; [L743] 1 havoc #t~ite25; [L743] 1 havoc #t~ite24; [L743] 1 havoc #t~ite23; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] 1 assume 0 != ~weak$$choice2~0 % 256; [L744] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L744] 1 havoc #t~ite26; [L744] 1 havoc #t~ite27; [L744] 1 havoc #t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] 1 assume 0 != ~weak$$choice2~0 % 256; [L745] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L745] 1 havoc #t~ite30; [L745] 1 havoc #t~ite29; [L745] 1 havoc #t~ite31; [L746] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L747] 1 assume 0 != ~x$flush_delayed~0 % 256; [L747] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L715] 0 ~x~0 := #t~ite4; [L715] 0 havoc #t~ite4; [L715] 0 havoc #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L747] 1 ~x~0 := #t~ite32; [L747] 1 havoc #t~ite32; [L748] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L716] 0 #t~ite5 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] 0 ~x$w_buff0_used~0 := #t~ite5; [L716] 0 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L717] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] 0 ~x$w_buff1_used~0 := #t~ite6; [L717] 0 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L718] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L718] 0 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L719] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L719] 0 havoc #t~ite8; [L722] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256); [L751] 1 #t~ite33 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 #t~ite34 := #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 ~x~0 := #t~ite34; [L751] 1 havoc #t~ite34; [L751] 1 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L752] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] 1 ~x$w_buff0_used~0 := #t~ite35; [L752] 1 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L753] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] 1 ~x$w_buff1_used~0 := #t~ite36; [L753] 1 havoc #t~ite36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L754] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L754] 1 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L755] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L755] 1 havoc #t~ite38; [L758] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L776] -1 havoc main_#t~nondet41; [L778] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L780] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L782] -1 main_#t~ite42 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 ~x~0 := main_#t~ite43; [L782] -1 havoc main_#t~ite43; [L782] -1 havoc main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L783] -1 main_#t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] -1 ~x$w_buff0_used~0 := main_#t~ite44; [L783] -1 havoc main_#t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L784] -1 main_#t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] -1 ~x$w_buff1_used~0 := main_#t~ite45; [L784] -1 havoc main_#t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L785] -1 main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] -1 ~x$r_buff0_thd0~0 := main_#t~ite46; [L785] -1 havoc main_#t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L786] -1 main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] -1 ~x$r_buff1_thd0~0 := main_#t~ite47; [L786] -1 havoc main_#t~ite47; [L789] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 2 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L791] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L791] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1711~0.base, main_~#t1711~0.offset, main_~#t1712~0.base, main_~#t1712~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L773] -1 call main_~#t1711~0.base, main_~#t1711~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] -1 call write~int(0, main_~#t1711~0.base, main_~#t1711~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L698-L725] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L701] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L702] 0 ~x$w_buff0~0 := 1; [L703] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L704] 0 ~x$w_buff0_used~0 := 1; [L705] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L705] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] -1 havoc main_#t~nondet40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L706] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L707] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L708] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L709] 0 ~x$r_buff0_thd1~0 := 1; [L712] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L715] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L715] 0 #t~ite4 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L775] -1 call main_~#t1712~0.base, main_~#t1712~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] -1 call write~int(1, main_~#t1712~0.base, main_~#t1712~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L726-L761] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L729] 1 ~y~0 := 2; [L732] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L735] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1); [L735] 1 havoc #t~nondet10.base, #t~nondet10.offset; [L736] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L736] 1 havoc #t~nondet11.base, #t~nondet11.offset; [L737] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L738] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] 1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256); [L739] 1 #t~ite13 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] 1 ~x~0 := #t~ite13; [L739] 1 havoc #t~ite13; [L739] 1 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] 1 assume 0 != ~weak$$choice2~0 % 256; [L740] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] 1 ~x$w_buff0~0 := #t~ite16; [L740] 1 havoc #t~ite16; [L740] 1 havoc #t~ite15; [L740] 1 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] 1 assume 0 != ~weak$$choice2~0 % 256; [L741] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] 1 ~x$w_buff1~0 := #t~ite19; [L741] 1 havoc #t~ite19; [L741] 1 havoc #t~ite17; [L741] 1 havoc #t~ite18; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] 1 assume 0 != ~weak$$choice2~0 % 256; [L742] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] 1 ~x$w_buff0_used~0 := #t~ite22; [L742] 1 havoc #t~ite20; [L742] 1 havoc #t~ite22; [L742] 1 havoc #t~ite21; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] 1 assume 0 != ~weak$$choice2~0 % 256; [L743] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] 1 ~x$w_buff1_used~0 := #t~ite25; [L743] 1 havoc #t~ite25; [L743] 1 havoc #t~ite24; [L743] 1 havoc #t~ite23; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] 1 assume 0 != ~weak$$choice2~0 % 256; [L744] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L744] 1 havoc #t~ite26; [L744] 1 havoc #t~ite27; [L744] 1 havoc #t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] 1 assume 0 != ~weak$$choice2~0 % 256; [L745] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L745] 1 havoc #t~ite30; [L745] 1 havoc #t~ite29; [L745] 1 havoc #t~ite31; [L746] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L747] 1 assume 0 != ~x$flush_delayed~0 % 256; [L747] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L715] 0 ~x~0 := #t~ite4; [L715] 0 havoc #t~ite4; [L715] 0 havoc #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L747] 1 ~x~0 := #t~ite32; [L747] 1 havoc #t~ite32; [L748] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L716] 0 #t~ite5 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] 0 ~x$w_buff0_used~0 := #t~ite5; [L716] 0 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L717] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] 0 ~x$w_buff1_used~0 := #t~ite6; [L717] 0 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L718] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L718] 0 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L719] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L719] 0 havoc #t~ite8; [L722] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256); [L751] 1 #t~ite33 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 #t~ite34 := #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 ~x~0 := #t~ite34; [L751] 1 havoc #t~ite34; [L751] 1 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L752] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] 1 ~x$w_buff0_used~0 := #t~ite35; [L752] 1 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L753] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] 1 ~x$w_buff1_used~0 := #t~ite36; [L753] 1 havoc #t~ite36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L754] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L754] 1 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L755] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L755] 1 havoc #t~ite38; [L758] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L776] -1 havoc main_#t~nondet41; [L778] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L780] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L782] -1 main_#t~ite42 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 ~x~0 := main_#t~ite43; [L782] -1 havoc main_#t~ite43; [L782] -1 havoc main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L783] -1 main_#t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] -1 ~x$w_buff0_used~0 := main_#t~ite44; [L783] -1 havoc main_#t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L784] -1 main_#t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] -1 ~x$w_buff1_used~0 := main_#t~ite45; [L784] -1 havoc main_#t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L785] -1 main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] -1 ~x$r_buff0_thd0~0 := main_#t~ite46; [L785] -1 havoc main_#t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L786] -1 main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] -1 ~x$r_buff1_thd0~0 := main_#t~ite47; [L786] -1 havoc main_#t~ite47; [L789] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 2 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L791] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L791] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0.base=6, main_~#t1711~0.offset=0, main_~#t1712~0.base=5, main_~#t1712~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1711~0, main_~#t1712~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L773] FCALL -1 call main_~#t1711~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FCALL -1 call write~int(0, main_~#t1711~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L698-L725] 0 ~arg := #in~arg; [L701] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L702] 0 ~x$w_buff0~0 := 1; [L703] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L704] 0 ~x$w_buff0_used~0 := 1; [L705] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L705] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] -1 havoc main_#t~nondet40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L706] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L707] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L708] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L709] 0 ~x$r_buff0_thd1~0 := 1; [L712] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L715] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L715] 0 #t~ite4 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L775] FCALL -1 call main_~#t1712~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FCALL -1 call write~int(1, main_~#t1712~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L726-L761] 1 ~arg := #in~arg; [L729] 1 ~y~0 := 2; [L732] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L735] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L735] 1 havoc #t~nondet10; [L736] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L736] 1 havoc #t~nondet11; [L737] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L738] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] COND TRUE 1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256) [L739] 1 #t~ite13 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] 1 ~x~0 := #t~ite13; [L739] 1 havoc #t~ite13; [L739] 1 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L740] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] 1 ~x$w_buff0~0 := #t~ite16; [L740] 1 havoc #t~ite16; [L740] 1 havoc #t~ite15; [L740] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L741] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] 1 ~x$w_buff1~0 := #t~ite19; [L741] 1 havoc #t~ite19; [L741] 1 havoc #t~ite17; [L741] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L742] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] 1 ~x$w_buff0_used~0 := #t~ite22; [L742] 1 havoc #t~ite20; [L742] 1 havoc #t~ite22; [L742] 1 havoc #t~ite21; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L743] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] 1 ~x$w_buff1_used~0 := #t~ite25; [L743] 1 havoc #t~ite25; [L743] 1 havoc #t~ite24; [L743] 1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L744] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L744] 1 havoc #t~ite26; [L744] 1 havoc #t~ite27; [L744] 1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L745] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L745] 1 havoc #t~ite30; [L745] 1 havoc #t~ite29; [L745] 1 havoc #t~ite31; [L746] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L747] COND TRUE 1 0 != ~x$flush_delayed~0 % 256 [L747] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L715] 0 ~x~0 := #t~ite4; [L715] 0 havoc #t~ite4; [L715] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L747] 1 ~x~0 := #t~ite32; [L747] 1 havoc #t~ite32; [L748] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L716] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] 0 ~x$w_buff0_used~0 := #t~ite5; [L716] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L717] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] 0 ~x$w_buff1_used~0 := #t~ite6; [L717] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L718] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L718] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L719] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L719] 0 havoc #t~ite8; [L722] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L751] 1 #t~ite33 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 ~x~0 := #t~ite34; [L751] 1 havoc #t~ite34; [L751] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L752] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] 1 ~x$w_buff0_used~0 := #t~ite35; [L752] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L753] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] 1 ~x$w_buff1_used~0 := #t~ite36; [L753] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L754] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L754] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L755] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L755] 1 havoc #t~ite38; [L758] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L776] -1 havoc main_#t~nondet41; [L778] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L780] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L782] -1 main_#t~ite42 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 ~x~0 := main_#t~ite43; [L782] -1 havoc main_#t~ite43; [L782] -1 havoc main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L783] -1 main_#t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] -1 ~x$w_buff0_used~0 := main_#t~ite44; [L783] -1 havoc main_#t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L784] -1 main_#t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] -1 ~x$w_buff1_used~0 := main_#t~ite45; [L784] -1 havoc main_#t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L785] -1 main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] -1 ~x$r_buff0_thd0~0 := main_#t~ite46; [L785] -1 havoc main_#t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L786] -1 main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] -1 ~x$r_buff1_thd0~0 := main_#t~ite47; [L786] -1 havoc main_#t~ite47; [L789] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 2 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L791] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L791] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1711~0, main_~#t1712~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L773] FCALL -1 call main_~#t1711~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FCALL -1 call write~int(0, main_~#t1711~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L698-L725] 0 ~arg := #in~arg; [L701] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L702] 0 ~x$w_buff0~0 := 1; [L703] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L704] 0 ~x$w_buff0_used~0 := 1; [L705] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L705] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] -1 havoc main_#t~nondet40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L706] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L707] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L708] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L709] 0 ~x$r_buff0_thd1~0 := 1; [L712] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L715] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L715] 0 #t~ite4 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L775] FCALL -1 call main_~#t1712~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FCALL -1 call write~int(1, main_~#t1712~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L726-L761] 1 ~arg := #in~arg; [L729] 1 ~y~0 := 2; [L732] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L735] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L735] 1 havoc #t~nondet10; [L736] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L736] 1 havoc #t~nondet11; [L737] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L738] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] COND TRUE 1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256) [L739] 1 #t~ite13 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] 1 ~x~0 := #t~ite13; [L739] 1 havoc #t~ite13; [L739] 1 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L740] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] 1 ~x$w_buff0~0 := #t~ite16; [L740] 1 havoc #t~ite16; [L740] 1 havoc #t~ite15; [L740] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L741] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] 1 ~x$w_buff1~0 := #t~ite19; [L741] 1 havoc #t~ite19; [L741] 1 havoc #t~ite17; [L741] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L742] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] 1 ~x$w_buff0_used~0 := #t~ite22; [L742] 1 havoc #t~ite20; [L742] 1 havoc #t~ite22; [L742] 1 havoc #t~ite21; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L743] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] 1 ~x$w_buff1_used~0 := #t~ite25; [L743] 1 havoc #t~ite25; [L743] 1 havoc #t~ite24; [L743] 1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L744] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L744] 1 havoc #t~ite26; [L744] 1 havoc #t~ite27; [L744] 1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L745] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L745] 1 havoc #t~ite30; [L745] 1 havoc #t~ite29; [L745] 1 havoc #t~ite31; [L746] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L747] COND TRUE 1 0 != ~x$flush_delayed~0 % 256 [L747] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L715] 0 ~x~0 := #t~ite4; [L715] 0 havoc #t~ite4; [L715] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L747] 1 ~x~0 := #t~ite32; [L747] 1 havoc #t~ite32; [L748] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L716] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] 0 ~x$w_buff0_used~0 := #t~ite5; [L716] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L717] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] 0 ~x$w_buff1_used~0 := #t~ite6; [L717] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L718] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L718] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L719] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L719] 0 havoc #t~ite8; [L722] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L751] 1 #t~ite33 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 ~x~0 := #t~ite34; [L751] 1 havoc #t~ite34; [L751] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L752] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] 1 ~x$w_buff0_used~0 := #t~ite35; [L752] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L753] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] 1 ~x$w_buff1_used~0 := #t~ite36; [L753] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L754] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L754] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L755] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L755] 1 havoc #t~ite38; [L758] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L776] -1 havoc main_#t~nondet41; [L778] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L780] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L782] -1 main_#t~ite42 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 ~x~0 := main_#t~ite43; [L782] -1 havoc main_#t~ite43; [L782] -1 havoc main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L783] -1 main_#t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] -1 ~x$w_buff0_used~0 := main_#t~ite44; [L783] -1 havoc main_#t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L784] -1 main_#t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] -1 ~x$w_buff1_used~0 := main_#t~ite45; [L784] -1 havoc main_#t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L785] -1 main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] -1 ~x$r_buff0_thd0~0 := main_#t~ite46; [L785] -1 havoc main_#t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L786] -1 main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] -1 ~x$r_buff1_thd0~0 := main_#t~ite47; [L786] -1 havoc main_#t~ite47; [L789] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 2 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L791] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L791] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1711~0!base=6, main_~#t1711~0!offset=0, main_~#t1712~0!base=5, main_~#t1712~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L773] FCALL -1 call ~#t1711~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FCALL -1 call write~int(0, ~#t1711~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L698-L725] 0 ~arg := #in~arg; [L701] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L702] 0 ~x$w_buff0~0 := 1; [L703] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L704] 0 ~x$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] -1 havoc #t~nondet40; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L706] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L707] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L708] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L709] 0 ~x$r_buff0_thd1~0 := 1; [L712] 0 ~y~0 := 1; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L715] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L715] 0 #t~ite4 := ~x$w_buff0~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L775] FCALL -1 call ~#t1712~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FCALL -1 call write~int(1, ~#t1712~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L726-L761] 1 ~arg := #in~arg; [L729] 1 ~y~0 := 2; [L732] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L735] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L735] 1 havoc #t~nondet10; [L736] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L736] 1 havoc #t~nondet11; [L737] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L738] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] COND TRUE 1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256) [L739] 1 #t~ite13 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] 1 ~x~0 := #t~ite13; [L739] 1 havoc #t~ite13; [L739] 1 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L740] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] 1 ~x$w_buff0~0 := #t~ite16; [L740] 1 havoc #t~ite16; [L740] 1 havoc #t~ite15; [L740] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L741] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] 1 ~x$w_buff1~0 := #t~ite19; [L741] 1 havoc #t~ite19; [L741] 1 havoc #t~ite17; [L741] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L742] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] 1 ~x$w_buff0_used~0 := #t~ite22; [L742] 1 havoc #t~ite20; [L742] 1 havoc #t~ite22; [L742] 1 havoc #t~ite21; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L743] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] 1 ~x$w_buff1_used~0 := #t~ite25; [L743] 1 havoc #t~ite25; [L743] 1 havoc #t~ite24; [L743] 1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L744] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L744] 1 havoc #t~ite26; [L744] 1 havoc #t~ite27; [L744] 1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L745] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L745] 1 havoc #t~ite30; [L745] 1 havoc #t~ite29; [L745] 1 havoc #t~ite31; [L746] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L747] COND TRUE 1 0 != ~x$flush_delayed~0 % 256 [L747] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L715] 0 ~x~0 := #t~ite4; [L715] 0 havoc #t~ite4; [L715] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L747] 1 ~x~0 := #t~ite32; [L747] 1 havoc #t~ite32; [L748] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L716] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] 0 ~x$w_buff0_used~0 := #t~ite5; [L716] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L717] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] 0 ~x$w_buff1_used~0 := #t~ite6; [L717] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L718] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L718] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L719] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L719] 0 havoc #t~ite8; [L722] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L751] 1 #t~ite33 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 ~x~0 := #t~ite34; [L751] 1 havoc #t~ite34; [L751] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L752] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] 1 ~x$w_buff0_used~0 := #t~ite35; [L752] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L753] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] 1 ~x$w_buff1_used~0 := #t~ite36; [L753] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L754] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L754] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L755] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L755] 1 havoc #t~ite38; [L758] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L776] -1 havoc #t~nondet41; [L778] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L780] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L782] -1 #t~ite42 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 #t~ite43 := #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 ~x~0 := #t~ite43; [L782] -1 havoc #t~ite43; [L782] -1 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L783] -1 #t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] -1 ~x$w_buff0_used~0 := #t~ite44; [L783] -1 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L784] -1 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] -1 ~x$w_buff1_used~0 := #t~ite45; [L784] -1 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L785] -1 #t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] -1 ~x$r_buff0_thd0~0 := #t~ite46; [L785] -1 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L786] -1 #t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] -1 ~x$r_buff1_thd0~0 := #t~ite47; [L786] -1 havoc #t~ite47; [L789] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 2 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L773] FCALL -1 call ~#t1711~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FCALL -1 call write~int(0, ~#t1711~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L698-L725] 0 ~arg := #in~arg; [L701] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L702] 0 ~x$w_buff0~0 := 1; [L703] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L704] 0 ~x$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L774] -1 havoc #t~nondet40; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L706] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L707] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L708] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L709] 0 ~x$r_buff0_thd1~0 := 1; [L712] 0 ~y~0 := 1; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L715] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L715] 0 #t~ite4 := ~x$w_buff0~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L775] FCALL -1 call ~#t1712~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FCALL -1 call write~int(1, ~#t1712~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L776] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L726-L761] 1 ~arg := #in~arg; [L729] 1 ~y~0 := 2; [L732] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L735] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L735] 1 havoc #t~nondet10; [L736] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L736] 1 havoc #t~nondet11; [L737] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L738] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] COND TRUE 1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256) [L739] 1 #t~ite13 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L739] 1 ~x~0 := #t~ite13; [L739] 1 havoc #t~ite13; [L739] 1 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L740] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L740] 1 ~x$w_buff0~0 := #t~ite16; [L740] 1 havoc #t~ite16; [L740] 1 havoc #t~ite15; [L740] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L741] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L741] 1 ~x$w_buff1~0 := #t~ite19; [L741] 1 havoc #t~ite19; [L741] 1 havoc #t~ite17; [L741] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L742] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L742] 1 ~x$w_buff0_used~0 := #t~ite22; [L742] 1 havoc #t~ite20; [L742] 1 havoc #t~ite22; [L742] 1 havoc #t~ite21; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L743] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L743] 1 ~x$w_buff1_used~0 := #t~ite25; [L743] 1 havoc #t~ite25; [L743] 1 havoc #t~ite24; [L743] 1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L744] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L744] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L744] 1 havoc #t~ite26; [L744] 1 havoc #t~ite27; [L744] 1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L745] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L745] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L745] 1 havoc #t~ite30; [L745] 1 havoc #t~ite29; [L745] 1 havoc #t~ite31; [L746] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L747] COND TRUE 1 0 != ~x$flush_delayed~0 % 256 [L747] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L715] 0 ~x~0 := #t~ite4; [L715] 0 havoc #t~ite4; [L715] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L747] 1 ~x~0 := #t~ite32; [L747] 1 havoc #t~ite32; [L748] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L716] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L716] 0 ~x$w_buff0_used~0 := #t~ite5; [L716] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L717] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L717] 0 ~x$w_buff1_used~0 := #t~ite6; [L717] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L718] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L718] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L718] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L719] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L719] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L719] 0 havoc #t~ite8; [L722] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L751] 1 #t~ite33 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L751] 1 ~x~0 := #t~ite34; [L751] 1 havoc #t~ite34; [L751] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L752] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L752] 1 ~x$w_buff0_used~0 := #t~ite35; [L752] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L753] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L753] 1 ~x$w_buff1_used~0 := #t~ite36; [L753] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L754] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L754] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L754] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L755] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L755] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L755] 1 havoc #t~ite38; [L758] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L776] -1 havoc #t~nondet41; [L778] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L780] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L782] -1 #t~ite42 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 #t~ite43 := #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L782] -1 ~x~0 := #t~ite43; [L782] -1 havoc #t~ite43; [L782] -1 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L783] -1 #t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L783] -1 ~x$w_buff0_used~0 := #t~ite44; [L783] -1 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L784] -1 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L784] -1 ~x$w_buff1_used~0 := #t~ite45; [L784] -1 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L785] -1 #t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L785] -1 ~x$r_buff0_thd0~0 := #t~ite46; [L785] -1 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L786] -1 #t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L786] -1 ~x$r_buff1_thd0~0 := #t~ite47; [L786] -1 havoc #t~ite47; [L789] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 2 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=2, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2] [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0] [L675] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L676] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0] [L677] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0] [L679] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L680] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0] [L681] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0] [L682] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L683] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L684] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L685] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L686] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L687] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L688] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L689] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L690] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L691] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L692] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L693] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L695] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L696] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L697] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L773] -1 pthread_t t1711; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L774] FCALL, FORK -1 pthread_create(&t1711, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L701] 0 x$w_buff1 = x$w_buff0 [L702] 0 x$w_buff0 = 1 [L703] 0 x$w_buff1_used = x$w_buff0_used [L704] 0 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0] [L706] 0 x$r_buff1_thd0 = x$r_buff0_thd0 [L707] 0 x$r_buff1_thd1 = x$r_buff0_thd1 [L708] 0 x$r_buff1_thd2 = x$r_buff0_thd2 [L709] 0 x$r_buff0_thd1 = (_Bool)1 [L712] 0 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L715] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L775] -1 pthread_t t1712; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L776] FCALL, FORK -1 pthread_create(&t1712, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L729] 1 y = 2 [L732] 1 __unbuffered_p1_EAX = y [L735] 1 weak$$choice0 = __VERIFIER_nondet_pointer() [L736] 1 weak$$choice2 = __VERIFIER_nondet_pointer() [L737] 1 x$flush_delayed = weak$$choice2 [L738] 1 x$mem_tmp = x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L739] EXPR 1 !x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1) VAL [!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L739] 1 x = !x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1) [L740] EXPR 1 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0))=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L740] 1 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)) [L741] EXPR 1 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L741] 1 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)) [L742] EXPR 1 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used))=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L742] 1 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used)) [L743] EXPR 1 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L743] 1 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L744] EXPR 1 weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L744] 1 x$r_buff0_thd2 = weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2)) [L745] EXPR 1 weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L745] 1 x$r_buff1_thd2 = weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L746] 1 __unbuffered_p1_EBX = x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L747] EXPR 1 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=1, x$flush_delayed ? x$mem_tmp : x=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L715] 0 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L747] 1 x = x$flush_delayed ? x$mem_tmp : x [L748] 1 x$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L716] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L716] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L717] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L717] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L718] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L718] 0 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L719] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L719] 0 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L722] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L751] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L751] EXPR 1 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=2] [L751] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x)=0, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=2] [L751] 1 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L752] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L752] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L753] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L753] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L754] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L754] 1 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L755] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L755] 1 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L758] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L778] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L782] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L782] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L782] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L782] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L783] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L783] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L784] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L784] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L785] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L785] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L786] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L786] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L789] -1 main$tmp_guard1 = !(y == 2 && __unbuffered_p1_EAX == 2 && __unbuffered_p1_EBX == 0) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] ----- [2018-11-23 14:29:05,386 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_574140b9-9c06-496f-8dad-f2fe678a2345/bin-2019/uautomizer/witness.graphml [2018-11-23 14:29:05,386 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 14:29:05,387 INFO L168 Benchmark]: Toolchain (without parser) took 27905.66 ms. Allocated memory was 1.0 GB in the beginning and 2.6 GB in the end (delta: 1.5 GB). Free memory was 956.6 MB in the beginning and 1.4 GB in the end (delta: -456.2 MB). Peak memory consumption was 1.1 GB. Max. memory is 11.5 GB. [2018-11-23 14:29:05,388 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 14:29:05,388 INFO L168 Benchmark]: CACSL2BoogieTranslator took 418.57 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 144.7 MB). Free memory was 956.6 MB in the beginning and 1.1 GB in the end (delta: -165.7 MB). Peak memory consumption was 35.5 MB. Max. memory is 11.5 GB. [2018-11-23 14:29:05,388 INFO L168 Benchmark]: Boogie Procedure Inliner took 34.13 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-23 14:29:05,393 INFO L168 Benchmark]: Boogie Preprocessor took 21.52 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 14:29:05,393 INFO L168 Benchmark]: RCFGBuilder took 540.00 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 52.6 MB). Peak memory consumption was 52.6 MB. Max. memory is 11.5 GB. [2018-11-23 14:29:05,393 INFO L168 Benchmark]: TraceAbstraction took 22299.81 ms. Allocated memory was 1.2 GB in the beginning and 2.6 GB in the end (delta: 1.4 GB). Free memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: -471.3 MB). Peak memory consumption was 924.4 MB. Max. memory is 11.5 GB. [2018-11-23 14:29:05,393 INFO L168 Benchmark]: Witness Printer took 4588.12 ms. Allocated memory is still 2.6 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 125.4 MB). Peak memory consumption was 125.4 MB. Max. memory is 11.5 GB. [2018-11-23 14:29:05,395 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 418.57 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 144.7 MB). Free memory was 956.6 MB in the beginning and 1.1 GB in the end (delta: -165.7 MB). Peak memory consumption was 35.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 34.13 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 21.52 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 540.00 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 52.6 MB). Peak memory consumption was 52.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 22299.81 ms. Allocated memory was 1.2 GB in the beginning and 2.6 GB in the end (delta: 1.4 GB). Free memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: -471.3 MB). Peak memory consumption was 924.4 MB. Max. memory is 11.5 GB. * Witness Printer took 4588.12 ms. Allocated memory is still 2.6 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 125.4 MB). Peak memory consumption was 125.4 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0] [L675] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L676] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0] [L677] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0] [L679] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L680] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0] [L681] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0] [L682] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L683] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L684] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L685] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L686] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L687] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L688] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L689] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L690] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L691] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L692] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L693] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L695] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L696] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L697] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L773] -1 pthread_t t1711; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L774] FCALL, FORK -1 pthread_create(&t1711, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L701] 0 x$w_buff1 = x$w_buff0 [L702] 0 x$w_buff0 = 1 [L703] 0 x$w_buff1_used = x$w_buff0_used [L704] 0 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0] [L706] 0 x$r_buff1_thd0 = x$r_buff0_thd0 [L707] 0 x$r_buff1_thd1 = x$r_buff0_thd1 [L708] 0 x$r_buff1_thd2 = x$r_buff0_thd2 [L709] 0 x$r_buff0_thd1 = (_Bool)1 [L712] 0 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L715] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L775] -1 pthread_t t1712; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L776] FCALL, FORK -1 pthread_create(&t1712, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L729] 1 y = 2 [L732] 1 __unbuffered_p1_EAX = y [L735] 1 weak$$choice0 = __VERIFIER_nondet_pointer() [L736] 1 weak$$choice2 = __VERIFIER_nondet_pointer() [L737] 1 x$flush_delayed = weak$$choice2 [L738] 1 x$mem_tmp = x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L739] EXPR 1 !x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1) VAL [!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L739] 1 x = !x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1) [L740] EXPR 1 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0))=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L740] 1 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)) [L741] EXPR 1 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L741] 1 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)) [L742] EXPR 1 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used))=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L742] 1 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used)) [L743] EXPR 1 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L743] 1 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L744] EXPR 1 weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L744] 1 x$r_buff0_thd2 = weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2)) [L745] EXPR 1 weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L745] 1 x$r_buff1_thd2 = weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L746] 1 __unbuffered_p1_EBX = x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L747] EXPR 1 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=1, x$flush_delayed ? x$mem_tmp : x=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L715] 0 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L747] 1 x = x$flush_delayed ? x$mem_tmp : x [L748] 1 x$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L716] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L716] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L717] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L717] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L718] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L718] 0 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L719] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L719] 0 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L722] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L751] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L751] EXPR 1 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=2] [L751] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x)=0, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=2] [L751] 1 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L752] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L752] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L753] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L753] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L754] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L754] 1 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L755] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L755] 1 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L758] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L778] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L782] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L782] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L782] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L782] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L783] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L783] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L784] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L784] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L785] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L785] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L786] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L786] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L789] -1 main$tmp_guard1 = !(y == 2 && __unbuffered_p1_EAX == 2 && __unbuffered_p1_EBX == 0) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=2, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 222 locations, 3 error locations. UNSAFE Result, 22.2s OverallTime, 36 OverallIterations, 1 TraceHistogramMax, 10.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 8978 SDtfs, 10198 SDslu, 21942 SDs, 0 SdLazy, 10392 SolverSat, 502 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 388 GetRequests, 89 SyntacticMatches, 43 SemanticMatches, 256 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 355 ImplicationChecksByTransitivity, 2.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=34806occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 4.9s AutomataMinimizationTime, 35 MinimizatonAttempts, 90832 StatesRemovedByMinimization, 34 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 2.2s InterpolantComputationTime, 2764 NumberOfCodeBlocks, 2764 NumberOfCodeBlocksAsserted, 36 NumberOfCheckSat, 2634 ConstructedInterpolants, 0 QuantifiedInterpolants, 626505 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 35 InterpolantComputations, 35 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...