./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe029_power.opt_false-unreach-call.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_69642bdf-4e67-44c1-b368-2141fba9f8c8/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_69642bdf-4e67-44c1-b368-2141fba9f8c8/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_69642bdf-4e67-44c1-b368-2141fba9f8c8/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_69642bdf-4e67-44c1-b368-2141fba9f8c8/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe029_power.opt_false-unreach-call.i -s /tmp/vcloud-vcloud-master/worker/working_dir_69642bdf-4e67-44c1-b368-2141fba9f8c8/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_69642bdf-4e67-44c1-b368-2141fba9f8c8/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 47114b7025e0370460384816fc34be8953a40ffc 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 03:48:56,879 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 03:48:56,880 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 03:48:56,888 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 03:48:56,888 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 03:48:56,888 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 03:48:56,889 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 03:48:56,890 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 03:48:56,891 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 03:48:56,891 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 03:48:56,892 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 03:48:56,892 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 03:48:56,892 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 03:48:56,893 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 03:48:56,894 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 03:48:56,894 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 03:48:56,895 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 03:48:56,896 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 03:48:56,897 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 03:48:56,898 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 03:48:56,899 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 03:48:56,899 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 03:48:56,901 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 03:48:56,901 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 03:48:56,901 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 03:48:56,902 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 03:48:56,902 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 03:48:56,903 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 03:48:56,903 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 03:48:56,904 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 03:48:56,904 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 03:48:56,904 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 03:48:56,904 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 03:48:56,904 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 03:48:56,905 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 03:48:56,905 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 03:48:56,905 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_69642bdf-4e67-44c1-b368-2141fba9f8c8/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-23 03:48:56,912 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 03:48:56,913 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 03:48:56,913 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 03:48:56,913 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 03:48:56,914 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 03:48:56,914 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 03:48:56,914 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 03:48:56,914 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 03:48:56,914 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 03:48:56,914 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 03:48:56,914 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 03:48:56,914 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 03:48:56,914 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 03:48:56,915 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 03:48:56,915 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 03:48:56,915 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 03:48:56,915 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 03:48:56,915 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 03:48:56,915 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 03:48:56,915 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 03:48:56,915 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 03:48:56,916 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 03:48:56,916 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 03:48:56,916 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 03:48:56,916 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 03:48:56,916 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 03:48:56,916 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 03:48:56,916 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 03:48:56,916 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 03:48:56,916 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 03:48:56,917 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_69642bdf-4e67-44c1-b368-2141fba9f8c8/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 47114b7025e0370460384816fc34be8953a40ffc [2018-11-23 03:48:56,940 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 03:48:56,949 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 03:48:56,951 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 03:48:56,952 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 03:48:56,953 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 03:48:56,953 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_69642bdf-4e67-44c1-b368-2141fba9f8c8/bin-2019/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe029_power.opt_false-unreach-call.i [2018-11-23 03:48:56,998 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_69642bdf-4e67-44c1-b368-2141fba9f8c8/bin-2019/uautomizer/data/d764c50fd/2cb969145b1548ee9a071f41bdd5a7b1/FLAGa860df445 [2018-11-23 03:48:57,340 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 03:48:57,340 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_69642bdf-4e67-44c1-b368-2141fba9f8c8/sv-benchmarks/c/pthread-wmm/safe029_power.opt_false-unreach-call.i [2018-11-23 03:48:57,348 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_69642bdf-4e67-44c1-b368-2141fba9f8c8/bin-2019/uautomizer/data/d764c50fd/2cb969145b1548ee9a071f41bdd5a7b1/FLAGa860df445 [2018-11-23 03:48:57,358 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_69642bdf-4e67-44c1-b368-2141fba9f8c8/bin-2019/uautomizer/data/d764c50fd/2cb969145b1548ee9a071f41bdd5a7b1 [2018-11-23 03:48:57,360 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 03:48:57,362 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 03:48:57,362 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 03:48:57,362 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 03:48:57,365 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 03:48:57,366 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 03:48:57" (1/1) ... [2018-11-23 03:48:57,368 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7befe0c1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:48:57, skipping insertion in model container [2018-11-23 03:48:57,368 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 03:48:57" (1/1) ... [2018-11-23 03:48:57,375 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 03:48:57,408 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 03:48:57,632 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 03:48:57,641 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 03:48:57,731 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 03:48:57,771 INFO L195 MainTranslator]: Completed translation [2018-11-23 03:48:57,772 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:48:57 WrapperNode [2018-11-23 03:48:57,772 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 03:48:57,773 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 03:48:57,773 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 03:48:57,773 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 03:48:57,780 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:48:57" (1/1) ... [2018-11-23 03:48:57,790 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:48:57" (1/1) ... [2018-11-23 03:48:57,807 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 03:48:57,807 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 03:48:57,807 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 03:48:57,808 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 03:48:57,813 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:48:57" (1/1) ... [2018-11-23 03:48:57,814 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:48:57" (1/1) ... [2018-11-23 03:48:57,816 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:48:57" (1/1) ... [2018-11-23 03:48:57,816 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:48:57" (1/1) ... [2018-11-23 03:48:57,821 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:48:57" (1/1) ... [2018-11-23 03:48:57,823 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:48:57" (1/1) ... [2018-11-23 03:48:57,825 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:48:57" (1/1) ... [2018-11-23 03:48:57,827 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 03:48:57,827 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 03:48:57,827 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 03:48:57,827 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 03:48:57,828 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:48:57" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_69642bdf-4e67-44c1-b368-2141fba9f8c8/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 03:48:57,864 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 03:48:57,865 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-23 03:48:57,865 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2018-11-23 03:48:57,865 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 03:48:57,865 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2018-11-23 03:48:57,865 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2018-11-23 03:48:57,865 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2018-11-23 03:48:57,865 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2018-11-23 03:48:57,865 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2018-11-23 03:48:57,865 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 03:48:57,865 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 03:48:57,866 WARN L198 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2018-11-23 03:48:58,325 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 03:48:58,325 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-11-23 03:48:58,325 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 03:48:58 BoogieIcfgContainer [2018-11-23 03:48:58,325 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 03:48:58,326 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 03:48:58,326 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 03:48:58,329 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 03:48:58,329 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 03:48:57" (1/3) ... [2018-11-23 03:48:58,330 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2baf6f95 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 03:48:58, skipping insertion in model container [2018-11-23 03:48:58,330 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:48:57" (2/3) ... [2018-11-23 03:48:58,330 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2baf6f95 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 03:48:58, skipping insertion in model container [2018-11-23 03:48:58,330 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 03:48:58" (3/3) ... [2018-11-23 03:48:58,331 INFO L112 eAbstractionObserver]: Analyzing ICFG safe029_power.opt_false-unreach-call.i [2018-11-23 03:48:58,356 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,356 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,356 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,356 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,357 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,357 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,357 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,357 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,357 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,358 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,358 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,358 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,358 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,358 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,358 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,359 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,359 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,359 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,359 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,359 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,359 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,359 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,360 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,360 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,360 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,360 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,360 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,360 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,360 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,361 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,361 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,361 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,361 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,361 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,361 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,362 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,362 WARN L317 ript$VariableManager]: TermVariabe Thread1_P1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,362 WARN L317 ript$VariableManager]: TermVariabe Thread1_P1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,362 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,362 WARN L317 ript$VariableManager]: TermVariabe Thread1_P1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,362 WARN L317 ript$VariableManager]: TermVariabe Thread1_P1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,362 WARN L317 ript$VariableManager]: TermVariabe Thread1_P1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,362 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,363 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,363 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,363 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,363 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,363 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,363 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,363 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,364 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,364 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,364 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,364 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,364 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,364 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,364 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,365 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,365 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,365 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,365 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,365 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,365 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,365 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,365 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,366 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,366 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet16.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,366 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet16.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,366 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,366 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,366 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet16.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,366 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet16.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:48:58,372 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2018-11-23 03:48:58,372 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 03:48:58,379 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2018-11-23 03:48:58,390 INFO L257 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2018-11-23 03:48:58,411 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 03:48:58,411 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 03:48:58,411 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 03:48:58,411 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 03:48:58,411 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 03:48:58,411 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 03:48:58,412 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 03:48:58,412 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 03:48:58,412 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 03:48:58,420 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 140places, 178 transitions [2018-11-23 03:48:59,547 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 25086 states. [2018-11-23 03:48:59,548 INFO L276 IsEmpty]: Start isEmpty. Operand 25086 states. [2018-11-23 03:48:59,556 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-11-23 03:48:59,556 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:48:59,556 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:48:59,558 INFO L423 AbstractCegarLoop]: === Iteration 1 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:48:59,563 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:48:59,563 INFO L82 PathProgramCache]: Analyzing trace with hash 1594278667, now seen corresponding path program 1 times [2018-11-23 03:48:59,565 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:48:59,565 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:48:59,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:48:59,600 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:48:59,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:48:59,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:48:59,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:48:59,737 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:48:59,737 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:48:59,740 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:48:59,752 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:48:59,752 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:48:59,754 INFO L87 Difference]: Start difference. First operand 25086 states. Second operand 4 states. [2018-11-23 03:49:00,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:00,334 INFO L93 Difference]: Finished difference Result 45386 states and 177624 transitions. [2018-11-23 03:49:00,334 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 03:49:00,335 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2018-11-23 03:49:00,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:00,540 INFO L225 Difference]: With dead ends: 45386 [2018-11-23 03:49:00,540 INFO L226 Difference]: Without dead ends: 40626 [2018-11-23 03:49:00,542 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:49:00,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40626 states. [2018-11-23 03:49:01,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40626 to 23660. [2018-11-23 03:49:01,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23660 states. [2018-11-23 03:49:01,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23660 states to 23660 states and 92541 transitions. [2018-11-23 03:49:01,459 INFO L78 Accepts]: Start accepts. Automaton has 23660 states and 92541 transitions. Word has length 35 [2018-11-23 03:49:01,459 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:01,459 INFO L480 AbstractCegarLoop]: Abstraction has 23660 states and 92541 transitions. [2018-11-23 03:49:01,459 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:49:01,459 INFO L276 IsEmpty]: Start isEmpty. Operand 23660 states and 92541 transitions. [2018-11-23 03:49:01,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-23 03:49:01,463 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:01,464 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:01,464 INFO L423 AbstractCegarLoop]: === Iteration 2 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:01,465 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:01,465 INFO L82 PathProgramCache]: Analyzing trace with hash 1049069648, now seen corresponding path program 1 times [2018-11-23 03:49:01,465 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:01,465 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:01,469 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:01,469 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:01,469 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:01,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:01,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:01,538 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:01,538 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:49:01,539 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:49:01,539 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:49:01,539 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:49:01,540 INFO L87 Difference]: Start difference. First operand 23660 states and 92541 transitions. Second operand 5 states. [2018-11-23 03:49:02,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:02,350 INFO L93 Difference]: Finished difference Result 64828 states and 241367 transitions. [2018-11-23 03:49:02,351 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 03:49:02,351 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 42 [2018-11-23 03:49:02,351 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:02,588 INFO L225 Difference]: With dead ends: 64828 [2018-11-23 03:49:02,588 INFO L226 Difference]: Without dead ends: 64668 [2018-11-23 03:49:02,589 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:49:02,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64668 states. [2018-11-23 03:49:03,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64668 to 37140. [2018-11-23 03:49:03,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37140 states. [2018-11-23 03:49:03,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37140 states to 37140 states and 138282 transitions. [2018-11-23 03:49:03,539 INFO L78 Accepts]: Start accepts. Automaton has 37140 states and 138282 transitions. Word has length 42 [2018-11-23 03:49:03,540 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:03,540 INFO L480 AbstractCegarLoop]: Abstraction has 37140 states and 138282 transitions. [2018-11-23 03:49:03,540 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:49:03,540 INFO L276 IsEmpty]: Start isEmpty. Operand 37140 states and 138282 transitions. [2018-11-23 03:49:03,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-11-23 03:49:03,543 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:03,543 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:03,543 INFO L423 AbstractCegarLoop]: === Iteration 3 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:03,543 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:03,543 INFO L82 PathProgramCache]: Analyzing trace with hash -888651829, now seen corresponding path program 1 times [2018-11-23 03:49:03,543 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:03,543 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:03,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:03,546 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:03,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:03,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:03,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:03,609 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:03,609 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:49:03,609 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:49:03,609 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:49:03,609 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:49:03,610 INFO L87 Difference]: Start difference. First operand 37140 states and 138282 transitions. Second operand 4 states. [2018-11-23 03:49:03,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:03,678 INFO L93 Difference]: Finished difference Result 12362 states and 41175 transitions. [2018-11-23 03:49:03,678 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 03:49:03,678 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 43 [2018-11-23 03:49:03,678 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:03,693 INFO L225 Difference]: With dead ends: 12362 [2018-11-23 03:49:03,693 INFO L226 Difference]: Without dead ends: 11841 [2018-11-23 03:49:03,693 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:49:03,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11841 states. [2018-11-23 03:49:03,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11841 to 11841. [2018-11-23 03:49:03,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11841 states. [2018-11-23 03:49:03,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11841 states to 11841 states and 39620 transitions. [2018-11-23 03:49:03,834 INFO L78 Accepts]: Start accepts. Automaton has 11841 states and 39620 transitions. Word has length 43 [2018-11-23 03:49:03,834 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:03,834 INFO L480 AbstractCegarLoop]: Abstraction has 11841 states and 39620 transitions. [2018-11-23 03:49:03,834 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:49:03,834 INFO L276 IsEmpty]: Start isEmpty. Operand 11841 states and 39620 transitions. [2018-11-23 03:49:03,837 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-23 03:49:03,837 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:03,837 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:03,837 INFO L423 AbstractCegarLoop]: === Iteration 4 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:03,838 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:03,838 INFO L82 PathProgramCache]: Analyzing trace with hash -1845292501, now seen corresponding path program 1 times [2018-11-23 03:49:03,838 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:03,838 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:03,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:03,840 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:03,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:03,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:04,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:04,084 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:04,084 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:49:04,084 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:49:04,084 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:49:04,085 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:49:04,085 INFO L87 Difference]: Start difference. First operand 11841 states and 39620 transitions. Second operand 4 states. [2018-11-23 03:49:04,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:04,256 INFO L93 Difference]: Finished difference Result 17017 states and 55691 transitions. [2018-11-23 03:49:04,257 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 03:49:04,257 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 56 [2018-11-23 03:49:04,257 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:04,286 INFO L225 Difference]: With dead ends: 17017 [2018-11-23 03:49:04,286 INFO L226 Difference]: Without dead ends: 17017 [2018-11-23 03:49:04,286 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:49:04,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17017 states. [2018-11-23 03:49:04,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17017 to 12877. [2018-11-23 03:49:04,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12877 states. [2018-11-23 03:49:04,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12877 states to 12877 states and 42718 transitions. [2018-11-23 03:49:04,448 INFO L78 Accepts]: Start accepts. Automaton has 12877 states and 42718 transitions. Word has length 56 [2018-11-23 03:49:04,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:04,448 INFO L480 AbstractCegarLoop]: Abstraction has 12877 states and 42718 transitions. [2018-11-23 03:49:04,448 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:49:04,448 INFO L276 IsEmpty]: Start isEmpty. Operand 12877 states and 42718 transitions. [2018-11-23 03:49:04,452 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-23 03:49:04,453 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:04,453 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:04,453 INFO L423 AbstractCegarLoop]: === Iteration 5 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:04,453 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:04,453 INFO L82 PathProgramCache]: Analyzing trace with hash -169488919, now seen corresponding path program 1 times [2018-11-23 03:49:04,453 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:04,453 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:04,455 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:04,455 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:04,455 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:04,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:04,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:04,531 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:04,531 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:49:04,531 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:49:04,531 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:49:04,531 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:49:04,532 INFO L87 Difference]: Start difference. First operand 12877 states and 42718 transitions. Second operand 6 states. [2018-11-23 03:49:04,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:04,869 INFO L93 Difference]: Finished difference Result 18597 states and 60828 transitions. [2018-11-23 03:49:04,869 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 03:49:04,869 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 56 [2018-11-23 03:49:04,869 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:04,891 INFO L225 Difference]: With dead ends: 18597 [2018-11-23 03:49:04,892 INFO L226 Difference]: Without dead ends: 18565 [2018-11-23 03:49:04,892 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=52, Invalid=130, Unknown=0, NotChecked=0, Total=182 [2018-11-23 03:49:04,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18565 states. [2018-11-23 03:49:05,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18565 to 14409. [2018-11-23 03:49:05,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14409 states. [2018-11-23 03:49:05,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14409 states to 14409 states and 47547 transitions. [2018-11-23 03:49:05,080 INFO L78 Accepts]: Start accepts. Automaton has 14409 states and 47547 transitions. Word has length 56 [2018-11-23 03:49:05,081 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:05,081 INFO L480 AbstractCegarLoop]: Abstraction has 14409 states and 47547 transitions. [2018-11-23 03:49:05,081 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:49:05,081 INFO L276 IsEmpty]: Start isEmpty. Operand 14409 states and 47547 transitions. [2018-11-23 03:49:05,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-23 03:49:05,093 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:05,093 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:05,093 INFO L423 AbstractCegarLoop]: === Iteration 6 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:05,093 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:05,093 INFO L82 PathProgramCache]: Analyzing trace with hash 860313174, now seen corresponding path program 1 times [2018-11-23 03:49:05,093 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:05,093 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:05,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:05,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:05,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:05,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:05,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:05,189 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:05,189 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 03:49:05,189 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 03:49:05,189 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 03:49:05,189 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:49:05,190 INFO L87 Difference]: Start difference. First operand 14409 states and 47547 transitions. Second operand 7 states. [2018-11-23 03:49:06,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:06,141 INFO L93 Difference]: Finished difference Result 49866 states and 161886 transitions. [2018-11-23 03:49:06,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 03:49:06,142 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 70 [2018-11-23 03:49:06,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:06,309 INFO L225 Difference]: With dead ends: 49866 [2018-11-23 03:49:06,310 INFO L226 Difference]: Without dead ends: 49594 [2018-11-23 03:49:06,310 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=83, Unknown=0, NotChecked=0, Total=132 [2018-11-23 03:49:06,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49594 states. [2018-11-23 03:49:06,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49594 to 22262. [2018-11-23 03:49:06,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22262 states. [2018-11-23 03:49:06,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22262 states to 22262 states and 72740 transitions. [2018-11-23 03:49:06,669 INFO L78 Accepts]: Start accepts. Automaton has 22262 states and 72740 transitions. Word has length 70 [2018-11-23 03:49:06,669 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:06,669 INFO L480 AbstractCegarLoop]: Abstraction has 22262 states and 72740 transitions. [2018-11-23 03:49:06,669 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 03:49:06,669 INFO L276 IsEmpty]: Start isEmpty. Operand 22262 states and 72740 transitions. [2018-11-23 03:49:06,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-23 03:49:06,684 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:06,684 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:06,684 INFO L423 AbstractCegarLoop]: === Iteration 7 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:06,684 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:06,685 INFO L82 PathProgramCache]: Analyzing trace with hash -2081344425, now seen corresponding path program 1 times [2018-11-23 03:49:06,685 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:06,685 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:06,686 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:06,686 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:06,686 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:06,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:06,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:06,749 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:06,749 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:49:06,749 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:49:06,749 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:49:06,749 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:49:06,749 INFO L87 Difference]: Start difference. First operand 22262 states and 72740 transitions. Second operand 5 states. [2018-11-23 03:49:06,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:06,780 INFO L93 Difference]: Finished difference Result 4734 states and 12518 transitions. [2018-11-23 03:49:06,781 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 03:49:06,781 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 70 [2018-11-23 03:49:06,781 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:06,784 INFO L225 Difference]: With dead ends: 4734 [2018-11-23 03:49:06,784 INFO L226 Difference]: Without dead ends: 3910 [2018-11-23 03:49:06,785 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:49:06,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3910 states. [2018-11-23 03:49:06,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3910 to 3410. [2018-11-23 03:49:06,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3410 states. [2018-11-23 03:49:06,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3410 states to 3410 states and 9066 transitions. [2018-11-23 03:49:06,814 INFO L78 Accepts]: Start accepts. Automaton has 3410 states and 9066 transitions. Word has length 70 [2018-11-23 03:49:06,814 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:06,814 INFO L480 AbstractCegarLoop]: Abstraction has 3410 states and 9066 transitions. [2018-11-23 03:49:06,814 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:49:06,814 INFO L276 IsEmpty]: Start isEmpty. Operand 3410 states and 9066 transitions. [2018-11-23 03:49:06,817 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-11-23 03:49:06,817 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:06,818 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:06,818 INFO L423 AbstractCegarLoop]: === Iteration 8 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:06,818 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:06,818 INFO L82 PathProgramCache]: Analyzing trace with hash 583358504, now seen corresponding path program 1 times [2018-11-23 03:49:06,818 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:06,818 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:06,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:06,820 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:06,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:06,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:06,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:06,859 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:06,859 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 03:49:06,859 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 03:49:06,860 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 03:49:06,860 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 03:49:06,860 INFO L87 Difference]: Start difference. First operand 3410 states and 9066 transitions. Second operand 3 states. [2018-11-23 03:49:06,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:06,947 INFO L93 Difference]: Finished difference Result 3508 states and 9283 transitions. [2018-11-23 03:49:06,947 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 03:49:06,947 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 89 [2018-11-23 03:49:06,947 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:06,950 INFO L225 Difference]: With dead ends: 3508 [2018-11-23 03:49:06,950 INFO L226 Difference]: Without dead ends: 3508 [2018-11-23 03:49:06,950 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 03:49:06,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3508 states. [2018-11-23 03:49:06,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3508 to 3448. [2018-11-23 03:49:06,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3448 states. [2018-11-23 03:49:06,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3448 states to 3448 states and 9152 transitions. [2018-11-23 03:49:06,974 INFO L78 Accepts]: Start accepts. Automaton has 3448 states and 9152 transitions. Word has length 89 [2018-11-23 03:49:06,974 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:06,974 INFO L480 AbstractCegarLoop]: Abstraction has 3448 states and 9152 transitions. [2018-11-23 03:49:06,975 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 03:49:06,975 INFO L276 IsEmpty]: Start isEmpty. Operand 3448 states and 9152 transitions. [2018-11-23 03:49:06,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-11-23 03:49:06,977 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:06,977 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:06,978 INFO L423 AbstractCegarLoop]: === Iteration 9 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:06,978 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:06,978 INFO L82 PathProgramCache]: Analyzing trace with hash -1719572279, now seen corresponding path program 1 times [2018-11-23 03:49:06,978 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:06,978 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:06,979 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:06,979 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:06,979 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:06,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:07,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:07,039 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:07,039 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:49:07,039 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:49:07,039 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:49:07,039 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:49:07,039 INFO L87 Difference]: Start difference. First operand 3448 states and 9152 transitions. Second operand 5 states. [2018-11-23 03:49:07,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:07,168 INFO L93 Difference]: Finished difference Result 4211 states and 10984 transitions. [2018-11-23 03:49:07,168 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 03:49:07,168 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 89 [2018-11-23 03:49:07,168 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:07,171 INFO L225 Difference]: With dead ends: 4211 [2018-11-23 03:49:07,172 INFO L226 Difference]: Without dead ends: 4211 [2018-11-23 03:49:07,172 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:49:07,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4211 states. [2018-11-23 03:49:07,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4211 to 4119. [2018-11-23 03:49:07,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4119 states. [2018-11-23 03:49:07,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4119 states to 4119 states and 10768 transitions. [2018-11-23 03:49:07,205 INFO L78 Accepts]: Start accepts. Automaton has 4119 states and 10768 transitions. Word has length 89 [2018-11-23 03:49:07,205 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:07,205 INFO L480 AbstractCegarLoop]: Abstraction has 4119 states and 10768 transitions. [2018-11-23 03:49:07,205 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:49:07,205 INFO L276 IsEmpty]: Start isEmpty. Operand 4119 states and 10768 transitions. [2018-11-23 03:49:07,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-11-23 03:49:07,209 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:07,209 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:07,209 INFO L423 AbstractCegarLoop]: === Iteration 10 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:07,210 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:07,210 INFO L82 PathProgramCache]: Analyzing trace with hash -1727331638, now seen corresponding path program 2 times [2018-11-23 03:49:07,210 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:07,210 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:07,211 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:07,211 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:07,211 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:07,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:07,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:07,255 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:07,255 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:49:07,255 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:49:07,255 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:49:07,256 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:49:07,256 INFO L87 Difference]: Start difference. First operand 4119 states and 10768 transitions. Second operand 4 states. [2018-11-23 03:49:07,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:07,400 INFO L93 Difference]: Finished difference Result 5581 states and 14678 transitions. [2018-11-23 03:49:07,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 03:49:07,400 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 89 [2018-11-23 03:49:07,401 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:07,405 INFO L225 Difference]: With dead ends: 5581 [2018-11-23 03:49:07,405 INFO L226 Difference]: Without dead ends: 5581 [2018-11-23 03:49:07,405 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:49:07,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5581 states. [2018-11-23 03:49:07,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5581 to 4161. [2018-11-23 03:49:07,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4161 states. [2018-11-23 03:49:07,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4161 states to 4161 states and 10862 transitions. [2018-11-23 03:49:07,443 INFO L78 Accepts]: Start accepts. Automaton has 4161 states and 10862 transitions. Word has length 89 [2018-11-23 03:49:07,444 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:07,444 INFO L480 AbstractCegarLoop]: Abstraction has 4161 states and 10862 transitions. [2018-11-23 03:49:07,444 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:49:07,444 INFO L276 IsEmpty]: Start isEmpty. Operand 4161 states and 10862 transitions. [2018-11-23 03:49:07,447 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-11-23 03:49:07,447 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:07,447 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:07,447 INFO L423 AbstractCegarLoop]: === Iteration 11 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:07,447 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:07,447 INFO L82 PathProgramCache]: Analyzing trace with hash 1540346686, now seen corresponding path program 1 times [2018-11-23 03:49:07,447 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:07,447 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:07,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:07,449 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 03:49:07,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:07,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:07,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:07,480 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:07,480 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:49:07,480 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:49:07,480 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:49:07,481 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:49:07,481 INFO L87 Difference]: Start difference. First operand 4161 states and 10862 transitions. Second operand 4 states. [2018-11-23 03:49:07,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:07,569 INFO L93 Difference]: Finished difference Result 7678 states and 20193 transitions. [2018-11-23 03:49:07,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 03:49:07,569 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 91 [2018-11-23 03:49:07,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:07,575 INFO L225 Difference]: With dead ends: 7678 [2018-11-23 03:49:07,575 INFO L226 Difference]: Without dead ends: 7678 [2018-11-23 03:49:07,575 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:49:07,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7678 states. [2018-11-23 03:49:07,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7678 to 4107. [2018-11-23 03:49:07,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4107 states. [2018-11-23 03:49:07,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4107 states to 4107 states and 10647 transitions. [2018-11-23 03:49:07,616 INFO L78 Accepts]: Start accepts. Automaton has 4107 states and 10647 transitions. Word has length 91 [2018-11-23 03:49:07,616 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:07,617 INFO L480 AbstractCegarLoop]: Abstraction has 4107 states and 10647 transitions. [2018-11-23 03:49:07,617 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:49:07,617 INFO L276 IsEmpty]: Start isEmpty. Operand 4107 states and 10647 transitions. [2018-11-23 03:49:07,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-11-23 03:49:07,620 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:07,620 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:07,620 INFO L423 AbstractCegarLoop]: === Iteration 12 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:07,620 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:07,620 INFO L82 PathProgramCache]: Analyzing trace with hash -162033363, now seen corresponding path program 1 times [2018-11-23 03:49:07,621 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:07,621 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:07,622 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:07,622 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:07,622 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:07,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:07,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:07,701 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:07,701 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:49:07,702 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:49:07,702 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:49:07,702 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:49:07,702 INFO L87 Difference]: Start difference. First operand 4107 states and 10647 transitions. Second operand 6 states. [2018-11-23 03:49:07,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:07,829 INFO L93 Difference]: Finished difference Result 4519 states and 11603 transitions. [2018-11-23 03:49:07,830 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 03:49:07,830 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 91 [2018-11-23 03:49:07,830 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:07,833 INFO L225 Difference]: With dead ends: 4519 [2018-11-23 03:49:07,833 INFO L226 Difference]: Without dead ends: 4519 [2018-11-23 03:49:07,834 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:49:07,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4519 states. [2018-11-23 03:49:07,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4519 to 4176. [2018-11-23 03:49:07,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4176 states. [2018-11-23 03:49:07,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4176 states to 4176 states and 10816 transitions. [2018-11-23 03:49:07,885 INFO L78 Accepts]: Start accepts. Automaton has 4176 states and 10816 transitions. Word has length 91 [2018-11-23 03:49:07,885 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:07,885 INFO L480 AbstractCegarLoop]: Abstraction has 4176 states and 10816 transitions. [2018-11-23 03:49:07,885 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:49:07,885 INFO L276 IsEmpty]: Start isEmpty. Operand 4176 states and 10816 transitions. [2018-11-23 03:49:07,888 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-11-23 03:49:07,888 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:07,888 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:07,888 INFO L423 AbstractCegarLoop]: === Iteration 13 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:07,888 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:07,888 INFO L82 PathProgramCache]: Analyzing trace with hash 807547660, now seen corresponding path program 1 times [2018-11-23 03:49:07,889 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:07,889 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:07,890 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:07,890 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:07,890 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:07,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:07,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:07,978 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:07,978 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:49:07,978 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:49:07,978 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:49:07,978 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:49:07,979 INFO L87 Difference]: Start difference. First operand 4176 states and 10816 transitions. Second operand 6 states. [2018-11-23 03:49:08,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:08,142 INFO L93 Difference]: Finished difference Result 6055 states and 15454 transitions. [2018-11-23 03:49:08,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:49:08,142 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 91 [2018-11-23 03:49:08,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:08,148 INFO L225 Difference]: With dead ends: 6055 [2018-11-23 03:49:08,148 INFO L226 Difference]: Without dead ends: 6023 [2018-11-23 03:49:08,148 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:49:08,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6023 states. [2018-11-23 03:49:08,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6023 to 4800. [2018-11-23 03:49:08,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4800 states. [2018-11-23 03:49:08,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4800 states to 4800 states and 12362 transitions. [2018-11-23 03:49:08,204 INFO L78 Accepts]: Start accepts. Automaton has 4800 states and 12362 transitions. Word has length 91 [2018-11-23 03:49:08,204 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:08,204 INFO L480 AbstractCegarLoop]: Abstraction has 4800 states and 12362 transitions. [2018-11-23 03:49:08,204 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:49:08,204 INFO L276 IsEmpty]: Start isEmpty. Operand 4800 states and 12362 transitions. [2018-11-23 03:49:08,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-11-23 03:49:08,208 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:08,208 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:08,209 INFO L423 AbstractCegarLoop]: === Iteration 14 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:08,209 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:08,209 INFO L82 PathProgramCache]: Analyzing trace with hash 1769161677, now seen corresponding path program 1 times [2018-11-23 03:49:08,209 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:08,209 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:08,210 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:08,210 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:08,210 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:08,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:08,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:08,322 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:08,322 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 03:49:08,322 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 03:49:08,322 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 03:49:08,322 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:49:08,323 INFO L87 Difference]: Start difference. First operand 4800 states and 12362 transitions. Second operand 7 states. [2018-11-23 03:49:08,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:08,679 INFO L93 Difference]: Finished difference Result 9725 states and 25304 transitions. [2018-11-23 03:49:08,679 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 03:49:08,680 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 91 [2018-11-23 03:49:08,680 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:08,690 INFO L225 Difference]: With dead ends: 9725 [2018-11-23 03:49:08,690 INFO L226 Difference]: Without dead ends: 9725 [2018-11-23 03:49:08,690 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=111, Unknown=0, NotChecked=0, Total=156 [2018-11-23 03:49:08,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9725 states. [2018-11-23 03:49:08,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9725 to 5424. [2018-11-23 03:49:08,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5424 states. [2018-11-23 03:49:08,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5424 states to 5424 states and 13996 transitions. [2018-11-23 03:49:08,757 INFO L78 Accepts]: Start accepts. Automaton has 5424 states and 13996 transitions. Word has length 91 [2018-11-23 03:49:08,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:08,757 INFO L480 AbstractCegarLoop]: Abstraction has 5424 states and 13996 transitions. [2018-11-23 03:49:08,757 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 03:49:08,757 INFO L276 IsEmpty]: Start isEmpty. Operand 5424 states and 13996 transitions. [2018-11-23 03:49:08,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-11-23 03:49:08,761 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:08,761 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:08,762 INFO L423 AbstractCegarLoop]: === Iteration 15 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:08,762 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:08,762 INFO L82 PathProgramCache]: Analyzing trace with hash -1281041138, now seen corresponding path program 1 times [2018-11-23 03:49:08,762 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:08,762 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:08,763 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:08,763 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:08,763 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:08,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:08,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:08,909 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:08,910 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 03:49:08,910 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 03:49:08,910 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 03:49:08,910 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:49:08,910 INFO L87 Difference]: Start difference. First operand 5424 states and 13996 transitions. Second operand 7 states. [2018-11-23 03:49:09,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:09,245 INFO L93 Difference]: Finished difference Result 5117 states and 13127 transitions. [2018-11-23 03:49:09,245 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 03:49:09,246 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 91 [2018-11-23 03:49:09,246 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:09,251 INFO L225 Difference]: With dead ends: 5117 [2018-11-23 03:49:09,251 INFO L226 Difference]: Without dead ends: 5117 [2018-11-23 03:49:09,251 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=31, Invalid=59, Unknown=0, NotChecked=0, Total=90 [2018-11-23 03:49:09,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5117 states. [2018-11-23 03:49:09,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5117 to 4981. [2018-11-23 03:49:09,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4981 states. [2018-11-23 03:49:09,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4981 states to 4981 states and 12823 transitions. [2018-11-23 03:49:09,307 INFO L78 Accepts]: Start accepts. Automaton has 4981 states and 12823 transitions. Word has length 91 [2018-11-23 03:49:09,308 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:09,308 INFO L480 AbstractCegarLoop]: Abstraction has 4981 states and 12823 transitions. [2018-11-23 03:49:09,308 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 03:49:09,308 INFO L276 IsEmpty]: Start isEmpty. Operand 4981 states and 12823 transitions. [2018-11-23 03:49:09,313 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-11-23 03:49:09,313 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:09,313 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:09,313 INFO L423 AbstractCegarLoop]: === Iteration 16 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:09,314 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:09,314 INFO L82 PathProgramCache]: Analyzing trace with hash -1672445698, now seen corresponding path program 1 times [2018-11-23 03:49:09,314 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:09,314 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:09,315 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:09,315 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:09,315 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:09,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:09,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:09,401 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:09,401 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 03:49:09,401 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 03:49:09,401 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 03:49:09,401 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:49:09,401 INFO L87 Difference]: Start difference. First operand 4981 states and 12823 transitions. Second operand 7 states. [2018-11-23 03:49:09,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:09,613 INFO L93 Difference]: Finished difference Result 5441 states and 13921 transitions. [2018-11-23 03:49:09,613 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:49:09,613 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 91 [2018-11-23 03:49:09,614 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:09,617 INFO L225 Difference]: With dead ends: 5441 [2018-11-23 03:49:09,618 INFO L226 Difference]: Without dead ends: 5441 [2018-11-23 03:49:09,618 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:49:09,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5441 states. [2018-11-23 03:49:09,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5441 to 5022. [2018-11-23 03:49:09,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5022 states. [2018-11-23 03:49:09,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5022 states to 5022 states and 12889 transitions. [2018-11-23 03:49:09,656 INFO L78 Accepts]: Start accepts. Automaton has 5022 states and 12889 transitions. Word has length 91 [2018-11-23 03:49:09,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:09,657 INFO L480 AbstractCegarLoop]: Abstraction has 5022 states and 12889 transitions. [2018-11-23 03:49:09,657 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 03:49:09,657 INFO L276 IsEmpty]: Start isEmpty. Operand 5022 states and 12889 transitions. [2018-11-23 03:49:09,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-11-23 03:49:09,661 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:09,661 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:09,661 INFO L423 AbstractCegarLoop]: === Iteration 17 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:09,661 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:09,661 INFO L82 PathProgramCache]: Analyzing trace with hash 1439174301, now seen corresponding path program 1 times [2018-11-23 03:49:09,662 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:09,662 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:09,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:09,663 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:09,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:09,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:09,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:09,729 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:09,729 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:49:09,729 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:49:09,729 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:49:09,729 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:49:09,729 INFO L87 Difference]: Start difference. First operand 5022 states and 12889 transitions. Second operand 5 states. [2018-11-23 03:49:09,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:09,830 INFO L93 Difference]: Finished difference Result 4541 states and 11655 transitions. [2018-11-23 03:49:09,830 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 03:49:09,830 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 91 [2018-11-23 03:49:09,830 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:09,835 INFO L225 Difference]: With dead ends: 4541 [2018-11-23 03:49:09,835 INFO L226 Difference]: Without dead ends: 4541 [2018-11-23 03:49:09,835 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:49:09,841 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4541 states. [2018-11-23 03:49:09,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4541 to 4491. [2018-11-23 03:49:09,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4491 states. [2018-11-23 03:49:09,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4491 states to 4491 states and 11554 transitions. [2018-11-23 03:49:09,882 INFO L78 Accepts]: Start accepts. Automaton has 4491 states and 11554 transitions. Word has length 91 [2018-11-23 03:49:09,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:09,882 INFO L480 AbstractCegarLoop]: Abstraction has 4491 states and 11554 transitions. [2018-11-23 03:49:09,882 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:49:09,882 INFO L276 IsEmpty]: Start isEmpty. Operand 4491 states and 11554 transitions. [2018-11-23 03:49:09,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-11-23 03:49:09,887 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:09,887 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:09,887 INFO L423 AbstractCegarLoop]: === Iteration 18 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:09,887 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:09,887 INFO L82 PathProgramCache]: Analyzing trace with hash -347029090, now seen corresponding path program 1 times [2018-11-23 03:49:09,888 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:09,888 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:09,889 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:09,889 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:09,889 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:09,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:09,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:09,960 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:09,960 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:49:09,961 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:49:09,961 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:49:09,961 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:49:09,961 INFO L87 Difference]: Start difference. First operand 4491 states and 11554 transitions. Second operand 6 states. [2018-11-23 03:49:10,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:10,034 INFO L93 Difference]: Finished difference Result 4075 states and 10146 transitions. [2018-11-23 03:49:10,034 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 03:49:10,034 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 91 [2018-11-23 03:49:10,034 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:10,037 INFO L225 Difference]: With dead ends: 4075 [2018-11-23 03:49:10,037 INFO L226 Difference]: Without dead ends: 4075 [2018-11-23 03:49:10,037 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:49:10,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4075 states. [2018-11-23 03:49:10,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4075 to 2421. [2018-11-23 03:49:10,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2421 states. [2018-11-23 03:49:10,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2421 states to 2421 states and 6211 transitions. [2018-11-23 03:49:10,059 INFO L78 Accepts]: Start accepts. Automaton has 2421 states and 6211 transitions. Word has length 91 [2018-11-23 03:49:10,059 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:10,059 INFO L480 AbstractCegarLoop]: Abstraction has 2421 states and 6211 transitions. [2018-11-23 03:49:10,059 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:49:10,059 INFO L276 IsEmpty]: Start isEmpty. Operand 2421 states and 6211 transitions. [2018-11-23 03:49:10,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 03:49:10,061 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:10,061 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:10,061 INFO L423 AbstractCegarLoop]: === Iteration 19 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:10,061 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:10,061 INFO L82 PathProgramCache]: Analyzing trace with hash -626984130, now seen corresponding path program 1 times [2018-11-23 03:49:10,061 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:10,061 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:10,062 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:10,062 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:10,062 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:10,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:10,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:10,133 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:10,133 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 03:49:10,135 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 03:49:10,135 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 03:49:10,135 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:49:10,135 INFO L87 Difference]: Start difference. First operand 2421 states and 6211 transitions. Second operand 7 states. [2018-11-23 03:49:10,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:10,478 INFO L93 Difference]: Finished difference Result 3893 states and 9716 transitions. [2018-11-23 03:49:10,478 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-23 03:49:10,478 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 93 [2018-11-23 03:49:10,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:10,481 INFO L225 Difference]: With dead ends: 3893 [2018-11-23 03:49:10,481 INFO L226 Difference]: Without dead ends: 3861 [2018-11-23 03:49:10,482 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2018-11-23 03:49:10,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3861 states. [2018-11-23 03:49:10,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3861 to 3073. [2018-11-23 03:49:10,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3073 states. [2018-11-23 03:49:10,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3073 states to 3073 states and 7791 transitions. [2018-11-23 03:49:10,507 INFO L78 Accepts]: Start accepts. Automaton has 3073 states and 7791 transitions. Word has length 93 [2018-11-23 03:49:10,507 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:10,507 INFO L480 AbstractCegarLoop]: Abstraction has 3073 states and 7791 transitions. [2018-11-23 03:49:10,507 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 03:49:10,508 INFO L276 IsEmpty]: Start isEmpty. Operand 3073 states and 7791 transitions. [2018-11-23 03:49:10,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 03:49:10,510 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:10,510 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:10,510 INFO L423 AbstractCegarLoop]: === Iteration 20 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:10,510 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:10,511 INFO L82 PathProgramCache]: Analyzing trace with hash 617780351, now seen corresponding path program 1 times [2018-11-23 03:49:10,511 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:10,511 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:10,512 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:10,512 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:10,512 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:10,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:10,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:10,578 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:10,578 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:49:10,578 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:49:10,578 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:49:10,578 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:49:10,578 INFO L87 Difference]: Start difference. First operand 3073 states and 7791 transitions. Second operand 6 states. [2018-11-23 03:49:10,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:10,686 INFO L93 Difference]: Finished difference Result 3123 states and 7833 transitions. [2018-11-23 03:49:10,687 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 03:49:10,687 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 93 [2018-11-23 03:49:10,687 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:10,690 INFO L225 Difference]: With dead ends: 3123 [2018-11-23 03:49:10,690 INFO L226 Difference]: Without dead ends: 3123 [2018-11-23 03:49:10,690 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-11-23 03:49:10,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3123 states. [2018-11-23 03:49:10,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3123 to 3043. [2018-11-23 03:49:10,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3043 states. [2018-11-23 03:49:10,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3043 states to 3043 states and 7679 transitions. [2018-11-23 03:49:10,721 INFO L78 Accepts]: Start accepts. Automaton has 3043 states and 7679 transitions. Word has length 93 [2018-11-23 03:49:10,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:10,721 INFO L480 AbstractCegarLoop]: Abstraction has 3043 states and 7679 transitions. [2018-11-23 03:49:10,721 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:49:10,721 INFO L276 IsEmpty]: Start isEmpty. Operand 3043 states and 7679 transitions. [2018-11-23 03:49:10,723 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 03:49:10,724 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:10,724 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:10,724 INFO L423 AbstractCegarLoop]: === Iteration 21 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:10,724 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:10,724 INFO L82 PathProgramCache]: Analyzing trace with hash -297218369, now seen corresponding path program 1 times [2018-11-23 03:49:10,724 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:10,725 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:10,725 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:10,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:10,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:10,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:10,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:10,788 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:10,789 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:49:10,789 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:49:10,789 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:49:10,789 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:49:10,789 INFO L87 Difference]: Start difference. First operand 3043 states and 7679 transitions. Second operand 6 states. [2018-11-23 03:49:10,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:10,956 INFO L93 Difference]: Finished difference Result 3582 states and 8908 transitions. [2018-11-23 03:49:10,956 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 03:49:10,956 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 93 [2018-11-23 03:49:10,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:10,960 INFO L225 Difference]: With dead ends: 3582 [2018-11-23 03:49:10,961 INFO L226 Difference]: Without dead ends: 3582 [2018-11-23 03:49:10,961 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:49:10,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3582 states. [2018-11-23 03:49:10,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3582 to 3082. [2018-11-23 03:49:10,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3082 states. [2018-11-23 03:49:11,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3082 states to 3082 states and 7728 transitions. [2018-11-23 03:49:11,002 INFO L78 Accepts]: Start accepts. Automaton has 3082 states and 7728 transitions. Word has length 93 [2018-11-23 03:49:11,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:11,002 INFO L480 AbstractCegarLoop]: Abstraction has 3082 states and 7728 transitions. [2018-11-23 03:49:11,002 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:49:11,002 INFO L276 IsEmpty]: Start isEmpty. Operand 3082 states and 7728 transitions. [2018-11-23 03:49:11,005 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 03:49:11,005 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:11,005 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:11,006 INFO L423 AbstractCegarLoop]: === Iteration 22 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:11,006 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:11,006 INFO L82 PathProgramCache]: Analyzing trace with hash -1093073861, now seen corresponding path program 2 times [2018-11-23 03:49:11,006 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:11,006 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:11,007 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:11,007 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:11,008 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:11,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:11,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:11,139 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:11,139 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 03:49:11,139 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 03:49:11,140 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 03:49:11,140 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:49:11,140 INFO L87 Difference]: Start difference. First operand 3082 states and 7728 transitions. Second operand 7 states. [2018-11-23 03:49:11,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:11,438 INFO L93 Difference]: Finished difference Result 3099 states and 7760 transitions. [2018-11-23 03:49:11,438 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-23 03:49:11,439 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 93 [2018-11-23 03:49:11,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:11,441 INFO L225 Difference]: With dead ends: 3099 [2018-11-23 03:49:11,441 INFO L226 Difference]: Without dead ends: 3099 [2018-11-23 03:49:11,442 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2018-11-23 03:49:11,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3099 states. [2018-11-23 03:49:11,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3099 to 3082. [2018-11-23 03:49:11,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3082 states. [2018-11-23 03:49:11,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3082 states to 3082 states and 7725 transitions. [2018-11-23 03:49:11,475 INFO L78 Accepts]: Start accepts. Automaton has 3082 states and 7725 transitions. Word has length 93 [2018-11-23 03:49:11,476 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:11,476 INFO L480 AbstractCegarLoop]: Abstraction has 3082 states and 7725 transitions. [2018-11-23 03:49:11,476 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 03:49:11,476 INFO L276 IsEmpty]: Start isEmpty. Operand 3082 states and 7725 transitions. [2018-11-23 03:49:11,478 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 03:49:11,478 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:11,478 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:11,478 INFO L423 AbstractCegarLoop]: === Iteration 23 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:11,478 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:11,478 INFO L82 PathProgramCache]: Analyzing trace with hash 1409070332, now seen corresponding path program 1 times [2018-11-23 03:49:11,478 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:11,478 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:11,479 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:11,479 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 03:49:11,480 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:11,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:11,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:11,575 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:11,575 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 03:49:11,575 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 03:49:11,575 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 03:49:11,575 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:49:11,576 INFO L87 Difference]: Start difference. First operand 3082 states and 7725 transitions. Second operand 7 states. [2018-11-23 03:49:11,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:11,764 INFO L93 Difference]: Finished difference Result 4056 states and 10447 transitions. [2018-11-23 03:49:11,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 03:49:11,764 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 93 [2018-11-23 03:49:11,764 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:11,767 INFO L225 Difference]: With dead ends: 4056 [2018-11-23 03:49:11,767 INFO L226 Difference]: Without dead ends: 4056 [2018-11-23 03:49:11,767 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=76, Invalid=134, Unknown=0, NotChecked=0, Total=210 [2018-11-23 03:49:11,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4056 states. [2018-11-23 03:49:11,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4056 to 2458. [2018-11-23 03:49:11,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2458 states. [2018-11-23 03:49:11,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2458 states to 2458 states and 6206 transitions. [2018-11-23 03:49:11,788 INFO L78 Accepts]: Start accepts. Automaton has 2458 states and 6206 transitions. Word has length 93 [2018-11-23 03:49:11,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:11,788 INFO L480 AbstractCegarLoop]: Abstraction has 2458 states and 6206 transitions. [2018-11-23 03:49:11,789 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 03:49:11,789 INFO L276 IsEmpty]: Start isEmpty. Operand 2458 states and 6206 transitions. [2018-11-23 03:49:11,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 03:49:11,790 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:11,790 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:11,790 INFO L423 AbstractCegarLoop]: === Iteration 24 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:11,791 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:11,791 INFO L82 PathProgramCache]: Analyzing trace with hash 494071612, now seen corresponding path program 1 times [2018-11-23 03:49:11,791 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:11,791 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:11,791 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:11,792 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:11,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:11,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:11,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:11,843 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:11,843 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:49:11,843 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:49:11,843 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:49:11,843 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:49:11,844 INFO L87 Difference]: Start difference. First operand 2458 states and 6206 transitions. Second operand 5 states. [2018-11-23 03:49:11,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:11,949 INFO L93 Difference]: Finished difference Result 2810 states and 7070 transitions. [2018-11-23 03:49:11,950 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:49:11,950 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 93 [2018-11-23 03:49:11,950 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:11,953 INFO L225 Difference]: With dead ends: 2810 [2018-11-23 03:49:11,953 INFO L226 Difference]: Without dead ends: 2778 [2018-11-23 03:49:11,953 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:49:11,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2778 states. [2018-11-23 03:49:11,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2778 to 2506. [2018-11-23 03:49:11,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2506 states. [2018-11-23 03:49:11,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2506 states to 2506 states and 6310 transitions. [2018-11-23 03:49:11,981 INFO L78 Accepts]: Start accepts. Automaton has 2506 states and 6310 transitions. Word has length 93 [2018-11-23 03:49:11,981 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:11,982 INFO L480 AbstractCegarLoop]: Abstraction has 2506 states and 6310 transitions. [2018-11-23 03:49:11,982 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:49:11,982 INFO L276 IsEmpty]: Start isEmpty. Operand 2506 states and 6310 transitions. [2018-11-23 03:49:11,984 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 03:49:11,984 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:11,984 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:11,984 INFO L423 AbstractCegarLoop]: === Iteration 25 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:11,984 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:11,984 INFO L82 PathProgramCache]: Analyzing trace with hash 1738836093, now seen corresponding path program 1 times [2018-11-23 03:49:11,984 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:11,985 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:11,985 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:11,986 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:11,986 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:12,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:12,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:12,066 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:12,066 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 03:49:12,066 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 03:49:12,066 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 03:49:12,066 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:49:12,066 INFO L87 Difference]: Start difference. First operand 2506 states and 6310 transitions. Second operand 7 states. [2018-11-23 03:49:12,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:12,227 INFO L93 Difference]: Finished difference Result 4157 states and 10693 transitions. [2018-11-23 03:49:12,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 03:49:12,227 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 93 [2018-11-23 03:49:12,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:12,229 INFO L225 Difference]: With dead ends: 4157 [2018-11-23 03:49:12,229 INFO L226 Difference]: Without dead ends: 1726 [2018-11-23 03:49:12,229 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2018-11-23 03:49:12,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1726 states. [2018-11-23 03:49:12,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1726 to 1726. [2018-11-23 03:49:12,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1726 states. [2018-11-23 03:49:12,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1726 states to 1726 states and 4513 transitions. [2018-11-23 03:49:12,243 INFO L78 Accepts]: Start accepts. Automaton has 1726 states and 4513 transitions. Word has length 93 [2018-11-23 03:49:12,243 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:12,243 INFO L480 AbstractCegarLoop]: Abstraction has 1726 states and 4513 transitions. [2018-11-23 03:49:12,243 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 03:49:12,243 INFO L276 IsEmpty]: Start isEmpty. Operand 1726 states and 4513 transitions. [2018-11-23 03:49:12,245 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 03:49:12,245 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:12,245 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:12,245 INFO L423 AbstractCegarLoop]: === Iteration 26 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:12,245 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:12,246 INFO L82 PathProgramCache]: Analyzing trace with hash -1752144950, now seen corresponding path program 1 times [2018-11-23 03:49:12,246 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:12,246 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:12,247 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:12,247 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:12,247 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:12,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:12,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:12,297 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:12,297 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:49:12,298 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:49:12,298 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:49:12,298 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:49:12,298 INFO L87 Difference]: Start difference. First operand 1726 states and 4513 transitions. Second operand 6 states. [2018-11-23 03:49:12,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:12,375 INFO L93 Difference]: Finished difference Result 1812 states and 4666 transitions. [2018-11-23 03:49:12,375 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:49:12,376 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 93 [2018-11-23 03:49:12,376 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:12,378 INFO L225 Difference]: With dead ends: 1812 [2018-11-23 03:49:12,378 INFO L226 Difference]: Without dead ends: 1792 [2018-11-23 03:49:12,378 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:49:12,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1792 states. [2018-11-23 03:49:12,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1792 to 1718. [2018-11-23 03:49:12,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1718 states. [2018-11-23 03:49:12,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1718 states to 1718 states and 4487 transitions. [2018-11-23 03:49:12,396 INFO L78 Accepts]: Start accepts. Automaton has 1718 states and 4487 transitions. Word has length 93 [2018-11-23 03:49:12,396 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:12,396 INFO L480 AbstractCegarLoop]: Abstraction has 1718 states and 4487 transitions. [2018-11-23 03:49:12,396 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:49:12,396 INFO L276 IsEmpty]: Start isEmpty. Operand 1718 states and 4487 transitions. [2018-11-23 03:49:12,398 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 03:49:12,398 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:12,398 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:12,398 INFO L423 AbstractCegarLoop]: === Iteration 27 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:12,398 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:12,398 INFO L82 PathProgramCache]: Analyzing trace with hash 2094125707, now seen corresponding path program 2 times [2018-11-23 03:49:12,398 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:12,398 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:12,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:12,399 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:49:12,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:12,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:49:12,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:49:12,538 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:49:12,538 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-23 03:49:12,538 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-23 03:49:12,538 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-23 03:49:12,538 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=111, Unknown=0, NotChecked=0, Total=132 [2018-11-23 03:49:12,539 INFO L87 Difference]: Start difference. First operand 1718 states and 4487 transitions. Second operand 12 states. [2018-11-23 03:49:12,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:49:12,869 INFO L93 Difference]: Finished difference Result 3315 states and 8720 transitions. [2018-11-23 03:49:12,870 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-23 03:49:12,870 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 93 [2018-11-23 03:49:12,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:49:12,872 INFO L225 Difference]: With dead ends: 3315 [2018-11-23 03:49:12,872 INFO L226 Difference]: Without dead ends: 2339 [2018-11-23 03:49:12,872 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=100, Invalid=550, Unknown=0, NotChecked=0, Total=650 [2018-11-23 03:49:12,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2339 states. [2018-11-23 03:49:12,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2339 to 2187. [2018-11-23 03:49:12,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2187 states. [2018-11-23 03:49:12,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2187 states to 2187 states and 5546 transitions. [2018-11-23 03:49:12,892 INFO L78 Accepts]: Start accepts. Automaton has 2187 states and 5546 transitions. Word has length 93 [2018-11-23 03:49:12,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:49:12,892 INFO L480 AbstractCegarLoop]: Abstraction has 2187 states and 5546 transitions. [2018-11-23 03:49:12,892 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-23 03:49:12,892 INFO L276 IsEmpty]: Start isEmpty. Operand 2187 states and 5546 transitions. [2018-11-23 03:49:12,895 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 03:49:12,895 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:49:12,895 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:49:12,895 INFO L423 AbstractCegarLoop]: === Iteration 28 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:49:12,895 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:49:12,895 INFO L82 PathProgramCache]: Analyzing trace with hash 1369725745, now seen corresponding path program 3 times [2018-11-23 03:49:12,896 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:49:12,896 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:49:12,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:12,897 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 03:49:12,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:49:12,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 03:49:12,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 03:49:12,945 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [474] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [361] L-1-->L671: Formula: (= |v_#valid_5| (store |v_#valid_6| 0 0)) InVars {#valid=|v_#valid_6|} OutVars{#valid=|v_#valid_5|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [514] L671-->L672: Formula: (= v_~__unbuffered_cnt~0_5 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [451] L672-->L673: Formula: (= v_~main$tmp_guard0~0_1 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [?] -1 [384] L673-->L675: Formula: (= v_~main$tmp_guard1~0_3 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [430] L675-->L676: Formula: (= v_~x~0_9 0) InVars {} OutVars{~x~0=v_~x~0_9} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [348] L676-->L677: Formula: (= v_~x$flush_delayed~0_4 0) InVars {} OutVars{~x$flush_delayed~0=v_~x$flush_delayed~0_4} AuxVars[] AssignedVars[~x$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 [485] L677-->L678: Formula: (= v_~x$mem_tmp~0_2 0) InVars {} OutVars{~x$mem_tmp~0=v_~x$mem_tmp~0_2} AuxVars[] AssignedVars[~x$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 [420] L678-->L679: Formula: (= v_~x$r_buff0_thd0~0_16 0) InVars {} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_16} AuxVars[] AssignedVars[~x$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 [522] L679-->L680: Formula: (= v_~x$r_buff0_thd1~0_13 0) InVars {} OutVars{~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_13} AuxVars[] AssignedVars[~x$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 [455] L680-->L681: Formula: (= v_~x$r_buff0_thd2~0_14 0) InVars {} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_14} AuxVars[] AssignedVars[~x$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 [387] L681-->L682: Formula: (= v_~x$r_buff1_thd0~0_10 0) InVars {} OutVars{~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_10} AuxVars[] AssignedVars[~x$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 [513] L682-->L683: Formula: (= v_~x$r_buff1_thd1~0_9 0) InVars {} OutVars{~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_9} AuxVars[] AssignedVars[~x$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 [449] L683-->L684: Formula: (= v_~x$r_buff1_thd2~0_9 0) InVars {} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_9} AuxVars[] AssignedVars[~x$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 [383] L684-->L685: Formula: (= v_~x$read_delayed~0_1 0) InVars {} OutVars{~x$read_delayed~0=v_~x$read_delayed~0_1} AuxVars[] AssignedVars[~x$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 [492] L685-->L686: Formula: (and (= v_~x$read_delayed_var~0.offset_1 0) (= v_~x$read_delayed_var~0.base_1 0)) InVars {} OutVars{~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_1, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~x$read_delayed_var~0.offset, ~x$read_delayed_var~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 [429] L686-->L687: Formula: (= v_~x$w_buff0~0_5 0) InVars {} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_5} AuxVars[] AssignedVars[~x$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 [379] L687-->L688: Formula: (= v_~x$w_buff0_used~0_38 0) InVars {} OutVars{~x$w_buff0_used~0=v_~x$w_buff0_used~0_38} AuxVars[] AssignedVars[~x$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 [484] L688-->L689: Formula: (= v_~x$w_buff1~0_4 0) InVars {} OutVars{~x$w_buff1~0=v_~x$w_buff1~0_4} AuxVars[] AssignedVars[~x$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 [418] L689-->L691: Formula: (= v_~x$w_buff1_used~0_24 0) InVars {} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_24} AuxVars[] AssignedVars[~x$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 [454] L691-->L692: Formula: (= v_~y~0_4 0) InVars {} OutVars{~y~0=v_~y~0_4} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [386] L692-->L693: Formula: (= v_~weak$$choice0~0_1 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_1} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [511] L693-->L-1-1: Formula: (= v_~weak$$choice2~0_7 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_7} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [512] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [509] L-1-2-->L753: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_1|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_1|, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_1|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_5|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_5|, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_1|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_1|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_5|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_1|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_5|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_1|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_5|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_1|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_5|, ULTIMATE.start_main_~#t2478~0.offset=|v_ULTIMATE.start_main_~#t2478~0.offset_3|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_1|, ULTIMATE.start_main_#t~nondet26.base=|v_ULTIMATE.start_main_#t~nondet26.base_1|, ULTIMATE.start_main_#t~nondet25.base=|v_ULTIMATE.start_main_#t~nondet25.base_1|, ULTIMATE.start_main_~#t2477~0.offset=|v_ULTIMATE.start_main_~#t2477~0.offset_3|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_5|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_1|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_2|, ULTIMATE.start_main_~#t2477~0.base=|v_ULTIMATE.start_main_~#t2477~0.base_3|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_2|, ULTIMATE.start_main_#t~nondet26.offset=|v_ULTIMATE.start_main_#t~nondet26.offset_1|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_5|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_3|, ULTIMATE.start_main_#t~nondet25.offset=|v_ULTIMATE.start_main_#t~nondet25.offset_1|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_1|, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_1|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_1|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_1|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_5|, ULTIMATE.start_main_~#t2478~0.base=|v_ULTIMATE.start_main_~#t2478~0.base_3|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_5|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_1|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t2478~0.offset, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~nondet26.base, ULTIMATE.start_main_#t~nondet25.base, ULTIMATE.start_main_~#t2477~0.offset, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_~#t2477~0.base, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~nondet26.offset, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~nondet25.offset, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_~#t2478~0.base, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~nondet17, ULTIMATE.start_main_#t~nondet18] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [368] L753-->L753-1: Formula: (and (= (store |v_#valid_8| |v_ULTIMATE.start_main_~#t2477~0.base_4| 1) |v_#valid_7|) (not (= 0 |v_ULTIMATE.start_main_~#t2477~0.base_4|)) (= 0 (select |v_#valid_8| |v_ULTIMATE.start_main_~#t2477~0.base_4|)) (= |v_#length_1| (store |v_#length_2| |v_ULTIMATE.start_main_~#t2477~0.base_4| 4)) (= 0 |v_ULTIMATE.start_main_~#t2477~0.offset_4|)) InVars {#length=|v_#length_2|, #valid=|v_#valid_8|} OutVars{ULTIMATE.start_main_~#t2477~0.base=|v_ULTIMATE.start_main_~#t2477~0.base_4|, ULTIMATE.start_main_~#t2477~0.offset=|v_ULTIMATE.start_main_~#t2477~0.offset_4|, #length=|v_#length_1|, #valid=|v_#valid_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2477~0.offset, #valid, ULTIMATE.start_main_~#t2477~0.base, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [373] L753-1-->L754: Formula: (= (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t2477~0.base_5| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t2477~0.base_5|) |v_ULTIMATE.start_main_~#t2477~0.offset_5| 0)) |v_#memory_int_1|) InVars {#memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t2477~0.base=|v_ULTIMATE.start_main_~#t2477~0.base_5|, ULTIMATE.start_main_~#t2477~0.offset=|v_ULTIMATE.start_main_~#t2477~0.offset_5|} OutVars{#memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t2477~0.base=|v_ULTIMATE.start_main_~#t2477~0.base_5|, ULTIMATE.start_main_~#t2477~0.offset=|v_ULTIMATE.start_main_~#t2477~0.offset_5|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 [575] L754-->P0ENTRY: Formula: (and (= 0 |v_Thread0_P0_#in~arg.offset_3|) (= 0 v_Thread0_P0_thidvar0_2) (= 0 |v_Thread0_P0_#in~arg.base_3|)) InVars {} OutVars{Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_3|, Thread0_P0_thidvar0=v_Thread0_P0_thidvar0_2, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P0_#in~arg.base, Thread0_P0_thidvar0, Thread0_P0_#in~arg.offset] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [480] L754-1-->L755: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [412] L755-->L755-1: Formula: (and (= (store |v_#length_4| |v_ULTIMATE.start_main_~#t2478~0.base_4| 4) |v_#length_3|) (= 0 (select |v_#valid_10| |v_ULTIMATE.start_main_~#t2478~0.base_4|)) (= 0 |v_ULTIMATE.start_main_~#t2478~0.offset_4|) (not (= 0 |v_ULTIMATE.start_main_~#t2478~0.base_4|)) (= |v_#valid_9| (store |v_#valid_10| |v_ULTIMATE.start_main_~#t2478~0.base_4| 1))) InVars {#length=|v_#length_4|, #valid=|v_#valid_10|} OutVars{ULTIMATE.start_main_~#t2478~0.offset=|v_ULTIMATE.start_main_~#t2478~0.offset_4|, ULTIMATE.start_main_~#t2478~0.base=|v_ULTIMATE.start_main_~#t2478~0.base_4|, #length=|v_#length_3|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2478~0.offset, ULTIMATE.start_main_~#t2478~0.base, #valid, #length] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [414] L755-1-->L756: Formula: (= |v_#memory_int_3| (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t2478~0.base_5| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t2478~0.base_5|) |v_ULTIMATE.start_main_~#t2478~0.offset_5| 1))) InVars {#memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t2478~0.offset=|v_ULTIMATE.start_main_~#t2478~0.offset_5|, ULTIMATE.start_main_~#t2478~0.base=|v_ULTIMATE.start_main_~#t2478~0.base_5|} OutVars{#memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t2478~0.offset=|v_ULTIMATE.start_main_~#t2478~0.offset_5|, ULTIMATE.start_main_~#t2478~0.base=|v_ULTIMATE.start_main_~#t2478~0.base_5|} AuxVars[] AssignedVars[#memory_int] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 [576] L756-->P1ENTRY: Formula: (and (= 0 |v_Thread1_P1_#in~arg.base_3|) (= 0 |v_Thread1_P1_#in~arg.offset_3|) (= 1 v_Thread1_P1_thidvar0_2)) InVars {} OutVars{Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_3|, Thread1_P1_thidvar0=v_Thread1_P1_thidvar0_2, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread1_P1_#in~arg.base, Thread1_P1_thidvar0, Thread1_P1_#in~arg.offset] VAL [Thread0_P0_thidvar0=0, Thread1_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [548] P1ENTRY-->L4: Formula: (and (= v_Thread1_P1_~arg.offset_1 |v_Thread1_P1_#in~arg.offset_1|) (= v_~x$w_buff0~0_2 2) (= v_Thread1_P1_~arg.base_1 |v_Thread1_P1_#in~arg.base_1|) (= v_Thread1_P1___VERIFIER_assert_~expression_1 |v_Thread1_P1___VERIFIER_assert_#in~expression_1|) (= v_~x$w_buff1~0_3 v_~x$w_buff0~0_3) (= v_~x$w_buff1_used~0_15 v_~x$w_buff0_used~0_22) (= v_~x$w_buff0_used~0_21 1) (= |v_Thread1_P1___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= 0 (mod v_~x$w_buff0_used~0_21 256))) (not (= 0 (mod v_~x$w_buff1_used~0_15 256))))) 1 0))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_3, Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_22} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_2, Thread1_P1___VERIFIER_assert_~expression=v_Thread1_P1___VERIFIER_assert_~expression_1, Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_~arg.offset=v_Thread1_P1_~arg.offset_1, Thread1_P1_~arg.base=v_Thread1_P1_~arg.base_1, ~x$w_buff1~0=v_~x$w_buff1~0_3, Thread1_P1___VERIFIER_assert_#in~expression=|v_Thread1_P1___VERIFIER_assert_#in~expression_1|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_15, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_21} AuxVars[] AssignedVars[~x$w_buff0~0, Thread1_P1___VERIFIER_assert_~expression, Thread1_P1_~arg.offset, Thread1_P1_~arg.base, ~x$w_buff1~0, Thread1_P1___VERIFIER_assert_#in~expression, ~x$w_buff1_used~0, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [550] L4-->L4-3: Formula: (not (= v_Thread1_P1___VERIFIER_assert_~expression_3 0)) InVars {Thread1_P1___VERIFIER_assert_~expression=v_Thread1_P1___VERIFIER_assert_~expression_3} OutVars{Thread1_P1___VERIFIER_assert_~expression=v_Thread1_P1___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [553] L4-3-->L731: Formula: (and (= v_~x$r_buff1_thd2~0_8 v_~x$r_buff0_thd2~0_11) (= v_~x$r_buff1_thd0~0_1 v_~x$r_buff0_thd0~0_1) (= v_~x$r_buff0_thd2~0_10 1) (= v_~x$r_buff1_thd1~0_8 v_~x$r_buff0_thd1~0_12) (= v_~y~0_2 1)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_12, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_11} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_12, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_8, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_8, ~y~0=v_~y~0_2, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_10, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_1} AuxVars[] AssignedVars[~x$r_buff1_thd2~0, ~x$r_buff1_thd1~0, ~y~0, ~x$r_buff0_thd2~0, ~x$r_buff1_thd0~0] VAL [Thread0_P0_thidvar0=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 0 [554] L731-->L731-5: Formula: (and (not (= 0 (mod v_~x$r_buff0_thd2~0_12 256))) (= |v_Thread1_P1_#t~ite11_1| v_~x$w_buff0~0_4) (not (= 0 (mod v_~x$w_buff0_used~0_23 256)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_4, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_12, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_23} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_4, Thread1_P1_#t~ite11=|v_Thread1_P1_#t~ite11_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_12, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_23} AuxVars[] AssignedVars[Thread1_P1_#t~ite11] VAL [Thread0_P0_thidvar0=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 1 [526] P0ENTRY-->L703: Formula: (and (= v_Thread0_P0_~arg.base_1 |v_Thread0_P0_#in~arg.base_1|) (= v_Thread0_P0_~arg.offset_1 |v_Thread0_P0_#in~arg.offset_1|) (= v_~y~0_1 2) (= v_~x~0_1 1)) InVars {Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|} OutVars{Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_~arg.offset=v_Thread0_P0_~arg.offset_1, Thread0_P0_~arg.base=v_Thread0_P0_~arg.base_1, ~y~0=v_~y~0_1, ~x~0=v_~x~0_1, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|} AuxVars[] AssignedVars[Thread0_P0_~arg.offset, Thread0_P0_~arg.base, ~y~0, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [528] L703-->L703-2: Formula: (or (= 0 (mod v_~x$r_buff0_thd1~0_4 256)) (= 0 (mod v_~x$w_buff0_used~0_3 256))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} OutVars{~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [531] L703-2-->L703-4: Formula: (and (or (= 0 (mod v_~x$w_buff1_used~0_4 256)) (= (mod v_~x$r_buff1_thd1~0_4 256) 0)) (= |v_Thread0_P0_#t~ite3_3| v_~x~0_2)) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_4, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_4, ~x~0=v_~x~0_2} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_4, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_4, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_3|, ~x~0=v_~x~0_2} AuxVars[] AssignedVars[Thread0_P0_#t~ite3] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite3|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [534] L703-4-->L703-5: Formula: (= |v_Thread0_P0_#t~ite4_4| |v_Thread0_P0_#t~ite3_4|) InVars {Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_4|} OutVars{Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_4|, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_4|} AuxVars[] AssignedVars[Thread0_P0_#t~ite4] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite3|=1, |Thread0_P0_#t~ite4|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [529] L703-5-->L704: Formula: (= v_~x~0_3 |v_Thread0_P0_#t~ite4_2|) InVars {Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_2|} OutVars{Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_3|, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_1|, ~x~0=v_~x~0_3} AuxVars[] AssignedVars[Thread0_P0_#t~ite4, Thread0_P0_#t~ite3, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [533] L704-->L704-2: Formula: (and (= |v_Thread0_P0_#t~ite5_2| v_~x$w_buff0_used~0_7) (or (= 0 (mod v_~x$w_buff0_used~0_7 256)) (= (mod v_~x$r_buff0_thd1~0_8 256) 0))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_7} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_2|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_7} AuxVars[] AssignedVars[Thread0_P0_#t~ite5] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite5|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [535] L704-2-->L705: Formula: (= v_~x$w_buff0_used~0_8 |v_Thread0_P0_#t~ite5_3|) InVars {Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_3|} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_8} AuxVars[] AssignedVars[Thread0_P0_#t~ite5, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [537] L705-->L705-2: Formula: (and (= |v_Thread0_P0_#t~ite6_2| v_~x$w_buff1_used~0_6) (or (= (mod v_~x$w_buff0_used~0_10 256) 0) (= (mod v_~x$r_buff0_thd1~0_10 256) 0)) (or (= 0 (mod v_~x$w_buff1_used~0_6 256)) (= (mod v_~x$r_buff1_thd1~0_7 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_6, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_10} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_6, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_10} AuxVars[] AssignedVars[Thread0_P0_#t~ite6] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite6|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [538] L705-2-->L706: Formula: (= v_~x$w_buff1_used~0_7 |v_Thread0_P0_#t~ite6_3|) InVars {Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_3|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_7, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, Thread0_P0_#t~ite6] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 0 [556] L731-5-->L732: Formula: (= v_~x~0_5 |v_Thread1_P1_#t~ite11_2|) InVars {Thread1_P1_#t~ite11=|v_Thread1_P1_#t~ite11_2|} OutVars{Thread1_P1_#t~ite11=|v_Thread1_P1_#t~ite11_3|, ~x~0=v_~x~0_5, Thread1_P1_#t~ite10=|v_Thread1_P1_#t~ite10_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite10, Thread1_P1_#t~ite11, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 [540] L706-->L706-2: Formula: (and (= |v_Thread0_P0_#t~ite7_2| v_~x$r_buff0_thd1~0_1) (or (= (mod v_~x$w_buff0_used~0_1 256) 0) (= 0 (mod v_~x$r_buff0_thd1~0_1 256)))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_1} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_2|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_1} AuxVars[] AssignedVars[Thread0_P0_#t~ite7] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite7|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 [541] L706-2-->L707: Formula: (= v_~x$r_buff0_thd1~0_3 |v_Thread0_P0_#t~ite7_3|) InVars {Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_3|} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_4|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_3} AuxVars[] AssignedVars[~x$r_buff0_thd1~0, Thread0_P0_#t~ite7] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 [559] L732-->L732-2: Formula: (and (not (= (mod v_~x$w_buff0_used~0_12 256) 0)) (= |v_Thread1_P1_#t~ite12_1| 0) (not (= (mod v_~x$r_buff0_thd2~0_1 256) 0))) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_12} OutVars{Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_12} AuxVars[] AssignedVars[Thread1_P1_#t~ite12] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite12|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 [562] L732-2-->L733: Formula: (= v_~x$w_buff0_used~0_14 |v_Thread1_P1_#t~ite12_3|) InVars {Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_3|} OutVars{Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_14} AuxVars[] AssignedVars[Thread1_P1_#t~ite12, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 [564] L733-->L733-2: Formula: (and (= |v_Thread1_P1_#t~ite13_2| v_~x$w_buff1_used~0_11) (or (= 0 (mod v_~x$w_buff1_used~0_11 256)) (= 0 (mod v_~x$r_buff1_thd2~0_4 256))) (or (= (mod v_~x$r_buff0_thd2~0_4 256) 0) (= (mod v_~x$w_buff0_used~0_16 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_11, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_4, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_16} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_11, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_4, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_16} AuxVars[] AssignedVars[Thread1_P1_#t~ite13] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite13|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 [565] L733-2-->L734: Formula: (= v_~x$w_buff1_used~0_12 |v_Thread1_P1_#t~ite13_3|) InVars {Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_3|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_12, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, Thread1_P1_#t~ite13] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 [567] L734-->L734-2: Formula: (and (or (= (mod v_~x$r_buff0_thd2~0_6 256) 0) (= 0 (mod v_~x$w_buff0_used~0_18 256))) (= |v_Thread1_P1_#t~ite14_2| v_~x$r_buff0_thd2~0_6)) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_18} OutVars{Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_18} AuxVars[] AssignedVars[Thread1_P1_#t~ite14] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite14|=1, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 [568] L734-2-->L735: Formula: (= v_~x$r_buff0_thd2~0_7 |v_Thread1_P1_#t~ite14_3|) InVars {Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_3|} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_7, Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_4|} AuxVars[] AssignedVars[Thread1_P1_#t~ite14, ~x$r_buff0_thd2~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 [570] L735-->L735-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_20 256) 0) (= (mod v_~x$r_buff0_thd2~0_9 256) 0)) (= |v_Thread1_P1_#t~ite15_2| v_~x$r_buff1_thd2~0_6) (or (= 0 (mod v_~x$r_buff1_thd2~0_6 256)) (= 0 (mod v_~x$w_buff1_used~0_14 256)))) InVars {~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_14, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_9, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_20} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_14, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_9, Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_20} AuxVars[] AssignedVars[Thread1_P1_#t~ite15] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite15|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 [571] L735-2-->L740: Formula: (and (= v_~x$r_buff1_thd2~0_7 |v_Thread1_P1_#t~ite15_3|) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_7, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_4|} AuxVars[] AssignedVars[~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, Thread1_P1_#t~ite15] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 [543] L707-->L707-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_5 256) 0) (= 0 (mod v_~x$r_buff0_thd1~0_6 256))) (or (= (mod v_~x$r_buff1_thd1~0_3 256) 0) (= (mod v_~x$w_buff1_used~0_3 256) 0)) (= |v_Thread0_P0_#t~ite8_2| v_~x$r_buff1_thd1~0_3)) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_3, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_6, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_3, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_3, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_6, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_3, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} AuxVars[] AssignedVars[Thread0_P0_#t~ite8] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite8|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 [544] L707-2-->L712: Formula: (and (= v_~x$r_buff1_thd1~0_5 |v_Thread0_P0_#t~ite8_3|) (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1))) InVars {Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_5, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_4|} AuxVars[] AssignedVars[~__unbuffered_cnt~0, ~x$r_buff1_thd1~0, Thread0_P0_#t~ite8] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [518] L756-1-->L760: Formula: (= v_~main$tmp_guard0~0_2 (ite (= (ite (= v_~__unbuffered_cnt~0_6 2) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_2, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_2|} AuxVars[] AssignedVars[~main$tmp_guard0~0, ULTIMATE.start_main_#t~nondet18] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [448] L760-->L762: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_3 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [502] L762-->L762-2: Formula: (or (= 0 (mod v_~x$w_buff0_used~0_40 256)) (= 0 (mod v_~x$r_buff0_thd0~0_18 256))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_18, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_40} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_18, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_40} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [491] L762-2-->L762-4: Formula: (and (or (= (mod v_~x$w_buff1_used~0_26 256) 0) (= 0 (mod v_~x$r_buff1_thd0~0_12 256))) (= |v_ULTIMATE.start_main_#t~ite19_3| v_~x~0_10)) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_26, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_12, ~x~0=v_~x~0_10} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_26, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_12, ~x~0=v_~x~0_10, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [495] L762-4-->L762-5: Formula: (= |v_ULTIMATE.start_main_#t~ite20_3| |v_ULTIMATE.start_main_#t~ite19_4|) InVars {ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_4|} OutVars{ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_3|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_#t~ite20|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [497] L762-5-->L763: Formula: (= v_~x~0_11 |v_ULTIMATE.start_main_#t~ite20_5|) InVars {ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_5|} OutVars{ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_4|, ~x~0=v_~x~0_11, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite20, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [442] L763-->L763-2: Formula: (and (or (= 0 (mod v_~x$r_buff0_thd0~0_20 256)) (= (mod v_~x$w_buff0_used~0_42 256) 0)) (= |v_ULTIMATE.start_main_#t~ite21_3| v_~x$w_buff0_used~0_42)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_20, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_42} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_20, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_42} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite21|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [426] L763-2-->L764: Formula: (= v_~x$w_buff0_used~0_43 |v_ULTIMATE.start_main_#t~ite21_5|) InVars {ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_5|} OutVars{ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_43} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [367] L764-->L764-2: Formula: (and (or (= 0 (mod v_~x$r_buff1_thd0~0_14 256)) (= 0 (mod v_~x$w_buff1_used~0_28 256))) (or (= (mod v_~x$w_buff0_used~0_45 256) 0) (= 0 (mod v_~x$r_buff0_thd0~0_22 256))) (= |v_ULTIMATE.start_main_#t~ite22_3| v_~x$w_buff1_used~0_28)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_22, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_28, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_14, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_45} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_22, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_28, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_14, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_45} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite22|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [376] L764-2-->L765: Formula: (= v_~x$w_buff1_used~0_29 |v_ULTIMATE.start_main_#t~ite22_5|) InVars {ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_5|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_29, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite22] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [478] L765-->L765-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_47 256) 0) (= 0 (mod v_~x$r_buff0_thd0~0_24 256))) (= |v_ULTIMATE.start_main_#t~ite23_3| v_~x$r_buff0_thd0~0_24)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_24, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_47} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_24, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_47} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite23|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [483] L765-2-->L766: Formula: (= v_~x$r_buff0_thd0~0_25 |v_ULTIMATE.start_main_#t~ite23_5|) InVars {ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_5|} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_25, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_4|} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite23] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [410] L766-->L766-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite24_3| v_~x$r_buff1_thd0~0_16) (or (= (mod v_~x$w_buff1_used~0_31 256) 0) (= (mod v_~x$r_buff1_thd0~0_16 256) 0)) (or (= (mod v_~x$w_buff0_used~0_49 256) 0) (= (mod v_~x$r_buff0_thd0~0_27 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_27, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_31, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_16, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_49} OutVars{ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_3|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_27, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_31, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_16, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_49} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite24|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [417] L766-2-->L773: Formula: (and (= v_~weak$$choice2~0_8 (ite (= 0 (+ |v_ULTIMATE.start_main_#t~nondet26.base_3| |v_ULTIMATE.start_main_#t~nondet26.offset_3|)) 0 1)) (= v_~x$r_buff1_thd0~0_17 |v_ULTIMATE.start_main_#t~ite24_5|) (= v_~x$flush_delayed~0_5 v_~weak$$choice2~0_8) (= v_~weak$$choice0~0_2 (ite (= 0 (+ |v_ULTIMATE.start_main_#t~nondet25.base_3| |v_ULTIMATE.start_main_#t~nondet25.offset_3|)) 0 1)) (= v_~x$mem_tmp~0_3 v_~x~0_12)) InVars {ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_5|, ULTIMATE.start_main_#t~nondet26.base=|v_ULTIMATE.start_main_#t~nondet26.base_3|, ULTIMATE.start_main_#t~nondet26.offset=|v_ULTIMATE.start_main_#t~nondet26.offset_3|, ULTIMATE.start_main_#t~nondet25.base=|v_ULTIMATE.start_main_#t~nondet25.base_3|, ULTIMATE.start_main_#t~nondet25.offset=|v_ULTIMATE.start_main_#t~nondet25.offset_3|, ~x~0=v_~x~0_12} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_2, ~x$flush_delayed~0=v_~x$flush_delayed~0_5, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_4|, ULTIMATE.start_main_#t~nondet26.base=|v_ULTIMATE.start_main_#t~nondet26.base_2|, ULTIMATE.start_main_#t~nondet26.offset=|v_ULTIMATE.start_main_#t~nondet26.offset_2|, ~x$mem_tmp~0=v_~x$mem_tmp~0_3, ULTIMATE.start_main_#t~nondet25.base=|v_ULTIMATE.start_main_#t~nondet25.base_2|, ~weak$$choice2~0=v_~weak$$choice2~0_8, ULTIMATE.start_main_#t~nondet25.offset=|v_ULTIMATE.start_main_#t~nondet25.offset_2|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_17, ~x~0=v_~x~0_12} AuxVars[] AssignedVars[~weak$$choice0~0, ~x$flush_delayed~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~nondet26.base, ULTIMATE.start_main_#t~nondet26.offset, ~x$mem_tmp~0, ULTIMATE.start_main_#t~nondet25.base, ~weak$$choice2~0, ULTIMATE.start_main_#t~nondet25.offset, ~x$r_buff1_thd0~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [499] L773-->L773-5: Formula: (and (= |v_ULTIMATE.start_main_#t~ite28_2| v_~x~0_13) (let ((.cse0 (= (mod v_~x$r_buff0_thd0~0_28 256) 0))) (or (and (= (mod v_~x$r_buff1_thd0~0_18 256) 0) .cse0) (and (= (mod v_~x$w_buff1_used~0_32 256) 0) .cse0) (= (mod v_~x$w_buff0_used~0_50 256) 0)))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_28, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_32, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_18, ~x~0=v_~x~0_13, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_50} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_28, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_2|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_32, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_18, ~x~0=v_~x~0_13, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_50} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite28|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [496] L773-5-->L774: Formula: (= v_~x~0_14 |v_ULTIMATE.start_main_#t~ite28_5|) InVars {ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_5|} OutVars{ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_5|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_4|, ~x~0=v_~x~0_14} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite27, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [437] L774-->L774-8: Formula: (and (= |v_ULTIMATE.start_main_#t~ite31_2| v_~x$w_buff0~0_8) (not (= (mod v_~weak$$choice2~0_9 256) 0))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_8, ~weak$$choice2~0=v_~weak$$choice2~0_9} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_8, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_2|, ~weak$$choice2~0=v_~weak$$choice2~0_9} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite31] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite31|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [411] L774-8-->L775: Formula: (= v_~x$w_buff0~0_12 |v_ULTIMATE.start_main_#t~ite31_5|) InVars {ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_5|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_12, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_5|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_4|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_5|} AuxVars[] AssignedVars[~x$w_buff0~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite31] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [364] L775-->L775-8: Formula: (and (not (= (mod v_~weak$$choice2~0_11 256) 0)) (= |v_ULTIMATE.start_main_#t~ite34_2| v_~x$w_buff1~0_7)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_11, ~x$w_buff1~0=v_~x$w_buff1~0_7} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_11, ~x$w_buff1~0=v_~x$w_buff1~0_7, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite34] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite34|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [360] L775-8-->L776: Formula: (= v_~x$w_buff1~0_11 |v_ULTIMATE.start_main_#t~ite34_5|) InVars {ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_5|} OutVars{ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_5|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_5|, ~x$w_buff1~0=v_~x$w_buff1~0_11, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_4|} AuxVars[] AssignedVars[~x$w_buff1~0, ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_#t~ite34] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [475] L776-->L776-8: Formula: (and (= |v_ULTIMATE.start_main_#t~ite37_4| v_~x$w_buff0_used~0_62) (not (= (mod v_~weak$$choice2~0_13 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_13, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_62} OutVars{ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_4|, ~weak$$choice2~0=v_~weak$$choice2~0_13, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_62} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite37] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite37|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [472] L776-8-->L777: Formula: (= v_~x$w_buff0_used~0_25 |v_ULTIMATE.start_main_#t~ite37_2|) InVars {ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_2|} OutVars{ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_1|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_1|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_25} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite37, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [407] L777-->L777-8: Formula: (and (= |v_ULTIMATE.start_main_#t~ite40_1| v_~x$w_buff1_used~0_16) (not (= (mod v_~weak$$choice2~0_1 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_1, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_16} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_16, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_1|, ~weak$$choice2~0=v_~weak$$choice2~0_1} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [402] L777-8-->L778: Formula: (= v_~x$w_buff1_used~0_19 |v_ULTIMATE.start_main_#t~ite40_4|) InVars {ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_4|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_19, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_4|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_3|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39, ~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite38] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [358] L778-->L778-8: Formula: (and (= |v_ULTIMATE.start_main_#t~ite43_1| v_~x$r_buff0_thd0~0_6) (not (= 0 (mod v_~weak$$choice2~0_3 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_3, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_1|, ~weak$$choice2~0=v_~weak$$choice2~0_3} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [508] L778-8-->L779: Formula: (= v_~x$r_buff0_thd0~0_11 |v_ULTIMATE.start_main_#t~ite43_4|) InVars {ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_4|} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_11, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_4|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_3|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [470] L779-->L779-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_5 256))) (= |v_ULTIMATE.start_main_#t~ite46_1| v_~x$r_buff1_thd0~0_6)) InVars {~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ~weak$$choice2~0=v_~weak$$choice2~0_5} OutVars{ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_1|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ~weak$$choice2~0=v_~weak$$choice2~0_5} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [447] L779-8-->L781: Formula: (and (= v_~x$r_buff1_thd0~0_9 |v_ULTIMATE.start_main_#t~ite46_4|) (= v_~main$tmp_guard1~0_1 (ite (= 0 (ite (not (and (= 2 v_~y~0_3) (= 2 v_~x~0_6))) 1 0)) 0 1))) InVars {ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_4|, ~y~0=v_~y~0_3, ~x~0=v_~x~0_6} OutVars{ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_3|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_1, ~y~0=v_~y~0_3, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_9, ~x~0=v_~x~0_6, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_4|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ~x$r_buff1_thd0~0, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [506] L781-->L781-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite47_1| v_~x$mem_tmp~0_1) (not (= 0 (mod v_~x$flush_delayed~0_1 256)))) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_1, ~x$mem_tmp~0=v_~x$mem_tmp~0_1} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_1|, ~x$mem_tmp~0=v_~x$mem_tmp~0_1, ~x$flush_delayed~0=v_~x$flush_delayed~0_1} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite47|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [510] L781-2-->L784: Formula: (and (= v_~x~0_8 |v_ULTIMATE.start_main_#t~ite47_4|) (= v_~x$flush_delayed~0_3 0)) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_4|} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_3|, ~x$flush_delayed~0=v_~x$flush_delayed~0_3, ~x~0=v_~x~0_8} AuxVars[] AssignedVars[~x$flush_delayed~0, ULTIMATE.start_main_#t~ite47, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [498] L784-->L784-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_2 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_2} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [503] L784-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [397] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [395] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [391] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25.base, main_#t~nondet25.offset, main_#t~nondet26.base, main_#t~nondet26.offset, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t2477~0.base, main_~#t2477~0.offset, main_~#t2478~0.base, main_~#t2478~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t2477~0.base, main_~#t2477~0.offset := #Ultimate.alloc(4); srcloc: L753 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t2477~0.base, main_~#t2477~0.offset, 4); srcloc: L753-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t2478~0.base, main_~#t2478~0.offset := #Ultimate.alloc(4); srcloc: L755 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t2478~0.base, main_~#t2478~0.offset, 4); srcloc: L755-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 2;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd2~0 := 1;~y~0 := 1; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256;#t~ite11 := ~x$w_buff0~0; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 2;~x~0 := 1; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256);#t~ite3 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite3|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 #t~ite4 := #t~ite3; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite3|=1, |P0_#t~ite4|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 ~x~0 := #t~ite4;havoc #t~ite3;havoc #t~ite4; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite5 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 ~x$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite6 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 ~x$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 0 ~x~0 := #t~ite11;havoc #t~ite11;havoc #t~ite10; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite7 := ~x$r_buff0_thd1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 ~x$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256;#t~ite12 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite12|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 ~x$w_buff0_used~0 := #t~ite12;havoc #t~ite12; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite13 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 ~x$w_buff1_used~0 := #t~ite13;havoc #t~ite13; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite14 := ~x$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite14|=1, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 ~x$r_buff0_thd2~0 := #t~ite14;havoc #t~ite14; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite15 := ~x$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite15|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 ~x$r_buff1_thd2~0 := #t~ite15;havoc #t~ite15;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite8 := ~x$r_buff1_thd1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 ~x$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 havoc main_#t~nondet18;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);main_#t~ite19 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 main_#t~ite20 := main_#t~ite19; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_#t~ite20|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x~0 := main_#t~ite20;havoc main_#t~ite19;havoc main_#t~ite20; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite21 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite21|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff0_used~0 := main_#t~ite21;havoc main_#t~ite21; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite22 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite22|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff1_used~0 := main_#t~ite22;havoc main_#t~ite22; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite23|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite23;havoc main_#t~ite23; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite24|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite24;havoc main_#t~ite24;~weak$$choice0~0 := (if 0 == main_#t~nondet25.base + main_#t~nondet25.offset then 0 else 1);havoc main_#t~nondet25.base, main_#t~nondet25.offset;~weak$$choice2~0 := (if 0 == main_#t~nondet26.base + main_#t~nondet26.offset then 0 else 1);havoc main_#t~nondet26.base, main_#t~nondet26.offset;~x$flush_delayed~0 := ~weak$$choice2~0;~x$mem_tmp~0 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256);main_#t~ite28 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite28|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x~0 := main_#t~ite28;havoc main_#t~ite28;havoc main_#t~ite27; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite31 := ~x$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite31|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff0~0 := main_#t~ite31;havoc main_#t~ite29;havoc main_#t~ite31;havoc main_#t~ite30; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite34 := ~x$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite34|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff1~0 := main_#t~ite34;havoc main_#t~ite33;havoc main_#t~ite32;havoc main_#t~ite34; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite37 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite37|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff0_used~0 := main_#t~ite37;havoc main_#t~ite36;havoc main_#t~ite37;havoc main_#t~ite35; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite40 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff1_used~0 := main_#t~ite40;havoc main_#t~ite39;havoc main_#t~ite38;havoc main_#t~ite40; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite43;havoc main_#t~ite41; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite46;havoc main_#t~ite44;havoc main_#t~ite46;havoc main_#t~ite45;~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 2 == ~y~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~x$flush_delayed~0 % 256;main_#t~ite47 := ~x$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite47|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x~0 := main_#t~ite47;havoc main_#t~ite47;~x$flush_delayed~0 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25.base, main_#t~nondet25.offset, main_#t~nondet26.base, main_#t~nondet26.offset, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t2477~0.base, main_~#t2477~0.offset, main_~#t2478~0.base, main_~#t2478~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t2477~0.base, main_~#t2477~0.offset := #Ultimate.alloc(4); srcloc: L753 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t2477~0.base, main_~#t2477~0.offset, 4); srcloc: L753-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t2478~0.base, main_~#t2478~0.offset := #Ultimate.alloc(4); srcloc: L755 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t2478~0.base, main_~#t2478~0.offset, 4); srcloc: L755-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 2;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd2~0 := 1;~y~0 := 1; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256;#t~ite11 := ~x$w_buff0~0; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 2;~x~0 := 1; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256);#t~ite3 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite3|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 #t~ite4 := #t~ite3; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite3|=1, |P0_#t~ite4|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 ~x~0 := #t~ite4;havoc #t~ite3;havoc #t~ite4; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite5 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 ~x$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite6 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 ~x$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 0 ~x~0 := #t~ite11;havoc #t~ite11;havoc #t~ite10; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite7 := ~x$r_buff0_thd1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 ~x$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256;#t~ite12 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite12|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 ~x$w_buff0_used~0 := #t~ite12;havoc #t~ite12; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite13 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 ~x$w_buff1_used~0 := #t~ite13;havoc #t~ite13; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite14 := ~x$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite14|=1, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 ~x$r_buff0_thd2~0 := #t~ite14;havoc #t~ite14; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite15 := ~x$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite15|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 ~x$r_buff1_thd2~0 := #t~ite15;havoc #t~ite15;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite8 := ~x$r_buff1_thd1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 ~x$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 havoc main_#t~nondet18;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);main_#t~ite19 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 main_#t~ite20 := main_#t~ite19; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_#t~ite20|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x~0 := main_#t~ite20;havoc main_#t~ite19;havoc main_#t~ite20; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite21 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite21|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff0_used~0 := main_#t~ite21;havoc main_#t~ite21; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite22 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite22|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff1_used~0 := main_#t~ite22;havoc main_#t~ite22; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite23|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite23;havoc main_#t~ite23; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite24|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite24;havoc main_#t~ite24;~weak$$choice0~0 := (if 0 == main_#t~nondet25.base + main_#t~nondet25.offset then 0 else 1);havoc main_#t~nondet25.base, main_#t~nondet25.offset;~weak$$choice2~0 := (if 0 == main_#t~nondet26.base + main_#t~nondet26.offset then 0 else 1);havoc main_#t~nondet26.base, main_#t~nondet26.offset;~x$flush_delayed~0 := ~weak$$choice2~0;~x$mem_tmp~0 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256);main_#t~ite28 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite28|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x~0 := main_#t~ite28;havoc main_#t~ite28;havoc main_#t~ite27; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite31 := ~x$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite31|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff0~0 := main_#t~ite31;havoc main_#t~ite29;havoc main_#t~ite31;havoc main_#t~ite30; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite34 := ~x$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite34|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff1~0 := main_#t~ite34;havoc main_#t~ite33;havoc main_#t~ite32;havoc main_#t~ite34; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite37 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite37|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff0_used~0 := main_#t~ite37;havoc main_#t~ite36;havoc main_#t~ite37;havoc main_#t~ite35; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite40 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff1_used~0 := main_#t~ite40;havoc main_#t~ite39;havoc main_#t~ite38;havoc main_#t~ite40; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite43;havoc main_#t~ite41; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite46;havoc main_#t~ite44;havoc main_#t~ite46;havoc main_#t~ite45;~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 2 == ~y~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~x$flush_delayed~0 % 256;main_#t~ite47 := ~x$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite47|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x~0 := main_#t~ite47;havoc main_#t~ite47;~x$flush_delayed~0 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L672] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [L673] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L675] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L676] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L677] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L678] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L679] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L681] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L682] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L684] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L685] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [L686] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L687] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L688] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L689] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L693] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25.base, main_#t~nondet25.offset, main_#t~nondet26.base, main_#t~nondet26.offset, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t2477~0.base, main_~#t2477~0.offset, main_~#t2478~0.base, main_~#t2478~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L753] -1 call main_~#t2477~0.base, main_~#t2477~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] -1 call write~int(0, main_~#t2477~0.base, main_~#t2477~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] -1 havoc main_#t~nondet17; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] -1 call main_~#t2478~0.base, main_~#t2478~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 call write~int(1, main_~#t2478~0.base, main_~#t2478~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L714-L741] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L717] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L718] 0 ~x$w_buff0~0 := 2; [L719] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L720] 0 ~x$w_buff0_used~0 := 1; [L721] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L721] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L722] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L723] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L724] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L725] 0 ~x$r_buff0_thd2~0 := 1; [L728] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L731] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256; [L731] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L694-L713] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L697] 1 ~y~0 := 2; [L700] 1 ~x~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256); [L703] 1 #t~ite3 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, #t~ite3=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 #t~ite4 := #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, #t~ite3=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 ~x~0 := #t~ite4; [L703] 1 havoc #t~ite3; [L703] 1 havoc #t~ite4; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L704] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] 1 ~x$w_buff0_used~0 := #t~ite5; [L704] 1 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L705] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] 1 ~x$w_buff1_used~0 := #t~ite6; [L705] 1 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L731] 0 ~x~0 := #t~ite11; [L731] 0 havoc #t~ite11; [L731] 0 havoc #t~ite10; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L706] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L706] 1 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256; [L732] 0 #t~ite12 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite12=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] 0 ~x$w_buff0_used~0 := #t~ite12; [L732] 0 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L733] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] 0 ~x$w_buff1_used~0 := #t~ite13; [L733] 0 havoc #t~ite13; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L734] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite14=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L734] 0 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L735] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite15=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L735] 0 havoc #t~ite15; [L738] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L707] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L707] 1 havoc #t~ite8; [L710] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L756] -1 havoc main_#t~nondet18; [L758] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L760] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L762] -1 main_#t~ite19 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 main_#t~ite20 := main_#t~ite19; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_#t~ite20=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 ~x~0 := main_#t~ite20; [L762] -1 havoc main_#t~ite19; [L762] -1 havoc main_#t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L763] -1 main_#t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite21=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] -1 ~x$w_buff0_used~0 := main_#t~ite21; [L763] -1 havoc main_#t~ite21; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L764] -1 main_#t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite22=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] -1 ~x$w_buff1_used~0 := main_#t~ite22; [L764] -1 havoc main_#t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L765] -1 main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite23=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] -1 ~x$r_buff0_thd0~0 := main_#t~ite23; [L765] -1 havoc main_#t~ite23; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L766] -1 main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite24=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] -1 ~x$r_buff1_thd0~0 := main_#t~ite24; [L766] -1 havoc main_#t~ite24; [L769] -1 ~weak$$choice0~0 := (if 0 == main_#t~nondet25.base + main_#t~nondet25.offset then 0 else 1); [L769] -1 havoc main_#t~nondet25.base, main_#t~nondet25.offset; [L770] -1 ~weak$$choice2~0 := (if 0 == main_#t~nondet26.base + main_#t~nondet26.offset then 0 else 1); [L770] -1 havoc main_#t~nondet26.base, main_#t~nondet26.offset; [L771] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L772] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] -1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256); [L773] -1 main_#t~ite28 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite28=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] -1 ~x~0 := main_#t~ite28; [L773] -1 havoc main_#t~ite28; [L773] -1 havoc main_#t~ite27; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] -1 assume 0 != ~weak$$choice2~0 % 256; [L774] -1 main_#t~ite31 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite31=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] -1 ~x$w_buff0~0 := main_#t~ite31; [L774] -1 havoc main_#t~ite29; [L774] -1 havoc main_#t~ite31; [L774] -1 havoc main_#t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] -1 assume 0 != ~weak$$choice2~0 % 256; [L775] -1 main_#t~ite34 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite34=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] -1 ~x$w_buff1~0 := main_#t~ite34; [L775] -1 havoc main_#t~ite33; [L775] -1 havoc main_#t~ite32; [L775] -1 havoc main_#t~ite34; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] -1 assume 0 != ~weak$$choice2~0 % 256; [L776] -1 main_#t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite37=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] -1 ~x$w_buff0_used~0 := main_#t~ite37; [L776] -1 havoc main_#t~ite36; [L776] -1 havoc main_#t~ite37; [L776] -1 havoc main_#t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] -1 assume 0 != ~weak$$choice2~0 % 256; [L777] -1 main_#t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] -1 ~x$w_buff1_used~0 := main_#t~ite40; [L777] -1 havoc main_#t~ite39; [L777] -1 havoc main_#t~ite38; [L777] -1 havoc main_#t~ite40; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] -1 assume 0 != ~weak$$choice2~0 % 256; [L778] -1 main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] -1 ~x$r_buff0_thd0~0 := main_#t~ite43; [L778] -1 havoc main_#t~ite42; [L778] -1 havoc main_#t~ite43; [L778] -1 havoc main_#t~ite41; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] -1 assume 0 != ~weak$$choice2~0 % 256; [L779] -1 main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] -1 ~x$r_buff1_thd0~0 := main_#t~ite46; [L779] -1 havoc main_#t~ite44; [L779] -1 havoc main_#t~ite46; [L779] -1 havoc main_#t~ite45; [L780] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 2 == ~y~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] -1 assume 0 != ~x$flush_delayed~0 % 256; [L781] -1 main_#t~ite47 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] -1 ~x~0 := main_#t~ite47; [L781] -1 havoc main_#t~ite47; [L782] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L784] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L784] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L672] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [L673] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L675] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L676] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L677] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L678] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L679] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L681] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L682] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L684] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L685] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [L686] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L687] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L688] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L689] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L693] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25.base, main_#t~nondet25.offset, main_#t~nondet26.base, main_#t~nondet26.offset, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t2477~0.base, main_~#t2477~0.offset, main_~#t2478~0.base, main_~#t2478~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L753] -1 call main_~#t2477~0.base, main_~#t2477~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] -1 call write~int(0, main_~#t2477~0.base, main_~#t2477~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] -1 havoc main_#t~nondet17; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] -1 call main_~#t2478~0.base, main_~#t2478~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 call write~int(1, main_~#t2478~0.base, main_~#t2478~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L714-L741] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L717] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L718] 0 ~x$w_buff0~0 := 2; [L719] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L720] 0 ~x$w_buff0_used~0 := 1; [L721] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L721] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L722] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L723] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L724] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L725] 0 ~x$r_buff0_thd2~0 := 1; [L728] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L731] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256; [L731] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L694-L713] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L697] 1 ~y~0 := 2; [L700] 1 ~x~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256); [L703] 1 #t~ite3 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, #t~ite3=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 #t~ite4 := #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, #t~ite3=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 ~x~0 := #t~ite4; [L703] 1 havoc #t~ite3; [L703] 1 havoc #t~ite4; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L704] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] 1 ~x$w_buff0_used~0 := #t~ite5; [L704] 1 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L705] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] 1 ~x$w_buff1_used~0 := #t~ite6; [L705] 1 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L731] 0 ~x~0 := #t~ite11; [L731] 0 havoc #t~ite11; [L731] 0 havoc #t~ite10; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L706] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L706] 1 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256; [L732] 0 #t~ite12 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite12=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] 0 ~x$w_buff0_used~0 := #t~ite12; [L732] 0 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L733] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] 0 ~x$w_buff1_used~0 := #t~ite13; [L733] 0 havoc #t~ite13; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L734] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite14=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L734] 0 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L735] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite15=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L735] 0 havoc #t~ite15; [L738] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L707] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L707] 1 havoc #t~ite8; [L710] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L756] -1 havoc main_#t~nondet18; [L758] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L760] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L762] -1 main_#t~ite19 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 main_#t~ite20 := main_#t~ite19; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_#t~ite20=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 ~x~0 := main_#t~ite20; [L762] -1 havoc main_#t~ite19; [L762] -1 havoc main_#t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L763] -1 main_#t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite21=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] -1 ~x$w_buff0_used~0 := main_#t~ite21; [L763] -1 havoc main_#t~ite21; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L764] -1 main_#t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite22=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] -1 ~x$w_buff1_used~0 := main_#t~ite22; [L764] -1 havoc main_#t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L765] -1 main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite23=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] -1 ~x$r_buff0_thd0~0 := main_#t~ite23; [L765] -1 havoc main_#t~ite23; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L766] -1 main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite24=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] -1 ~x$r_buff1_thd0~0 := main_#t~ite24; [L766] -1 havoc main_#t~ite24; [L769] -1 ~weak$$choice0~0 := (if 0 == main_#t~nondet25.base + main_#t~nondet25.offset then 0 else 1); [L769] -1 havoc main_#t~nondet25.base, main_#t~nondet25.offset; [L770] -1 ~weak$$choice2~0 := (if 0 == main_#t~nondet26.base + main_#t~nondet26.offset then 0 else 1); [L770] -1 havoc main_#t~nondet26.base, main_#t~nondet26.offset; [L771] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L772] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] -1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256); [L773] -1 main_#t~ite28 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite28=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] -1 ~x~0 := main_#t~ite28; [L773] -1 havoc main_#t~ite28; [L773] -1 havoc main_#t~ite27; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] -1 assume 0 != ~weak$$choice2~0 % 256; [L774] -1 main_#t~ite31 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite31=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] -1 ~x$w_buff0~0 := main_#t~ite31; [L774] -1 havoc main_#t~ite29; [L774] -1 havoc main_#t~ite31; [L774] -1 havoc main_#t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] -1 assume 0 != ~weak$$choice2~0 % 256; [L775] -1 main_#t~ite34 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite34=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] -1 ~x$w_buff1~0 := main_#t~ite34; [L775] -1 havoc main_#t~ite33; [L775] -1 havoc main_#t~ite32; [L775] -1 havoc main_#t~ite34; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] -1 assume 0 != ~weak$$choice2~0 % 256; [L776] -1 main_#t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite37=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] -1 ~x$w_buff0_used~0 := main_#t~ite37; [L776] -1 havoc main_#t~ite36; [L776] -1 havoc main_#t~ite37; [L776] -1 havoc main_#t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] -1 assume 0 != ~weak$$choice2~0 % 256; [L777] -1 main_#t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] -1 ~x$w_buff1_used~0 := main_#t~ite40; [L777] -1 havoc main_#t~ite39; [L777] -1 havoc main_#t~ite38; [L777] -1 havoc main_#t~ite40; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] -1 assume 0 != ~weak$$choice2~0 % 256; [L778] -1 main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] -1 ~x$r_buff0_thd0~0 := main_#t~ite43; [L778] -1 havoc main_#t~ite42; [L778] -1 havoc main_#t~ite43; [L778] -1 havoc main_#t~ite41; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] -1 assume 0 != ~weak$$choice2~0 % 256; [L779] -1 main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] -1 ~x$r_buff1_thd0~0 := main_#t~ite46; [L779] -1 havoc main_#t~ite44; [L779] -1 havoc main_#t~ite46; [L779] -1 havoc main_#t~ite45; [L780] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 2 == ~y~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] -1 assume 0 != ~x$flush_delayed~0 % 256; [L781] -1 main_#t~ite47 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] -1 ~x~0 := main_#t~ite47; [L781] -1 havoc main_#t~ite47; [L782] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L784] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L784] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L672] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [L673] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L675] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L676] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L677] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L678] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L679] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L681] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L682] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L684] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L685] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L686] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L687] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L688] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L689] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L693] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25, main_#t~nondet26, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t2477~0, main_~#t2478~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L753] FCALL -1 call main_~#t2477~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FCALL -1 call write~int(0, main_~#t2477~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] -1 havoc main_#t~nondet17; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] FCALL -1 call main_~#t2478~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FCALL -1 call write~int(1, main_~#t2478~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L714-L741] 0 ~arg := #in~arg; [L717] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L718] 0 ~x$w_buff0~0 := 2; [L719] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L720] 0 ~x$w_buff0_used~0 := 1; [L721] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L721] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L722] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L723] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L724] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L725] 0 ~x$r_buff0_thd2~0 := 1; [L728] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L731] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L731] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L694-L713] 1 ~arg := #in~arg; [L697] 1 ~y~0 := 2; [L700] 1 ~x~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256) [L703] 1 #t~ite3 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, #t~ite3=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 #t~ite4 := #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, #t~ite3=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 ~x~0 := #t~ite4; [L703] 1 havoc #t~ite3; [L703] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L704] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] 1 ~x$w_buff0_used~0 := #t~ite5; [L704] 1 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L705] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] 1 ~x$w_buff1_used~0 := #t~ite6; [L705] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L731] 0 ~x~0 := #t~ite11; [L731] 0 havoc #t~ite11; [L731] 0 havoc #t~ite10; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L706] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L706] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L732] 0 #t~ite12 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite12=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] 0 ~x$w_buff0_used~0 := #t~ite12; [L732] 0 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L733] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] 0 ~x$w_buff1_used~0 := #t~ite13; [L733] 0 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L734] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite14=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L734] 0 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L735] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite15=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L735] 0 havoc #t~ite15; [L738] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L707] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L707] 1 havoc #t~ite8; [L710] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L756] -1 havoc main_#t~nondet18; [L758] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L760] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L762] -1 main_#t~ite19 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 main_#t~ite20 := main_#t~ite19; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_#t~ite20=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 ~x~0 := main_#t~ite20; [L762] -1 havoc main_#t~ite19; [L762] -1 havoc main_#t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L763] -1 main_#t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite21=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] -1 ~x$w_buff0_used~0 := main_#t~ite21; [L763] -1 havoc main_#t~ite21; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L764] -1 main_#t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite22=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] -1 ~x$w_buff1_used~0 := main_#t~ite22; [L764] -1 havoc main_#t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L765] -1 main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite23=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] -1 ~x$r_buff0_thd0~0 := main_#t~ite23; [L765] -1 havoc main_#t~ite23; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L766] -1 main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite24=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] -1 ~x$r_buff1_thd0~0 := main_#t~ite24; [L766] -1 havoc main_#t~ite24; [L769] -1 ~weak$$choice0~0 := (if 0 == main_#t~nondet25!base + main_#t~nondet25!offset then 0 else 1); [L769] -1 havoc main_#t~nondet25; [L770] -1 ~weak$$choice2~0 := (if 0 == main_#t~nondet26!base + main_#t~nondet26!offset then 0 else 1); [L770] -1 havoc main_#t~nondet26; [L771] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L772] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] COND TRUE -1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256) [L773] -1 main_#t~ite28 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite28=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] -1 ~x~0 := main_#t~ite28; [L773] -1 havoc main_#t~ite28; [L773] -1 havoc main_#t~ite27; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L774] -1 main_#t~ite31 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite31=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] -1 ~x$w_buff0~0 := main_#t~ite31; [L774] -1 havoc main_#t~ite29; [L774] -1 havoc main_#t~ite31; [L774] -1 havoc main_#t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L775] -1 main_#t~ite34 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite34=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] -1 ~x$w_buff1~0 := main_#t~ite34; [L775] -1 havoc main_#t~ite33; [L775] -1 havoc main_#t~ite32; [L775] -1 havoc main_#t~ite34; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L776] -1 main_#t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite37=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] -1 ~x$w_buff0_used~0 := main_#t~ite37; [L776] -1 havoc main_#t~ite36; [L776] -1 havoc main_#t~ite37; [L776] -1 havoc main_#t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L777] -1 main_#t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] -1 ~x$w_buff1_used~0 := main_#t~ite40; [L777] -1 havoc main_#t~ite39; [L777] -1 havoc main_#t~ite38; [L777] -1 havoc main_#t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L778] -1 main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] -1 ~x$r_buff0_thd0~0 := main_#t~ite43; [L778] -1 havoc main_#t~ite42; [L778] -1 havoc main_#t~ite43; [L778] -1 havoc main_#t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L779] -1 main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] -1 ~x$r_buff1_thd0~0 := main_#t~ite46; [L779] -1 havoc main_#t~ite44; [L779] -1 havoc main_#t~ite46; [L779] -1 havoc main_#t~ite45; [L780] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 2 == ~y~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] COND TRUE -1 0 != ~x$flush_delayed~0 % 256 [L781] -1 main_#t~ite47 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] -1 ~x~0 := main_#t~ite47; [L781] -1 havoc main_#t~ite47; [L782] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L784] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L784] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L672] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [L673] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L675] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L676] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L677] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L678] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L679] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L681] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L682] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L684] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L685] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L686] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L687] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L688] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L689] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L693] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25, main_#t~nondet26, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t2477~0, main_~#t2478~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L753] FCALL -1 call main_~#t2477~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FCALL -1 call write~int(0, main_~#t2477~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] -1 havoc main_#t~nondet17; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] FCALL -1 call main_~#t2478~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FCALL -1 call write~int(1, main_~#t2478~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L714-L741] 0 ~arg := #in~arg; [L717] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L718] 0 ~x$w_buff0~0 := 2; [L719] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L720] 0 ~x$w_buff0_used~0 := 1; [L721] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L721] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L722] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L723] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L724] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L725] 0 ~x$r_buff0_thd2~0 := 1; [L728] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L731] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L731] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L694-L713] 1 ~arg := #in~arg; [L697] 1 ~y~0 := 2; [L700] 1 ~x~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256) [L703] 1 #t~ite3 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, #t~ite3=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 #t~ite4 := #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, #t~ite3=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 ~x~0 := #t~ite4; [L703] 1 havoc #t~ite3; [L703] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L704] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] 1 ~x$w_buff0_used~0 := #t~ite5; [L704] 1 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L705] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] 1 ~x$w_buff1_used~0 := #t~ite6; [L705] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L731] 0 ~x~0 := #t~ite11; [L731] 0 havoc #t~ite11; [L731] 0 havoc #t~ite10; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L706] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L706] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L732] 0 #t~ite12 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite12=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] 0 ~x$w_buff0_used~0 := #t~ite12; [L732] 0 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L733] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] 0 ~x$w_buff1_used~0 := #t~ite13; [L733] 0 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L734] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite14=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L734] 0 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L735] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite15=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L735] 0 havoc #t~ite15; [L738] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L707] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L707] 1 havoc #t~ite8; [L710] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L756] -1 havoc main_#t~nondet18; [L758] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L760] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L762] -1 main_#t~ite19 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 main_#t~ite20 := main_#t~ite19; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_#t~ite20=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 ~x~0 := main_#t~ite20; [L762] -1 havoc main_#t~ite19; [L762] -1 havoc main_#t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L763] -1 main_#t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite21=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] -1 ~x$w_buff0_used~0 := main_#t~ite21; [L763] -1 havoc main_#t~ite21; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L764] -1 main_#t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite22=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] -1 ~x$w_buff1_used~0 := main_#t~ite22; [L764] -1 havoc main_#t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L765] -1 main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite23=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] -1 ~x$r_buff0_thd0~0 := main_#t~ite23; [L765] -1 havoc main_#t~ite23; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L766] -1 main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite24=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] -1 ~x$r_buff1_thd0~0 := main_#t~ite24; [L766] -1 havoc main_#t~ite24; [L769] -1 ~weak$$choice0~0 := (if 0 == main_#t~nondet25!base + main_#t~nondet25!offset then 0 else 1); [L769] -1 havoc main_#t~nondet25; [L770] -1 ~weak$$choice2~0 := (if 0 == main_#t~nondet26!base + main_#t~nondet26!offset then 0 else 1); [L770] -1 havoc main_#t~nondet26; [L771] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L772] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] COND TRUE -1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256) [L773] -1 main_#t~ite28 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite28=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] -1 ~x~0 := main_#t~ite28; [L773] -1 havoc main_#t~ite28; [L773] -1 havoc main_#t~ite27; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L774] -1 main_#t~ite31 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite31=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] -1 ~x$w_buff0~0 := main_#t~ite31; [L774] -1 havoc main_#t~ite29; [L774] -1 havoc main_#t~ite31; [L774] -1 havoc main_#t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L775] -1 main_#t~ite34 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite34=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] -1 ~x$w_buff1~0 := main_#t~ite34; [L775] -1 havoc main_#t~ite33; [L775] -1 havoc main_#t~ite32; [L775] -1 havoc main_#t~ite34; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L776] -1 main_#t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite37=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] -1 ~x$w_buff0_used~0 := main_#t~ite37; [L776] -1 havoc main_#t~ite36; [L776] -1 havoc main_#t~ite37; [L776] -1 havoc main_#t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L777] -1 main_#t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] -1 ~x$w_buff1_used~0 := main_#t~ite40; [L777] -1 havoc main_#t~ite39; [L777] -1 havoc main_#t~ite38; [L777] -1 havoc main_#t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L778] -1 main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] -1 ~x$r_buff0_thd0~0 := main_#t~ite43; [L778] -1 havoc main_#t~ite42; [L778] -1 havoc main_#t~ite43; [L778] -1 havoc main_#t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L779] -1 main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] -1 ~x$r_buff1_thd0~0 := main_#t~ite46; [L779] -1 havoc main_#t~ite44; [L779] -1 havoc main_#t~ite46; [L779] -1 havoc main_#t~ite45; [L780] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 2 == ~y~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] COND TRUE -1 0 != ~x$flush_delayed~0 % 256 [L781] -1 main_#t~ite47 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] -1 ~x~0 := main_#t~ite47; [L781] -1 havoc main_#t~ite47; [L782] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L784] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L784] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L672] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [L673] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L675] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L676] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L677] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L678] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L679] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L681] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L682] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L684] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L685] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L686] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L687] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L688] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L689] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L693] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L753] FCALL -1 call ~#t2477~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FCALL -1 call write~int(0, ~#t2477~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] -1 havoc #t~nondet17; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] FCALL -1 call ~#t2478~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FCALL -1 call write~int(1, ~#t2478~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L714-L741] 0 ~arg := #in~arg; [L717] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L718] 0 ~x$w_buff0~0 := 2; [L719] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L720] 0 ~x$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L722] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L723] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L724] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L725] 0 ~x$r_buff0_thd2~0 := 1; [L728] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L731] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L731] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L694-L713] 1 ~arg := #in~arg; [L697] 1 ~y~0 := 2; [L700] 1 ~x~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256) [L703] 1 #t~ite3 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 #t~ite4 := #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, #t~ite4=1, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 ~x~0 := #t~ite4; [L703] 1 havoc #t~ite3; [L703] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L704] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] 1 ~x$w_buff0_used~0 := #t~ite5; [L704] 1 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L705] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] 1 ~x$w_buff1_used~0 := #t~ite6; [L705] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L731] 0 ~x~0 := #t~ite11; [L731] 0 havoc #t~ite11; [L731] 0 havoc #t~ite10; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L706] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L706] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L732] 0 #t~ite12 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] 0 ~x$w_buff0_used~0 := #t~ite12; [L732] 0 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L733] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] 0 ~x$w_buff1_used~0 := #t~ite13; [L733] 0 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L734] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L734] 0 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L735] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L735] 0 havoc #t~ite15; [L738] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L707] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, ~__unbuffered_cnt~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L707] 1 havoc #t~ite8; [L710] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L756] -1 havoc #t~nondet18; [L758] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L760] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L762] -1 #t~ite19 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 #t~ite20 := #t~ite19; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 ~x~0 := #t~ite20; [L762] -1 havoc #t~ite19; [L762] -1 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L763] -1 #t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] -1 ~x$w_buff0_used~0 := #t~ite21; [L763] -1 havoc #t~ite21; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L764] -1 #t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] -1 ~x$w_buff1_used~0 := #t~ite22; [L764] -1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L765] -1 #t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] -1 ~x$r_buff0_thd0~0 := #t~ite23; [L765] -1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L766] -1 #t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] -1 ~x$r_buff1_thd0~0 := #t~ite24; [L766] -1 havoc #t~ite24; [L769] -1 ~weak$$choice0~0 := (if 0 == #t~nondet25!base + #t~nondet25!offset then 0 else 1); [L769] -1 havoc #t~nondet25; [L770] -1 ~weak$$choice2~0 := (if 0 == #t~nondet26!base + #t~nondet26!offset then 0 else 1); [L770] -1 havoc #t~nondet26; [L771] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L772] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] COND TRUE -1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256) [L773] -1 #t~ite28 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] -1 ~x~0 := #t~ite28; [L773] -1 havoc #t~ite28; [L773] -1 havoc #t~ite27; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L774] -1 #t~ite31 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] -1 ~x$w_buff0~0 := #t~ite31; [L774] -1 havoc #t~ite29; [L774] -1 havoc #t~ite31; [L774] -1 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L775] -1 #t~ite34 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] -1 ~x$w_buff1~0 := #t~ite34; [L775] -1 havoc #t~ite33; [L775] -1 havoc #t~ite32; [L775] -1 havoc #t~ite34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L776] -1 #t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] -1 ~x$w_buff0_used~0 := #t~ite37; [L776] -1 havoc #t~ite36; [L776] -1 havoc #t~ite37; [L776] -1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L777] -1 #t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] -1 ~x$w_buff1_used~0 := #t~ite40; [L777] -1 havoc #t~ite39; [L777] -1 havoc #t~ite38; [L777] -1 havoc #t~ite40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L778] -1 #t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] -1 ~x$r_buff0_thd0~0 := #t~ite43; [L778] -1 havoc #t~ite42; [L778] -1 havoc #t~ite43; [L778] -1 havoc #t~ite41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L779] -1 #t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] -1 ~x$r_buff1_thd0~0 := #t~ite46; [L779] -1 havoc #t~ite44; [L779] -1 havoc #t~ite46; [L779] -1 havoc #t~ite45; [L780] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 2 == ~y~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] COND TRUE -1 0 != ~x$flush_delayed~0 % 256 [L781] -1 #t~ite47 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] -1 ~x~0 := #t~ite47; [L781] -1 havoc #t~ite47; [L782] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L672] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [L673] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L675] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L676] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L677] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L678] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L679] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L681] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L682] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L684] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L685] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L686] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L687] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L688] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L689] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L693] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L753] FCALL -1 call ~#t2477~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FCALL -1 call write~int(0, ~#t2477~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] -1 havoc #t~nondet17; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] FCALL -1 call ~#t2478~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FCALL -1 call write~int(1, ~#t2478~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L714-L741] 0 ~arg := #in~arg; [L717] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L718] 0 ~x$w_buff0~0 := 2; [L719] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L720] 0 ~x$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L722] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L723] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L724] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L725] 0 ~x$r_buff0_thd2~0 := 1; [L728] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L731] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L731] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L694-L713] 1 ~arg := #in~arg; [L697] 1 ~y~0 := 2; [L700] 1 ~x~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256) [L703] 1 #t~ite3 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 #t~ite4 := #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, #t~ite4=1, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 ~x~0 := #t~ite4; [L703] 1 havoc #t~ite3; [L703] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L704] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] 1 ~x$w_buff0_used~0 := #t~ite5; [L704] 1 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L705] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] 1 ~x$w_buff1_used~0 := #t~ite6; [L705] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L731] 0 ~x~0 := #t~ite11; [L731] 0 havoc #t~ite11; [L731] 0 havoc #t~ite10; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L706] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L706] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L732] 0 #t~ite12 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] 0 ~x$w_buff0_used~0 := #t~ite12; [L732] 0 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L733] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] 0 ~x$w_buff1_used~0 := #t~ite13; [L733] 0 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L734] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L734] 0 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L735] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L735] 0 havoc #t~ite15; [L738] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L707] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, ~__unbuffered_cnt~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L707] 1 havoc #t~ite8; [L710] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L756] -1 havoc #t~nondet18; [L758] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L760] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L762] -1 #t~ite19 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 #t~ite20 := #t~ite19; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 ~x~0 := #t~ite20; [L762] -1 havoc #t~ite19; [L762] -1 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L763] -1 #t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] -1 ~x$w_buff0_used~0 := #t~ite21; [L763] -1 havoc #t~ite21; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L764] -1 #t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] -1 ~x$w_buff1_used~0 := #t~ite22; [L764] -1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L765] -1 #t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] -1 ~x$r_buff0_thd0~0 := #t~ite23; [L765] -1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L766] -1 #t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] -1 ~x$r_buff1_thd0~0 := #t~ite24; [L766] -1 havoc #t~ite24; [L769] -1 ~weak$$choice0~0 := (if 0 == #t~nondet25!base + #t~nondet25!offset then 0 else 1); [L769] -1 havoc #t~nondet25; [L770] -1 ~weak$$choice2~0 := (if 0 == #t~nondet26!base + #t~nondet26!offset then 0 else 1); [L770] -1 havoc #t~nondet26; [L771] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L772] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] COND TRUE -1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256) [L773] -1 #t~ite28 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] -1 ~x~0 := #t~ite28; [L773] -1 havoc #t~ite28; [L773] -1 havoc #t~ite27; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L774] -1 #t~ite31 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] -1 ~x$w_buff0~0 := #t~ite31; [L774] -1 havoc #t~ite29; [L774] -1 havoc #t~ite31; [L774] -1 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L775] -1 #t~ite34 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] -1 ~x$w_buff1~0 := #t~ite34; [L775] -1 havoc #t~ite33; [L775] -1 havoc #t~ite32; [L775] -1 havoc #t~ite34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L776] -1 #t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] -1 ~x$w_buff0_used~0 := #t~ite37; [L776] -1 havoc #t~ite36; [L776] -1 havoc #t~ite37; [L776] -1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L777] -1 #t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] -1 ~x$w_buff1_used~0 := #t~ite40; [L777] -1 havoc #t~ite39; [L777] -1 havoc #t~ite38; [L777] -1 havoc #t~ite40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L778] -1 #t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] -1 ~x$r_buff0_thd0~0 := #t~ite43; [L778] -1 havoc #t~ite42; [L778] -1 havoc #t~ite43; [L778] -1 havoc #t~ite41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L779] -1 #t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] -1 ~x$r_buff1_thd0~0 := #t~ite46; [L779] -1 havoc #t~ite44; [L779] -1 havoc #t~ite46; [L779] -1 havoc #t~ite45; [L780] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 2 == ~y~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] COND TRUE -1 0 != ~x$flush_delayed~0 % 256 [L781] -1 #t~ite47 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] -1 ~x~0 := #t~ite47; [L781] -1 havoc #t~ite47; [L782] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L672] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0] [L673] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0] [L675] -1 int x = 0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L676] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0] [L677] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0] [L678] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L679] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L680] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L681] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L682] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L683] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L684] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L685] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L686] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L687] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L688] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L689] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L691] -1 int y = 0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L692] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L693] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L753] -1 pthread_t t2477; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L754] FCALL, FORK -1 pthread_create(&t2477, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L755] -1 pthread_t t2478; VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L756] FCALL, FORK -1 pthread_create(&t2478, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L717] 0 x$w_buff1 = x$w_buff0 [L718] 0 x$w_buff0 = 2 [L719] 0 x$w_buff1_used = x$w_buff0_used [L720] 0 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0] [L722] 0 x$r_buff1_thd0 = x$r_buff0_thd0 [L723] 0 x$r_buff1_thd1 = x$r_buff0_thd1 [L724] 0 x$r_buff1_thd2 = x$r_buff0_thd2 [L725] 0 x$r_buff0_thd2 = (_Bool)1 [L728] 0 y = 1 VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L731] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L697] 1 y = 2 [L700] 1 x = 1 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L703] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L703] EXPR 1 x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x=1, y=2] [L703] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x)=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x=1, y=2] [L703] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L704] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L704] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L705] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L705] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L731] 0 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L706] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L706] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L732] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L732] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L733] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L733] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L734] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L734] 0 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L735] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L735] 0 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L738] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L707] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=1, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L707] 1 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L710] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L758] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L762] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L762] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L762] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L762] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L763] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L763] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L764] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L764] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L765] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L765] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L766] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L766] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L769] -1 weak$$choice0 = __VERIFIER_nondet_pointer() [L770] -1 weak$$choice2 = __VERIFIER_nondet_pointer() [L771] -1 x$flush_delayed = weak$$choice2 [L772] -1 x$mem_tmp = x VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L773] EXPR -1 !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L773] -1 x = !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) [L774] EXPR -1 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L774] -1 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) [L775] EXPR -1 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L775] -1 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) [L776] EXPR -1 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L776] -1 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) [L777] EXPR -1 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L777] -1 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L778] EXPR -1 weak$$choice2 ? x$r_buff0_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff0_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L778] -1 x$r_buff0_thd0 = weak$$choice2 ? x$r_buff0_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff0_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0)) [L779] EXPR -1 weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L779] -1 x$r_buff1_thd0 = weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L780] -1 main$tmp_guard1 = !(x == 2 && y == 2) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L781] EXPR -1 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L781] -1 x = x$flush_delayed ? x$mem_tmp : x [L782] -1 x$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] ----- [2018-11-23 03:49:14,579 INFO L305 ceAbstractionStarter]: Did not count any witness invariants because Icfg is not BoogieIcfg [2018-11-23 03:49:14,582 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 03:49:14 BasicIcfg [2018-11-23 03:49:14,582 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 03:49:14,583 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 03:49:14,583 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 03:49:14,583 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 03:49:14,583 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 03:48:58" (3/4) ... [2018-11-23 03:49:14,586 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [474] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [361] L-1-->L671: Formula: (= |v_#valid_5| (store |v_#valid_6| 0 0)) InVars {#valid=|v_#valid_6|} OutVars{#valid=|v_#valid_5|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [514] L671-->L672: Formula: (= v_~__unbuffered_cnt~0_5 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [451] L672-->L673: Formula: (= v_~main$tmp_guard0~0_1 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [?] -1 [384] L673-->L675: Formula: (= v_~main$tmp_guard1~0_3 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [430] L675-->L676: Formula: (= v_~x~0_9 0) InVars {} OutVars{~x~0=v_~x~0_9} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [348] L676-->L677: Formula: (= v_~x$flush_delayed~0_4 0) InVars {} OutVars{~x$flush_delayed~0=v_~x$flush_delayed~0_4} AuxVars[] AssignedVars[~x$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 [485] L677-->L678: Formula: (= v_~x$mem_tmp~0_2 0) InVars {} OutVars{~x$mem_tmp~0=v_~x$mem_tmp~0_2} AuxVars[] AssignedVars[~x$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 [420] L678-->L679: Formula: (= v_~x$r_buff0_thd0~0_16 0) InVars {} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_16} AuxVars[] AssignedVars[~x$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 [522] L679-->L680: Formula: (= v_~x$r_buff0_thd1~0_13 0) InVars {} OutVars{~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_13} AuxVars[] AssignedVars[~x$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 [455] L680-->L681: Formula: (= v_~x$r_buff0_thd2~0_14 0) InVars {} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_14} AuxVars[] AssignedVars[~x$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 [387] L681-->L682: Formula: (= v_~x$r_buff1_thd0~0_10 0) InVars {} OutVars{~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_10} AuxVars[] AssignedVars[~x$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 [513] L682-->L683: Formula: (= v_~x$r_buff1_thd1~0_9 0) InVars {} OutVars{~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_9} AuxVars[] AssignedVars[~x$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 [449] L683-->L684: Formula: (= v_~x$r_buff1_thd2~0_9 0) InVars {} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_9} AuxVars[] AssignedVars[~x$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 [383] L684-->L685: Formula: (= v_~x$read_delayed~0_1 0) InVars {} OutVars{~x$read_delayed~0=v_~x$read_delayed~0_1} AuxVars[] AssignedVars[~x$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 [492] L685-->L686: Formula: (and (= v_~x$read_delayed_var~0.offset_1 0) (= v_~x$read_delayed_var~0.base_1 0)) InVars {} OutVars{~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_1, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~x$read_delayed_var~0.offset, ~x$read_delayed_var~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 [429] L686-->L687: Formula: (= v_~x$w_buff0~0_5 0) InVars {} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_5} AuxVars[] AssignedVars[~x$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 [379] L687-->L688: Formula: (= v_~x$w_buff0_used~0_38 0) InVars {} OutVars{~x$w_buff0_used~0=v_~x$w_buff0_used~0_38} AuxVars[] AssignedVars[~x$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 [484] L688-->L689: Formula: (= v_~x$w_buff1~0_4 0) InVars {} OutVars{~x$w_buff1~0=v_~x$w_buff1~0_4} AuxVars[] AssignedVars[~x$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 [418] L689-->L691: Formula: (= v_~x$w_buff1_used~0_24 0) InVars {} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_24} AuxVars[] AssignedVars[~x$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 [454] L691-->L692: Formula: (= v_~y~0_4 0) InVars {} OutVars{~y~0=v_~y~0_4} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [386] L692-->L693: Formula: (= v_~weak$$choice0~0_1 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_1} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [511] L693-->L-1-1: Formula: (= v_~weak$$choice2~0_7 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_7} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [512] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [509] L-1-2-->L753: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_1|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_1|, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_1|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_5|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_5|, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_1|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_1|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_5|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_1|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_5|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_1|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_5|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_1|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_5|, ULTIMATE.start_main_~#t2478~0.offset=|v_ULTIMATE.start_main_~#t2478~0.offset_3|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_1|, ULTIMATE.start_main_#t~nondet26.base=|v_ULTIMATE.start_main_#t~nondet26.base_1|, ULTIMATE.start_main_#t~nondet25.base=|v_ULTIMATE.start_main_#t~nondet25.base_1|, ULTIMATE.start_main_~#t2477~0.offset=|v_ULTIMATE.start_main_~#t2477~0.offset_3|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_5|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_1|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_2|, ULTIMATE.start_main_~#t2477~0.base=|v_ULTIMATE.start_main_~#t2477~0.base_3|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_2|, ULTIMATE.start_main_#t~nondet26.offset=|v_ULTIMATE.start_main_#t~nondet26.offset_1|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_5|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_3|, ULTIMATE.start_main_#t~nondet25.offset=|v_ULTIMATE.start_main_#t~nondet25.offset_1|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_1|, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_1|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_1|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_1|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_5|, ULTIMATE.start_main_~#t2478~0.base=|v_ULTIMATE.start_main_~#t2478~0.base_3|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_5|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_1|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t2478~0.offset, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~nondet26.base, ULTIMATE.start_main_#t~nondet25.base, ULTIMATE.start_main_~#t2477~0.offset, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_~#t2477~0.base, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~nondet26.offset, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~nondet25.offset, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_~#t2478~0.base, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~nondet17, ULTIMATE.start_main_#t~nondet18] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [368] L753-->L753-1: Formula: (and (= (store |v_#valid_8| |v_ULTIMATE.start_main_~#t2477~0.base_4| 1) |v_#valid_7|) (not (= 0 |v_ULTIMATE.start_main_~#t2477~0.base_4|)) (= 0 (select |v_#valid_8| |v_ULTIMATE.start_main_~#t2477~0.base_4|)) (= |v_#length_1| (store |v_#length_2| |v_ULTIMATE.start_main_~#t2477~0.base_4| 4)) (= 0 |v_ULTIMATE.start_main_~#t2477~0.offset_4|)) InVars {#length=|v_#length_2|, #valid=|v_#valid_8|} OutVars{ULTIMATE.start_main_~#t2477~0.base=|v_ULTIMATE.start_main_~#t2477~0.base_4|, ULTIMATE.start_main_~#t2477~0.offset=|v_ULTIMATE.start_main_~#t2477~0.offset_4|, #length=|v_#length_1|, #valid=|v_#valid_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2477~0.offset, #valid, ULTIMATE.start_main_~#t2477~0.base, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [373] L753-1-->L754: Formula: (= (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t2477~0.base_5| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t2477~0.base_5|) |v_ULTIMATE.start_main_~#t2477~0.offset_5| 0)) |v_#memory_int_1|) InVars {#memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t2477~0.base=|v_ULTIMATE.start_main_~#t2477~0.base_5|, ULTIMATE.start_main_~#t2477~0.offset=|v_ULTIMATE.start_main_~#t2477~0.offset_5|} OutVars{#memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t2477~0.base=|v_ULTIMATE.start_main_~#t2477~0.base_5|, ULTIMATE.start_main_~#t2477~0.offset=|v_ULTIMATE.start_main_~#t2477~0.offset_5|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 [575] L754-->P0ENTRY: Formula: (and (= 0 |v_Thread0_P0_#in~arg.offset_3|) (= 0 v_Thread0_P0_thidvar0_2) (= 0 |v_Thread0_P0_#in~arg.base_3|)) InVars {} OutVars{Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_3|, Thread0_P0_thidvar0=v_Thread0_P0_thidvar0_2, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P0_#in~arg.base, Thread0_P0_thidvar0, Thread0_P0_#in~arg.offset] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [480] L754-1-->L755: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [412] L755-->L755-1: Formula: (and (= (store |v_#length_4| |v_ULTIMATE.start_main_~#t2478~0.base_4| 4) |v_#length_3|) (= 0 (select |v_#valid_10| |v_ULTIMATE.start_main_~#t2478~0.base_4|)) (= 0 |v_ULTIMATE.start_main_~#t2478~0.offset_4|) (not (= 0 |v_ULTIMATE.start_main_~#t2478~0.base_4|)) (= |v_#valid_9| (store |v_#valid_10| |v_ULTIMATE.start_main_~#t2478~0.base_4| 1))) InVars {#length=|v_#length_4|, #valid=|v_#valid_10|} OutVars{ULTIMATE.start_main_~#t2478~0.offset=|v_ULTIMATE.start_main_~#t2478~0.offset_4|, ULTIMATE.start_main_~#t2478~0.base=|v_ULTIMATE.start_main_~#t2478~0.base_4|, #length=|v_#length_3|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2478~0.offset, ULTIMATE.start_main_~#t2478~0.base, #valid, #length] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [414] L755-1-->L756: Formula: (= |v_#memory_int_3| (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t2478~0.base_5| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t2478~0.base_5|) |v_ULTIMATE.start_main_~#t2478~0.offset_5| 1))) InVars {#memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t2478~0.offset=|v_ULTIMATE.start_main_~#t2478~0.offset_5|, ULTIMATE.start_main_~#t2478~0.base=|v_ULTIMATE.start_main_~#t2478~0.base_5|} OutVars{#memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t2478~0.offset=|v_ULTIMATE.start_main_~#t2478~0.offset_5|, ULTIMATE.start_main_~#t2478~0.base=|v_ULTIMATE.start_main_~#t2478~0.base_5|} AuxVars[] AssignedVars[#memory_int] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 [576] L756-->P1ENTRY: Formula: (and (= 0 |v_Thread1_P1_#in~arg.base_3|) (= 0 |v_Thread1_P1_#in~arg.offset_3|) (= 1 v_Thread1_P1_thidvar0_2)) InVars {} OutVars{Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_3|, Thread1_P1_thidvar0=v_Thread1_P1_thidvar0_2, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread1_P1_#in~arg.base, Thread1_P1_thidvar0, Thread1_P1_#in~arg.offset] VAL [Thread0_P0_thidvar0=0, Thread1_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [548] P1ENTRY-->L4: Formula: (and (= v_Thread1_P1_~arg.offset_1 |v_Thread1_P1_#in~arg.offset_1|) (= v_~x$w_buff0~0_2 2) (= v_Thread1_P1_~arg.base_1 |v_Thread1_P1_#in~arg.base_1|) (= v_Thread1_P1___VERIFIER_assert_~expression_1 |v_Thread1_P1___VERIFIER_assert_#in~expression_1|) (= v_~x$w_buff1~0_3 v_~x$w_buff0~0_3) (= v_~x$w_buff1_used~0_15 v_~x$w_buff0_used~0_22) (= v_~x$w_buff0_used~0_21 1) (= |v_Thread1_P1___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= 0 (mod v_~x$w_buff0_used~0_21 256))) (not (= 0 (mod v_~x$w_buff1_used~0_15 256))))) 1 0))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_3, Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_22} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_2, Thread1_P1___VERIFIER_assert_~expression=v_Thread1_P1___VERIFIER_assert_~expression_1, Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_~arg.offset=v_Thread1_P1_~arg.offset_1, Thread1_P1_~arg.base=v_Thread1_P1_~arg.base_1, ~x$w_buff1~0=v_~x$w_buff1~0_3, Thread1_P1___VERIFIER_assert_#in~expression=|v_Thread1_P1___VERIFIER_assert_#in~expression_1|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_15, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_21} AuxVars[] AssignedVars[~x$w_buff0~0, Thread1_P1___VERIFIER_assert_~expression, Thread1_P1_~arg.offset, Thread1_P1_~arg.base, ~x$w_buff1~0, Thread1_P1___VERIFIER_assert_#in~expression, ~x$w_buff1_used~0, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [550] L4-->L4-3: Formula: (not (= v_Thread1_P1___VERIFIER_assert_~expression_3 0)) InVars {Thread1_P1___VERIFIER_assert_~expression=v_Thread1_P1___VERIFIER_assert_~expression_3} OutVars{Thread1_P1___VERIFIER_assert_~expression=v_Thread1_P1___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [553] L4-3-->L731: Formula: (and (= v_~x$r_buff1_thd2~0_8 v_~x$r_buff0_thd2~0_11) (= v_~x$r_buff1_thd0~0_1 v_~x$r_buff0_thd0~0_1) (= v_~x$r_buff0_thd2~0_10 1) (= v_~x$r_buff1_thd1~0_8 v_~x$r_buff0_thd1~0_12) (= v_~y~0_2 1)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_12, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_11} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_12, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_8, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_8, ~y~0=v_~y~0_2, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_10, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_1} AuxVars[] AssignedVars[~x$r_buff1_thd2~0, ~x$r_buff1_thd1~0, ~y~0, ~x$r_buff0_thd2~0, ~x$r_buff1_thd0~0] VAL [Thread0_P0_thidvar0=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 0 [554] L731-->L731-5: Formula: (and (not (= 0 (mod v_~x$r_buff0_thd2~0_12 256))) (= |v_Thread1_P1_#t~ite11_1| v_~x$w_buff0~0_4) (not (= 0 (mod v_~x$w_buff0_used~0_23 256)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_4, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_12, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_23} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_4, Thread1_P1_#t~ite11=|v_Thread1_P1_#t~ite11_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_12, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_23} AuxVars[] AssignedVars[Thread1_P1_#t~ite11] VAL [Thread0_P0_thidvar0=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 1 [526] P0ENTRY-->L703: Formula: (and (= v_Thread0_P0_~arg.base_1 |v_Thread0_P0_#in~arg.base_1|) (= v_Thread0_P0_~arg.offset_1 |v_Thread0_P0_#in~arg.offset_1|) (= v_~y~0_1 2) (= v_~x~0_1 1)) InVars {Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|} OutVars{Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_~arg.offset=v_Thread0_P0_~arg.offset_1, Thread0_P0_~arg.base=v_Thread0_P0_~arg.base_1, ~y~0=v_~y~0_1, ~x~0=v_~x~0_1, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|} AuxVars[] AssignedVars[Thread0_P0_~arg.offset, Thread0_P0_~arg.base, ~y~0, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [528] L703-->L703-2: Formula: (or (= 0 (mod v_~x$r_buff0_thd1~0_4 256)) (= 0 (mod v_~x$w_buff0_used~0_3 256))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} OutVars{~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [531] L703-2-->L703-4: Formula: (and (or (= 0 (mod v_~x$w_buff1_used~0_4 256)) (= (mod v_~x$r_buff1_thd1~0_4 256) 0)) (= |v_Thread0_P0_#t~ite3_3| v_~x~0_2)) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_4, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_4, ~x~0=v_~x~0_2} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_4, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_4, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_3|, ~x~0=v_~x~0_2} AuxVars[] AssignedVars[Thread0_P0_#t~ite3] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite3|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [534] L703-4-->L703-5: Formula: (= |v_Thread0_P0_#t~ite4_4| |v_Thread0_P0_#t~ite3_4|) InVars {Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_4|} OutVars{Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_4|, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_4|} AuxVars[] AssignedVars[Thread0_P0_#t~ite4] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite3|=1, |Thread0_P0_#t~ite4|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [529] L703-5-->L704: Formula: (= v_~x~0_3 |v_Thread0_P0_#t~ite4_2|) InVars {Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_2|} OutVars{Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_3|, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_1|, ~x~0=v_~x~0_3} AuxVars[] AssignedVars[Thread0_P0_#t~ite4, Thread0_P0_#t~ite3, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [533] L704-->L704-2: Formula: (and (= |v_Thread0_P0_#t~ite5_2| v_~x$w_buff0_used~0_7) (or (= 0 (mod v_~x$w_buff0_used~0_7 256)) (= (mod v_~x$r_buff0_thd1~0_8 256) 0))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_7} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_2|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_7} AuxVars[] AssignedVars[Thread0_P0_#t~ite5] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite5|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [535] L704-2-->L705: Formula: (= v_~x$w_buff0_used~0_8 |v_Thread0_P0_#t~ite5_3|) InVars {Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_3|} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_8} AuxVars[] AssignedVars[Thread0_P0_#t~ite5, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [537] L705-->L705-2: Formula: (and (= |v_Thread0_P0_#t~ite6_2| v_~x$w_buff1_used~0_6) (or (= (mod v_~x$w_buff0_used~0_10 256) 0) (= (mod v_~x$r_buff0_thd1~0_10 256) 0)) (or (= 0 (mod v_~x$w_buff1_used~0_6 256)) (= (mod v_~x$r_buff1_thd1~0_7 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_6, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_10} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_6, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_10} AuxVars[] AssignedVars[Thread0_P0_#t~ite6] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite6|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 [538] L705-2-->L706: Formula: (= v_~x$w_buff1_used~0_7 |v_Thread0_P0_#t~ite6_3|) InVars {Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_3|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_7, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, Thread0_P0_#t~ite6] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 0 [556] L731-5-->L732: Formula: (= v_~x~0_5 |v_Thread1_P1_#t~ite11_2|) InVars {Thread1_P1_#t~ite11=|v_Thread1_P1_#t~ite11_2|} OutVars{Thread1_P1_#t~ite11=|v_Thread1_P1_#t~ite11_3|, ~x~0=v_~x~0_5, Thread1_P1_#t~ite10=|v_Thread1_P1_#t~ite10_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite10, Thread1_P1_#t~ite11, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 [540] L706-->L706-2: Formula: (and (= |v_Thread0_P0_#t~ite7_2| v_~x$r_buff0_thd1~0_1) (or (= (mod v_~x$w_buff0_used~0_1 256) 0) (= 0 (mod v_~x$r_buff0_thd1~0_1 256)))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_1} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_2|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_1} AuxVars[] AssignedVars[Thread0_P0_#t~ite7] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite7|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 [541] L706-2-->L707: Formula: (= v_~x$r_buff0_thd1~0_3 |v_Thread0_P0_#t~ite7_3|) InVars {Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_3|} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_4|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_3} AuxVars[] AssignedVars[~x$r_buff0_thd1~0, Thread0_P0_#t~ite7] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 [559] L732-->L732-2: Formula: (and (not (= (mod v_~x$w_buff0_used~0_12 256) 0)) (= |v_Thread1_P1_#t~ite12_1| 0) (not (= (mod v_~x$r_buff0_thd2~0_1 256) 0))) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_12} OutVars{Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_12} AuxVars[] AssignedVars[Thread1_P1_#t~ite12] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite12|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 [562] L732-2-->L733: Formula: (= v_~x$w_buff0_used~0_14 |v_Thread1_P1_#t~ite12_3|) InVars {Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_3|} OutVars{Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_14} AuxVars[] AssignedVars[Thread1_P1_#t~ite12, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 [564] L733-->L733-2: Formula: (and (= |v_Thread1_P1_#t~ite13_2| v_~x$w_buff1_used~0_11) (or (= 0 (mod v_~x$w_buff1_used~0_11 256)) (= 0 (mod v_~x$r_buff1_thd2~0_4 256))) (or (= (mod v_~x$r_buff0_thd2~0_4 256) 0) (= (mod v_~x$w_buff0_used~0_16 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_11, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_4, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_16} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_11, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_4, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_16} AuxVars[] AssignedVars[Thread1_P1_#t~ite13] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite13|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 [565] L733-2-->L734: Formula: (= v_~x$w_buff1_used~0_12 |v_Thread1_P1_#t~ite13_3|) InVars {Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_3|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_12, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, Thread1_P1_#t~ite13] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 [567] L734-->L734-2: Formula: (and (or (= (mod v_~x$r_buff0_thd2~0_6 256) 0) (= 0 (mod v_~x$w_buff0_used~0_18 256))) (= |v_Thread1_P1_#t~ite14_2| v_~x$r_buff0_thd2~0_6)) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_18} OutVars{Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_18} AuxVars[] AssignedVars[Thread1_P1_#t~ite14] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite14|=1, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 [568] L734-2-->L735: Formula: (= v_~x$r_buff0_thd2~0_7 |v_Thread1_P1_#t~ite14_3|) InVars {Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_3|} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_7, Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_4|} AuxVars[] AssignedVars[Thread1_P1_#t~ite14, ~x$r_buff0_thd2~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 [570] L735-->L735-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_20 256) 0) (= (mod v_~x$r_buff0_thd2~0_9 256) 0)) (= |v_Thread1_P1_#t~ite15_2| v_~x$r_buff1_thd2~0_6) (or (= 0 (mod v_~x$r_buff1_thd2~0_6 256)) (= 0 (mod v_~x$w_buff1_used~0_14 256)))) InVars {~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_14, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_9, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_20} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_14, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_9, Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_20} AuxVars[] AssignedVars[Thread1_P1_#t~ite15] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite15|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 [571] L735-2-->L740: Formula: (and (= v_~x$r_buff1_thd2~0_7 |v_Thread1_P1_#t~ite15_3|) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_7, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_4|} AuxVars[] AssignedVars[~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, Thread1_P1_#t~ite15] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 [543] L707-->L707-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_5 256) 0) (= 0 (mod v_~x$r_buff0_thd1~0_6 256))) (or (= (mod v_~x$r_buff1_thd1~0_3 256) 0) (= (mod v_~x$w_buff1_used~0_3 256) 0)) (= |v_Thread0_P0_#t~ite8_2| v_~x$r_buff1_thd1~0_3)) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_3, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_6, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_3, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_3, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_6, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_3, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} AuxVars[] AssignedVars[Thread0_P0_#t~ite8] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite8|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 [544] L707-2-->L712: Formula: (and (= v_~x$r_buff1_thd1~0_5 |v_Thread0_P0_#t~ite8_3|) (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1))) InVars {Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_5, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_4|} AuxVars[] AssignedVars[~__unbuffered_cnt~0, ~x$r_buff1_thd1~0, Thread0_P0_#t~ite8] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [518] L756-1-->L760: Formula: (= v_~main$tmp_guard0~0_2 (ite (= (ite (= v_~__unbuffered_cnt~0_6 2) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_2, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_2|} AuxVars[] AssignedVars[~main$tmp_guard0~0, ULTIMATE.start_main_#t~nondet18] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [448] L760-->L762: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_3 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [502] L762-->L762-2: Formula: (or (= 0 (mod v_~x$w_buff0_used~0_40 256)) (= 0 (mod v_~x$r_buff0_thd0~0_18 256))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_18, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_40} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_18, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_40} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [491] L762-2-->L762-4: Formula: (and (or (= (mod v_~x$w_buff1_used~0_26 256) 0) (= 0 (mod v_~x$r_buff1_thd0~0_12 256))) (= |v_ULTIMATE.start_main_#t~ite19_3| v_~x~0_10)) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_26, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_12, ~x~0=v_~x~0_10} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_26, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_12, ~x~0=v_~x~0_10, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [495] L762-4-->L762-5: Formula: (= |v_ULTIMATE.start_main_#t~ite20_3| |v_ULTIMATE.start_main_#t~ite19_4|) InVars {ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_4|} OutVars{ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_3|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_#t~ite20|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [497] L762-5-->L763: Formula: (= v_~x~0_11 |v_ULTIMATE.start_main_#t~ite20_5|) InVars {ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_5|} OutVars{ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_4|, ~x~0=v_~x~0_11, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite20, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [442] L763-->L763-2: Formula: (and (or (= 0 (mod v_~x$r_buff0_thd0~0_20 256)) (= (mod v_~x$w_buff0_used~0_42 256) 0)) (= |v_ULTIMATE.start_main_#t~ite21_3| v_~x$w_buff0_used~0_42)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_20, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_42} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_20, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_42} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite21|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [426] L763-2-->L764: Formula: (= v_~x$w_buff0_used~0_43 |v_ULTIMATE.start_main_#t~ite21_5|) InVars {ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_5|} OutVars{ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_43} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [367] L764-->L764-2: Formula: (and (or (= 0 (mod v_~x$r_buff1_thd0~0_14 256)) (= 0 (mod v_~x$w_buff1_used~0_28 256))) (or (= (mod v_~x$w_buff0_used~0_45 256) 0) (= 0 (mod v_~x$r_buff0_thd0~0_22 256))) (= |v_ULTIMATE.start_main_#t~ite22_3| v_~x$w_buff1_used~0_28)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_22, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_28, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_14, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_45} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_22, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_28, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_14, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_45} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite22|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [376] L764-2-->L765: Formula: (= v_~x$w_buff1_used~0_29 |v_ULTIMATE.start_main_#t~ite22_5|) InVars {ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_5|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_29, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite22] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [478] L765-->L765-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_47 256) 0) (= 0 (mod v_~x$r_buff0_thd0~0_24 256))) (= |v_ULTIMATE.start_main_#t~ite23_3| v_~x$r_buff0_thd0~0_24)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_24, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_47} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_24, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_47} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite23|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [483] L765-2-->L766: Formula: (= v_~x$r_buff0_thd0~0_25 |v_ULTIMATE.start_main_#t~ite23_5|) InVars {ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_5|} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_25, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_4|} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite23] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [410] L766-->L766-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite24_3| v_~x$r_buff1_thd0~0_16) (or (= (mod v_~x$w_buff1_used~0_31 256) 0) (= (mod v_~x$r_buff1_thd0~0_16 256) 0)) (or (= (mod v_~x$w_buff0_used~0_49 256) 0) (= (mod v_~x$r_buff0_thd0~0_27 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_27, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_31, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_16, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_49} OutVars{ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_3|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_27, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_31, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_16, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_49} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite24|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [417] L766-2-->L773: Formula: (and (= v_~weak$$choice2~0_8 (ite (= 0 (+ |v_ULTIMATE.start_main_#t~nondet26.base_3| |v_ULTIMATE.start_main_#t~nondet26.offset_3|)) 0 1)) (= v_~x$r_buff1_thd0~0_17 |v_ULTIMATE.start_main_#t~ite24_5|) (= v_~x$flush_delayed~0_5 v_~weak$$choice2~0_8) (= v_~weak$$choice0~0_2 (ite (= 0 (+ |v_ULTIMATE.start_main_#t~nondet25.base_3| |v_ULTIMATE.start_main_#t~nondet25.offset_3|)) 0 1)) (= v_~x$mem_tmp~0_3 v_~x~0_12)) InVars {ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_5|, ULTIMATE.start_main_#t~nondet26.base=|v_ULTIMATE.start_main_#t~nondet26.base_3|, ULTIMATE.start_main_#t~nondet26.offset=|v_ULTIMATE.start_main_#t~nondet26.offset_3|, ULTIMATE.start_main_#t~nondet25.base=|v_ULTIMATE.start_main_#t~nondet25.base_3|, ULTIMATE.start_main_#t~nondet25.offset=|v_ULTIMATE.start_main_#t~nondet25.offset_3|, ~x~0=v_~x~0_12} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_2, ~x$flush_delayed~0=v_~x$flush_delayed~0_5, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_4|, ULTIMATE.start_main_#t~nondet26.base=|v_ULTIMATE.start_main_#t~nondet26.base_2|, ULTIMATE.start_main_#t~nondet26.offset=|v_ULTIMATE.start_main_#t~nondet26.offset_2|, ~x$mem_tmp~0=v_~x$mem_tmp~0_3, ULTIMATE.start_main_#t~nondet25.base=|v_ULTIMATE.start_main_#t~nondet25.base_2|, ~weak$$choice2~0=v_~weak$$choice2~0_8, ULTIMATE.start_main_#t~nondet25.offset=|v_ULTIMATE.start_main_#t~nondet25.offset_2|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_17, ~x~0=v_~x~0_12} AuxVars[] AssignedVars[~weak$$choice0~0, ~x$flush_delayed~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~nondet26.base, ULTIMATE.start_main_#t~nondet26.offset, ~x$mem_tmp~0, ULTIMATE.start_main_#t~nondet25.base, ~weak$$choice2~0, ULTIMATE.start_main_#t~nondet25.offset, ~x$r_buff1_thd0~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [499] L773-->L773-5: Formula: (and (= |v_ULTIMATE.start_main_#t~ite28_2| v_~x~0_13) (let ((.cse0 (= (mod v_~x$r_buff0_thd0~0_28 256) 0))) (or (and (= (mod v_~x$r_buff1_thd0~0_18 256) 0) .cse0) (and (= (mod v_~x$w_buff1_used~0_32 256) 0) .cse0) (= (mod v_~x$w_buff0_used~0_50 256) 0)))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_28, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_32, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_18, ~x~0=v_~x~0_13, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_50} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_28, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_2|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_32, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_18, ~x~0=v_~x~0_13, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_50} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite28|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [496] L773-5-->L774: Formula: (= v_~x~0_14 |v_ULTIMATE.start_main_#t~ite28_5|) InVars {ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_5|} OutVars{ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_5|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_4|, ~x~0=v_~x~0_14} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite27, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [437] L774-->L774-8: Formula: (and (= |v_ULTIMATE.start_main_#t~ite31_2| v_~x$w_buff0~0_8) (not (= (mod v_~weak$$choice2~0_9 256) 0))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_8, ~weak$$choice2~0=v_~weak$$choice2~0_9} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_8, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_2|, ~weak$$choice2~0=v_~weak$$choice2~0_9} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite31] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite31|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [411] L774-8-->L775: Formula: (= v_~x$w_buff0~0_12 |v_ULTIMATE.start_main_#t~ite31_5|) InVars {ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_5|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_12, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_5|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_4|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_5|} AuxVars[] AssignedVars[~x$w_buff0~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite31] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [364] L775-->L775-8: Formula: (and (not (= (mod v_~weak$$choice2~0_11 256) 0)) (= |v_ULTIMATE.start_main_#t~ite34_2| v_~x$w_buff1~0_7)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_11, ~x$w_buff1~0=v_~x$w_buff1~0_7} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_11, ~x$w_buff1~0=v_~x$w_buff1~0_7, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite34] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite34|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [360] L775-8-->L776: Formula: (= v_~x$w_buff1~0_11 |v_ULTIMATE.start_main_#t~ite34_5|) InVars {ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_5|} OutVars{ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_5|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_5|, ~x$w_buff1~0=v_~x$w_buff1~0_11, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_4|} AuxVars[] AssignedVars[~x$w_buff1~0, ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_#t~ite34] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [475] L776-->L776-8: Formula: (and (= |v_ULTIMATE.start_main_#t~ite37_4| v_~x$w_buff0_used~0_62) (not (= (mod v_~weak$$choice2~0_13 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_13, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_62} OutVars{ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_4|, ~weak$$choice2~0=v_~weak$$choice2~0_13, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_62} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite37] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite37|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [472] L776-8-->L777: Formula: (= v_~x$w_buff0_used~0_25 |v_ULTIMATE.start_main_#t~ite37_2|) InVars {ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_2|} OutVars{ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_1|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_1|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_25} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite37, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [407] L777-->L777-8: Formula: (and (= |v_ULTIMATE.start_main_#t~ite40_1| v_~x$w_buff1_used~0_16) (not (= (mod v_~weak$$choice2~0_1 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_1, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_16} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_16, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_1|, ~weak$$choice2~0=v_~weak$$choice2~0_1} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [402] L777-8-->L778: Formula: (= v_~x$w_buff1_used~0_19 |v_ULTIMATE.start_main_#t~ite40_4|) InVars {ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_4|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_19, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_4|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_3|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39, ~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite38] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [358] L778-->L778-8: Formula: (and (= |v_ULTIMATE.start_main_#t~ite43_1| v_~x$r_buff0_thd0~0_6) (not (= 0 (mod v_~weak$$choice2~0_3 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_3, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_1|, ~weak$$choice2~0=v_~weak$$choice2~0_3} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [508] L778-8-->L779: Formula: (= v_~x$r_buff0_thd0~0_11 |v_ULTIMATE.start_main_#t~ite43_4|) InVars {ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_4|} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_11, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_4|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_3|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [470] L779-->L779-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_5 256))) (= |v_ULTIMATE.start_main_#t~ite46_1| v_~x$r_buff1_thd0~0_6)) InVars {~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ~weak$$choice2~0=v_~weak$$choice2~0_5} OutVars{ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_1|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ~weak$$choice2~0=v_~weak$$choice2~0_5} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [447] L779-8-->L781: Formula: (and (= v_~x$r_buff1_thd0~0_9 |v_ULTIMATE.start_main_#t~ite46_4|) (= v_~main$tmp_guard1~0_1 (ite (= 0 (ite (not (and (= 2 v_~y~0_3) (= 2 v_~x~0_6))) 1 0)) 0 1))) InVars {ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_4|, ~y~0=v_~y~0_3, ~x~0=v_~x~0_6} OutVars{ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_3|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_1, ~y~0=v_~y~0_3, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_9, ~x~0=v_~x~0_6, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_4|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ~x$r_buff1_thd0~0, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [506] L781-->L781-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite47_1| v_~x$mem_tmp~0_1) (not (= 0 (mod v_~x$flush_delayed~0_1 256)))) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_1, ~x$mem_tmp~0=v_~x$mem_tmp~0_1} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_1|, ~x$mem_tmp~0=v_~x$mem_tmp~0_1, ~x$flush_delayed~0=v_~x$flush_delayed~0_1} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite47|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [510] L781-2-->L784: Formula: (and (= v_~x~0_8 |v_ULTIMATE.start_main_#t~ite47_4|) (= v_~x$flush_delayed~0_3 0)) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_4|} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_3|, ~x$flush_delayed~0=v_~x$flush_delayed~0_3, ~x~0=v_~x~0_8} AuxVars[] AssignedVars[~x$flush_delayed~0, ULTIMATE.start_main_#t~ite47, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [498] L784-->L784-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_2 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_2} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [503] L784-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [397] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [395] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 [391] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25.base, main_#t~nondet25.offset, main_#t~nondet26.base, main_#t~nondet26.offset, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t2477~0.base, main_~#t2477~0.offset, main_~#t2478~0.base, main_~#t2478~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t2477~0.base, main_~#t2477~0.offset := #Ultimate.alloc(4); srcloc: L753 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t2477~0.base, main_~#t2477~0.offset, 4); srcloc: L753-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t2478~0.base, main_~#t2478~0.offset := #Ultimate.alloc(4); srcloc: L755 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t2478~0.base, main_~#t2478~0.offset, 4); srcloc: L755-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 2;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd2~0 := 1;~y~0 := 1; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256;#t~ite11 := ~x$w_buff0~0; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 2;~x~0 := 1; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256);#t~ite3 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite3|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 #t~ite4 := #t~ite3; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite3|=1, |P0_#t~ite4|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 ~x~0 := #t~ite4;havoc #t~ite3;havoc #t~ite4; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite5 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 ~x$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite6 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 ~x$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 0 ~x~0 := #t~ite11;havoc #t~ite11;havoc #t~ite10; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite7 := ~x$r_buff0_thd1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 ~x$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256;#t~ite12 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite12|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 ~x$w_buff0_used~0 := #t~ite12;havoc #t~ite12; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite13 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 ~x$w_buff1_used~0 := #t~ite13;havoc #t~ite13; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite14 := ~x$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite14|=1, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 ~x$r_buff0_thd2~0 := #t~ite14;havoc #t~ite14; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite15 := ~x$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite15|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 ~x$r_buff1_thd2~0 := #t~ite15;havoc #t~ite15;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite8 := ~x$r_buff1_thd1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 ~x$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 havoc main_#t~nondet18;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);main_#t~ite19 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 main_#t~ite20 := main_#t~ite19; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_#t~ite20|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x~0 := main_#t~ite20;havoc main_#t~ite19;havoc main_#t~ite20; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite21 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite21|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff0_used~0 := main_#t~ite21;havoc main_#t~ite21; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite22 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite22|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff1_used~0 := main_#t~ite22;havoc main_#t~ite22; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite23|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite23;havoc main_#t~ite23; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite24|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite24;havoc main_#t~ite24;~weak$$choice0~0 := (if 0 == main_#t~nondet25.base + main_#t~nondet25.offset then 0 else 1);havoc main_#t~nondet25.base, main_#t~nondet25.offset;~weak$$choice2~0 := (if 0 == main_#t~nondet26.base + main_#t~nondet26.offset then 0 else 1);havoc main_#t~nondet26.base, main_#t~nondet26.offset;~x$flush_delayed~0 := ~weak$$choice2~0;~x$mem_tmp~0 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256);main_#t~ite28 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite28|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x~0 := main_#t~ite28;havoc main_#t~ite28;havoc main_#t~ite27; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite31 := ~x$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite31|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff0~0 := main_#t~ite31;havoc main_#t~ite29;havoc main_#t~ite31;havoc main_#t~ite30; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite34 := ~x$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite34|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff1~0 := main_#t~ite34;havoc main_#t~ite33;havoc main_#t~ite32;havoc main_#t~ite34; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite37 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite37|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff0_used~0 := main_#t~ite37;havoc main_#t~ite36;havoc main_#t~ite37;havoc main_#t~ite35; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite40 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff1_used~0 := main_#t~ite40;havoc main_#t~ite39;havoc main_#t~ite38;havoc main_#t~ite40; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite43;havoc main_#t~ite41; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite46;havoc main_#t~ite44;havoc main_#t~ite46;havoc main_#t~ite45;~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 2 == ~y~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~x$flush_delayed~0 % 256;main_#t~ite47 := ~x$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite47|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x~0 := main_#t~ite47;havoc main_#t~ite47;~x$flush_delayed~0 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25.base, main_#t~nondet25.offset, main_#t~nondet26.base, main_#t~nondet26.offset, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t2477~0.base, main_~#t2477~0.offset, main_~#t2478~0.base, main_~#t2478~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t2477~0.base, main_~#t2477~0.offset := #Ultimate.alloc(4); srcloc: L753 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t2477~0.base, main_~#t2477~0.offset, 4); srcloc: L753-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t2478~0.base, main_~#t2478~0.offset := #Ultimate.alloc(4); srcloc: L755 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t2478~0.base, main_~#t2478~0.offset, 4); srcloc: L755-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 2;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd2~0 := 1;~y~0 := 1; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256;#t~ite11 := ~x$w_buff0~0; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 2;~x~0 := 1; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256);#t~ite3 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite3|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 #t~ite4 := #t~ite3; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite3|=1, |P0_#t~ite4|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 ~x~0 := #t~ite4;havoc #t~ite3;havoc #t~ite4; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite5 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 ~x$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite6 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 1 ~x$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [?] 0 ~x~0 := #t~ite11;havoc #t~ite11;havoc #t~ite10; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite7 := ~x$r_buff0_thd1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 ~x$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256;#t~ite12 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite12|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 ~x$w_buff0_used~0 := #t~ite12;havoc #t~ite12; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite13 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 ~x$w_buff1_used~0 := #t~ite13;havoc #t~ite13; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite14 := ~x$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite14|=1, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 ~x$r_buff0_thd2~0 := #t~ite14;havoc #t~ite14; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite15 := ~x$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite15|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 0 ~x$r_buff1_thd2~0 := #t~ite15;havoc #t~ite15;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite8 := ~x$r_buff1_thd1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] 1 ~x$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 havoc main_#t~nondet18;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);main_#t~ite19 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 main_#t~ite20 := main_#t~ite19; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_#t~ite20|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x~0 := main_#t~ite20;havoc main_#t~ite19;havoc main_#t~ite20; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite21 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite21|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff0_used~0 := main_#t~ite21;havoc main_#t~ite21; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite22 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite22|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff1_used~0 := main_#t~ite22;havoc main_#t~ite22; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite23|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite23;havoc main_#t~ite23; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite24|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite24;havoc main_#t~ite24;~weak$$choice0~0 := (if 0 == main_#t~nondet25.base + main_#t~nondet25.offset then 0 else 1);havoc main_#t~nondet25.base, main_#t~nondet25.offset;~weak$$choice2~0 := (if 0 == main_#t~nondet26.base + main_#t~nondet26.offset then 0 else 1);havoc main_#t~nondet26.base, main_#t~nondet26.offset;~x$flush_delayed~0 := ~weak$$choice2~0;~x$mem_tmp~0 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256);main_#t~ite28 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite28|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x~0 := main_#t~ite28;havoc main_#t~ite28;havoc main_#t~ite27; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite31 := ~x$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite31|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff0~0 := main_#t~ite31;havoc main_#t~ite29;havoc main_#t~ite31;havoc main_#t~ite30; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite34 := ~x$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite34|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff1~0 := main_#t~ite34;havoc main_#t~ite33;havoc main_#t~ite32;havoc main_#t~ite34; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite37 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite37|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff0_used~0 := main_#t~ite37;havoc main_#t~ite36;havoc main_#t~ite37;havoc main_#t~ite35; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite40 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$w_buff1_used~0 := main_#t~ite40;havoc main_#t~ite39;havoc main_#t~ite38;havoc main_#t~ite40; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite43;havoc main_#t~ite41; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite46;havoc main_#t~ite44;havoc main_#t~ite46;havoc main_#t~ite45;~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 2 == ~y~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 != ~x$flush_delayed~0 % 256;main_#t~ite47 := ~x$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite47|=2, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 ~x~0 := main_#t~ite47;havoc main_#t~ite47;~x$flush_delayed~0 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2477~0.base|=5, |ULTIMATE.start_main_~#t2477~0.offset|=0, |ULTIMATE.start_main_~#t2478~0.base|=6, |ULTIMATE.start_main_~#t2478~0.offset|=0, ~__unbuffered_cnt~0=2, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L672] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [L673] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L675] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L676] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L677] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L678] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L679] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L681] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L682] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L684] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L685] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [L686] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L687] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L688] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L689] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L693] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25.base, main_#t~nondet25.offset, main_#t~nondet26.base, main_#t~nondet26.offset, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t2477~0.base, main_~#t2477~0.offset, main_~#t2478~0.base, main_~#t2478~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L753] -1 call main_~#t2477~0.base, main_~#t2477~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] -1 call write~int(0, main_~#t2477~0.base, main_~#t2477~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] -1 havoc main_#t~nondet17; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] -1 call main_~#t2478~0.base, main_~#t2478~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 call write~int(1, main_~#t2478~0.base, main_~#t2478~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L714-L741] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L717] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L718] 0 ~x$w_buff0~0 := 2; [L719] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L720] 0 ~x$w_buff0_used~0 := 1; [L721] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L721] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L722] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L723] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L724] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L725] 0 ~x$r_buff0_thd2~0 := 1; [L728] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L731] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256; [L731] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L694-L713] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L697] 1 ~y~0 := 2; [L700] 1 ~x~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256); [L703] 1 #t~ite3 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, #t~ite3=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 #t~ite4 := #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, #t~ite3=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 ~x~0 := #t~ite4; [L703] 1 havoc #t~ite3; [L703] 1 havoc #t~ite4; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L704] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] 1 ~x$w_buff0_used~0 := #t~ite5; [L704] 1 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L705] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] 1 ~x$w_buff1_used~0 := #t~ite6; [L705] 1 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L731] 0 ~x~0 := #t~ite11; [L731] 0 havoc #t~ite11; [L731] 0 havoc #t~ite10; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L706] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L706] 1 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256; [L732] 0 #t~ite12 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite12=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] 0 ~x$w_buff0_used~0 := #t~ite12; [L732] 0 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L733] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] 0 ~x$w_buff1_used~0 := #t~ite13; [L733] 0 havoc #t~ite13; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L734] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite14=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L734] 0 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L735] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite15=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L735] 0 havoc #t~ite15; [L738] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L707] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L707] 1 havoc #t~ite8; [L710] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L756] -1 havoc main_#t~nondet18; [L758] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L760] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L762] -1 main_#t~ite19 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 main_#t~ite20 := main_#t~ite19; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_#t~ite20=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 ~x~0 := main_#t~ite20; [L762] -1 havoc main_#t~ite19; [L762] -1 havoc main_#t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L763] -1 main_#t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite21=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] -1 ~x$w_buff0_used~0 := main_#t~ite21; [L763] -1 havoc main_#t~ite21; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L764] -1 main_#t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite22=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] -1 ~x$w_buff1_used~0 := main_#t~ite22; [L764] -1 havoc main_#t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L765] -1 main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite23=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] -1 ~x$r_buff0_thd0~0 := main_#t~ite23; [L765] -1 havoc main_#t~ite23; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L766] -1 main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite24=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] -1 ~x$r_buff1_thd0~0 := main_#t~ite24; [L766] -1 havoc main_#t~ite24; [L769] -1 ~weak$$choice0~0 := (if 0 == main_#t~nondet25.base + main_#t~nondet25.offset then 0 else 1); [L769] -1 havoc main_#t~nondet25.base, main_#t~nondet25.offset; [L770] -1 ~weak$$choice2~0 := (if 0 == main_#t~nondet26.base + main_#t~nondet26.offset then 0 else 1); [L770] -1 havoc main_#t~nondet26.base, main_#t~nondet26.offset; [L771] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L772] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] -1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256); [L773] -1 main_#t~ite28 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite28=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] -1 ~x~0 := main_#t~ite28; [L773] -1 havoc main_#t~ite28; [L773] -1 havoc main_#t~ite27; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] -1 assume 0 != ~weak$$choice2~0 % 256; [L774] -1 main_#t~ite31 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite31=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] -1 ~x$w_buff0~0 := main_#t~ite31; [L774] -1 havoc main_#t~ite29; [L774] -1 havoc main_#t~ite31; [L774] -1 havoc main_#t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] -1 assume 0 != ~weak$$choice2~0 % 256; [L775] -1 main_#t~ite34 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite34=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] -1 ~x$w_buff1~0 := main_#t~ite34; [L775] -1 havoc main_#t~ite33; [L775] -1 havoc main_#t~ite32; [L775] -1 havoc main_#t~ite34; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] -1 assume 0 != ~weak$$choice2~0 % 256; [L776] -1 main_#t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite37=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] -1 ~x$w_buff0_used~0 := main_#t~ite37; [L776] -1 havoc main_#t~ite36; [L776] -1 havoc main_#t~ite37; [L776] -1 havoc main_#t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] -1 assume 0 != ~weak$$choice2~0 % 256; [L777] -1 main_#t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] -1 ~x$w_buff1_used~0 := main_#t~ite40; [L777] -1 havoc main_#t~ite39; [L777] -1 havoc main_#t~ite38; [L777] -1 havoc main_#t~ite40; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] -1 assume 0 != ~weak$$choice2~0 % 256; [L778] -1 main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] -1 ~x$r_buff0_thd0~0 := main_#t~ite43; [L778] -1 havoc main_#t~ite42; [L778] -1 havoc main_#t~ite43; [L778] -1 havoc main_#t~ite41; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] -1 assume 0 != ~weak$$choice2~0 % 256; [L779] -1 main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] -1 ~x$r_buff1_thd0~0 := main_#t~ite46; [L779] -1 havoc main_#t~ite44; [L779] -1 havoc main_#t~ite46; [L779] -1 havoc main_#t~ite45; [L780] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 2 == ~y~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] -1 assume 0 != ~x$flush_delayed~0 % 256; [L781] -1 main_#t~ite47 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] -1 ~x~0 := main_#t~ite47; [L781] -1 havoc main_#t~ite47; [L782] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L784] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L784] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L672] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [L673] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L675] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L676] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L677] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L678] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L679] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L681] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L682] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L684] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L685] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [L686] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L687] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L688] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L689] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L693] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25.base, main_#t~nondet25.offset, main_#t~nondet26.base, main_#t~nondet26.offset, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t2477~0.base, main_~#t2477~0.offset, main_~#t2478~0.base, main_~#t2478~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L753] -1 call main_~#t2477~0.base, main_~#t2477~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] -1 call write~int(0, main_~#t2477~0.base, main_~#t2477~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] -1 havoc main_#t~nondet17; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] -1 call main_~#t2478~0.base, main_~#t2478~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 call write~int(1, main_~#t2478~0.base, main_~#t2478~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L714-L741] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L717] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L718] 0 ~x$w_buff0~0 := 2; [L719] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L720] 0 ~x$w_buff0_used~0 := 1; [L721] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L721] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L722] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L723] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L724] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L725] 0 ~x$r_buff0_thd2~0 := 1; [L728] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L731] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256; [L731] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L694-L713] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L697] 1 ~y~0 := 2; [L700] 1 ~x~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256); [L703] 1 #t~ite3 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, #t~ite3=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 #t~ite4 := #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, #t~ite3=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 ~x~0 := #t~ite4; [L703] 1 havoc #t~ite3; [L703] 1 havoc #t~ite4; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L704] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] 1 ~x$w_buff0_used~0 := #t~ite5; [L704] 1 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L705] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] 1 ~x$w_buff1_used~0 := #t~ite6; [L705] 1 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L731] 0 ~x~0 := #t~ite11; [L731] 0 havoc #t~ite11; [L731] 0 havoc #t~ite10; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L706] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L706] 1 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256; [L732] 0 #t~ite12 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite12=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] 0 ~x$w_buff0_used~0 := #t~ite12; [L732] 0 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L733] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] 0 ~x$w_buff1_used~0 := #t~ite13; [L733] 0 havoc #t~ite13; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L734] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite14=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L734] 0 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L735] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite15=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L735] 0 havoc #t~ite15; [L738] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L707] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L707] 1 havoc #t~ite8; [L710] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L756] -1 havoc main_#t~nondet18; [L758] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L760] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L762] -1 main_#t~ite19 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 main_#t~ite20 := main_#t~ite19; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_#t~ite20=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 ~x~0 := main_#t~ite20; [L762] -1 havoc main_#t~ite19; [L762] -1 havoc main_#t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L763] -1 main_#t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite21=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] -1 ~x$w_buff0_used~0 := main_#t~ite21; [L763] -1 havoc main_#t~ite21; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L764] -1 main_#t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite22=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] -1 ~x$w_buff1_used~0 := main_#t~ite22; [L764] -1 havoc main_#t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L765] -1 main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite23=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] -1 ~x$r_buff0_thd0~0 := main_#t~ite23; [L765] -1 havoc main_#t~ite23; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L766] -1 main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite24=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] -1 ~x$r_buff1_thd0~0 := main_#t~ite24; [L766] -1 havoc main_#t~ite24; [L769] -1 ~weak$$choice0~0 := (if 0 == main_#t~nondet25.base + main_#t~nondet25.offset then 0 else 1); [L769] -1 havoc main_#t~nondet25.base, main_#t~nondet25.offset; [L770] -1 ~weak$$choice2~0 := (if 0 == main_#t~nondet26.base + main_#t~nondet26.offset then 0 else 1); [L770] -1 havoc main_#t~nondet26.base, main_#t~nondet26.offset; [L771] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L772] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] -1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256); [L773] -1 main_#t~ite28 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite28=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] -1 ~x~0 := main_#t~ite28; [L773] -1 havoc main_#t~ite28; [L773] -1 havoc main_#t~ite27; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] -1 assume 0 != ~weak$$choice2~0 % 256; [L774] -1 main_#t~ite31 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite31=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] -1 ~x$w_buff0~0 := main_#t~ite31; [L774] -1 havoc main_#t~ite29; [L774] -1 havoc main_#t~ite31; [L774] -1 havoc main_#t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] -1 assume 0 != ~weak$$choice2~0 % 256; [L775] -1 main_#t~ite34 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite34=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] -1 ~x$w_buff1~0 := main_#t~ite34; [L775] -1 havoc main_#t~ite33; [L775] -1 havoc main_#t~ite32; [L775] -1 havoc main_#t~ite34; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] -1 assume 0 != ~weak$$choice2~0 % 256; [L776] -1 main_#t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite37=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] -1 ~x$w_buff0_used~0 := main_#t~ite37; [L776] -1 havoc main_#t~ite36; [L776] -1 havoc main_#t~ite37; [L776] -1 havoc main_#t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] -1 assume 0 != ~weak$$choice2~0 % 256; [L777] -1 main_#t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] -1 ~x$w_buff1_used~0 := main_#t~ite40; [L777] -1 havoc main_#t~ite39; [L777] -1 havoc main_#t~ite38; [L777] -1 havoc main_#t~ite40; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] -1 assume 0 != ~weak$$choice2~0 % 256; [L778] -1 main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] -1 ~x$r_buff0_thd0~0 := main_#t~ite43; [L778] -1 havoc main_#t~ite42; [L778] -1 havoc main_#t~ite43; [L778] -1 havoc main_#t~ite41; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] -1 assume 0 != ~weak$$choice2~0 % 256; [L779] -1 main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] -1 ~x$r_buff1_thd0~0 := main_#t~ite46; [L779] -1 havoc main_#t~ite44; [L779] -1 havoc main_#t~ite46; [L779] -1 havoc main_#t~ite45; [L780] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 2 == ~y~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] -1 assume 0 != ~x$flush_delayed~0 % 256; [L781] -1 main_#t~ite47 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=2, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] -1 ~x~0 := main_#t~ite47; [L781] -1 havoc main_#t~ite47; [L782] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L784] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L784] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0.base=5, main_~#t2477~0.offset=0, main_~#t2478~0.base=6, main_~#t2478~0.offset=0, ~__unbuffered_cnt~0=2, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L672] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [L673] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L675] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L676] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L677] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L678] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L679] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L681] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L682] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L684] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L685] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L686] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L687] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L688] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L689] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L693] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25, main_#t~nondet26, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t2477~0, main_~#t2478~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L753] FCALL -1 call main_~#t2477~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FCALL -1 call write~int(0, main_~#t2477~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] -1 havoc main_#t~nondet17; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] FCALL -1 call main_~#t2478~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FCALL -1 call write~int(1, main_~#t2478~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L714-L741] 0 ~arg := #in~arg; [L717] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L718] 0 ~x$w_buff0~0 := 2; [L719] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L720] 0 ~x$w_buff0_used~0 := 1; [L721] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L721] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L722] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L723] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L724] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L725] 0 ~x$r_buff0_thd2~0 := 1; [L728] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L731] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L731] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L694-L713] 1 ~arg := #in~arg; [L697] 1 ~y~0 := 2; [L700] 1 ~x~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256) [L703] 1 #t~ite3 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, #t~ite3=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 #t~ite4 := #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, #t~ite3=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 ~x~0 := #t~ite4; [L703] 1 havoc #t~ite3; [L703] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L704] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] 1 ~x$w_buff0_used~0 := #t~ite5; [L704] 1 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L705] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] 1 ~x$w_buff1_used~0 := #t~ite6; [L705] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L731] 0 ~x~0 := #t~ite11; [L731] 0 havoc #t~ite11; [L731] 0 havoc #t~ite10; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L706] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L706] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L732] 0 #t~ite12 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite12=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] 0 ~x$w_buff0_used~0 := #t~ite12; [L732] 0 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L733] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] 0 ~x$w_buff1_used~0 := #t~ite13; [L733] 0 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L734] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite14=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L734] 0 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L735] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite15=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L735] 0 havoc #t~ite15; [L738] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L707] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L707] 1 havoc #t~ite8; [L710] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L756] -1 havoc main_#t~nondet18; [L758] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L760] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L762] -1 main_#t~ite19 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 main_#t~ite20 := main_#t~ite19; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_#t~ite20=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 ~x~0 := main_#t~ite20; [L762] -1 havoc main_#t~ite19; [L762] -1 havoc main_#t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L763] -1 main_#t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite21=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] -1 ~x$w_buff0_used~0 := main_#t~ite21; [L763] -1 havoc main_#t~ite21; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L764] -1 main_#t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite22=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] -1 ~x$w_buff1_used~0 := main_#t~ite22; [L764] -1 havoc main_#t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L765] -1 main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite23=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] -1 ~x$r_buff0_thd0~0 := main_#t~ite23; [L765] -1 havoc main_#t~ite23; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L766] -1 main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite24=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] -1 ~x$r_buff1_thd0~0 := main_#t~ite24; [L766] -1 havoc main_#t~ite24; [L769] -1 ~weak$$choice0~0 := (if 0 == main_#t~nondet25!base + main_#t~nondet25!offset then 0 else 1); [L769] -1 havoc main_#t~nondet25; [L770] -1 ~weak$$choice2~0 := (if 0 == main_#t~nondet26!base + main_#t~nondet26!offset then 0 else 1); [L770] -1 havoc main_#t~nondet26; [L771] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L772] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] COND TRUE -1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256) [L773] -1 main_#t~ite28 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite28=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] -1 ~x~0 := main_#t~ite28; [L773] -1 havoc main_#t~ite28; [L773] -1 havoc main_#t~ite27; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L774] -1 main_#t~ite31 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite31=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] -1 ~x$w_buff0~0 := main_#t~ite31; [L774] -1 havoc main_#t~ite29; [L774] -1 havoc main_#t~ite31; [L774] -1 havoc main_#t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L775] -1 main_#t~ite34 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite34=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] -1 ~x$w_buff1~0 := main_#t~ite34; [L775] -1 havoc main_#t~ite33; [L775] -1 havoc main_#t~ite32; [L775] -1 havoc main_#t~ite34; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L776] -1 main_#t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite37=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] -1 ~x$w_buff0_used~0 := main_#t~ite37; [L776] -1 havoc main_#t~ite36; [L776] -1 havoc main_#t~ite37; [L776] -1 havoc main_#t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L777] -1 main_#t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] -1 ~x$w_buff1_used~0 := main_#t~ite40; [L777] -1 havoc main_#t~ite39; [L777] -1 havoc main_#t~ite38; [L777] -1 havoc main_#t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L778] -1 main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] -1 ~x$r_buff0_thd0~0 := main_#t~ite43; [L778] -1 havoc main_#t~ite42; [L778] -1 havoc main_#t~ite43; [L778] -1 havoc main_#t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L779] -1 main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] -1 ~x$r_buff1_thd0~0 := main_#t~ite46; [L779] -1 havoc main_#t~ite44; [L779] -1 havoc main_#t~ite46; [L779] -1 havoc main_#t~ite45; [L780] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 2 == ~y~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] COND TRUE -1 0 != ~x$flush_delayed~0 % 256 [L781] -1 main_#t~ite47 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] -1 ~x~0 := main_#t~ite47; [L781] -1 havoc main_#t~ite47; [L782] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L784] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L784] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L672] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [L673] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L675] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L676] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L677] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L678] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L679] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L681] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L682] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L684] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L685] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L686] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L687] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L688] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L689] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L693] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25, main_#t~nondet26, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t2477~0, main_~#t2478~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L753] FCALL -1 call main_~#t2477~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FCALL -1 call write~int(0, main_~#t2477~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] -1 havoc main_#t~nondet17; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] FCALL -1 call main_~#t2478~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FCALL -1 call write~int(1, main_~#t2478~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L714-L741] 0 ~arg := #in~arg; [L717] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L718] 0 ~x$w_buff0~0 := 2; [L719] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L720] 0 ~x$w_buff0_used~0 := 1; [L721] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L721] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L722] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L723] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L724] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L725] 0 ~x$r_buff0_thd2~0 := 1; [L728] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L731] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L731] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L694-L713] 1 ~arg := #in~arg; [L697] 1 ~y~0 := 2; [L700] 1 ~x~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256) [L703] 1 #t~ite3 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, #t~ite3=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 #t~ite4 := #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, #t~ite3=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 ~x~0 := #t~ite4; [L703] 1 havoc #t~ite3; [L703] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L704] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] 1 ~x$w_buff0_used~0 := #t~ite5; [L704] 1 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L705] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] 1 ~x$w_buff1_used~0 := #t~ite6; [L705] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L731] 0 ~x~0 := #t~ite11; [L731] 0 havoc #t~ite11; [L731] 0 havoc #t~ite10; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L706] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L706] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L732] 0 #t~ite12 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite12=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] 0 ~x$w_buff0_used~0 := #t~ite12; [L732] 0 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L733] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] 0 ~x$w_buff1_used~0 := #t~ite13; [L733] 0 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L734] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite14=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L734] 0 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L735] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite15=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L735] 0 havoc #t~ite15; [L738] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L707] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L707] 1 havoc #t~ite8; [L710] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L756] -1 havoc main_#t~nondet18; [L758] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L760] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L762] -1 main_#t~ite19 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 main_#t~ite20 := main_#t~ite19; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_#t~ite20=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 ~x~0 := main_#t~ite20; [L762] -1 havoc main_#t~ite19; [L762] -1 havoc main_#t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L763] -1 main_#t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite21=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] -1 ~x$w_buff0_used~0 := main_#t~ite21; [L763] -1 havoc main_#t~ite21; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L764] -1 main_#t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite22=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] -1 ~x$w_buff1_used~0 := main_#t~ite22; [L764] -1 havoc main_#t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L765] -1 main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite23=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] -1 ~x$r_buff0_thd0~0 := main_#t~ite23; [L765] -1 havoc main_#t~ite23; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L766] -1 main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite24=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] -1 ~x$r_buff1_thd0~0 := main_#t~ite24; [L766] -1 havoc main_#t~ite24; [L769] -1 ~weak$$choice0~0 := (if 0 == main_#t~nondet25!base + main_#t~nondet25!offset then 0 else 1); [L769] -1 havoc main_#t~nondet25; [L770] -1 ~weak$$choice2~0 := (if 0 == main_#t~nondet26!base + main_#t~nondet26!offset then 0 else 1); [L770] -1 havoc main_#t~nondet26; [L771] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L772] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] COND TRUE -1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256) [L773] -1 main_#t~ite28 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite28=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] -1 ~x~0 := main_#t~ite28; [L773] -1 havoc main_#t~ite28; [L773] -1 havoc main_#t~ite27; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L774] -1 main_#t~ite31 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite31=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] -1 ~x$w_buff0~0 := main_#t~ite31; [L774] -1 havoc main_#t~ite29; [L774] -1 havoc main_#t~ite31; [L774] -1 havoc main_#t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L775] -1 main_#t~ite34 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite34=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] -1 ~x$w_buff1~0 := main_#t~ite34; [L775] -1 havoc main_#t~ite33; [L775] -1 havoc main_#t~ite32; [L775] -1 havoc main_#t~ite34; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L776] -1 main_#t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite37=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] -1 ~x$w_buff0_used~0 := main_#t~ite37; [L776] -1 havoc main_#t~ite36; [L776] -1 havoc main_#t~ite37; [L776] -1 havoc main_#t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L777] -1 main_#t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] -1 ~x$w_buff1_used~0 := main_#t~ite40; [L777] -1 havoc main_#t~ite39; [L777] -1 havoc main_#t~ite38; [L777] -1 havoc main_#t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L778] -1 main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] -1 ~x$r_buff0_thd0~0 := main_#t~ite43; [L778] -1 havoc main_#t~ite42; [L778] -1 havoc main_#t~ite43; [L778] -1 havoc main_#t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L779] -1 main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] -1 ~x$r_buff1_thd0~0 := main_#t~ite46; [L779] -1 havoc main_#t~ite44; [L779] -1 havoc main_#t~ite46; [L779] -1 havoc main_#t~ite45; [L780] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 2 == ~y~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] COND TRUE -1 0 != ~x$flush_delayed~0 % 256 [L781] -1 main_#t~ite47 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=2, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] -1 ~x~0 := main_#t~ite47; [L781] -1 havoc main_#t~ite47; [L782] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L784] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L784] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t2477~0!base=5, main_~#t2477~0!offset=0, main_~#t2478~0!base=6, main_~#t2478~0!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L672] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [L673] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L675] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L676] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L677] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L678] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L679] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L681] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L682] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L684] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L685] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L686] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L687] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L688] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L689] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L693] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L753] FCALL -1 call ~#t2477~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FCALL -1 call write~int(0, ~#t2477~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] -1 havoc #t~nondet17; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] FCALL -1 call ~#t2478~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FCALL -1 call write~int(1, ~#t2478~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L714-L741] 0 ~arg := #in~arg; [L717] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L718] 0 ~x$w_buff0~0 := 2; [L719] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L720] 0 ~x$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L722] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L723] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L724] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L725] 0 ~x$r_buff0_thd2~0 := 1; [L728] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L731] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L731] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L694-L713] 1 ~arg := #in~arg; [L697] 1 ~y~0 := 2; [L700] 1 ~x~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256) [L703] 1 #t~ite3 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 #t~ite4 := #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, #t~ite4=1, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 ~x~0 := #t~ite4; [L703] 1 havoc #t~ite3; [L703] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L704] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] 1 ~x$w_buff0_used~0 := #t~ite5; [L704] 1 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L705] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] 1 ~x$w_buff1_used~0 := #t~ite6; [L705] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L731] 0 ~x~0 := #t~ite11; [L731] 0 havoc #t~ite11; [L731] 0 havoc #t~ite10; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L706] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L706] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L732] 0 #t~ite12 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] 0 ~x$w_buff0_used~0 := #t~ite12; [L732] 0 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L733] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] 0 ~x$w_buff1_used~0 := #t~ite13; [L733] 0 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L734] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L734] 0 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L735] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L735] 0 havoc #t~ite15; [L738] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L707] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, ~__unbuffered_cnt~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L707] 1 havoc #t~ite8; [L710] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L756] -1 havoc #t~nondet18; [L758] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L760] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L762] -1 #t~ite19 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 #t~ite20 := #t~ite19; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 ~x~0 := #t~ite20; [L762] -1 havoc #t~ite19; [L762] -1 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L763] -1 #t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] -1 ~x$w_buff0_used~0 := #t~ite21; [L763] -1 havoc #t~ite21; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L764] -1 #t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] -1 ~x$w_buff1_used~0 := #t~ite22; [L764] -1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L765] -1 #t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] -1 ~x$r_buff0_thd0~0 := #t~ite23; [L765] -1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L766] -1 #t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] -1 ~x$r_buff1_thd0~0 := #t~ite24; [L766] -1 havoc #t~ite24; [L769] -1 ~weak$$choice0~0 := (if 0 == #t~nondet25!base + #t~nondet25!offset then 0 else 1); [L769] -1 havoc #t~nondet25; [L770] -1 ~weak$$choice2~0 := (if 0 == #t~nondet26!base + #t~nondet26!offset then 0 else 1); [L770] -1 havoc #t~nondet26; [L771] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L772] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] COND TRUE -1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256) [L773] -1 #t~ite28 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] -1 ~x~0 := #t~ite28; [L773] -1 havoc #t~ite28; [L773] -1 havoc #t~ite27; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L774] -1 #t~ite31 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] -1 ~x$w_buff0~0 := #t~ite31; [L774] -1 havoc #t~ite29; [L774] -1 havoc #t~ite31; [L774] -1 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L775] -1 #t~ite34 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] -1 ~x$w_buff1~0 := #t~ite34; [L775] -1 havoc #t~ite33; [L775] -1 havoc #t~ite32; [L775] -1 havoc #t~ite34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L776] -1 #t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] -1 ~x$w_buff0_used~0 := #t~ite37; [L776] -1 havoc #t~ite36; [L776] -1 havoc #t~ite37; [L776] -1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L777] -1 #t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] -1 ~x$w_buff1_used~0 := #t~ite40; [L777] -1 havoc #t~ite39; [L777] -1 havoc #t~ite38; [L777] -1 havoc #t~ite40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L778] -1 #t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] -1 ~x$r_buff0_thd0~0 := #t~ite43; [L778] -1 havoc #t~ite42; [L778] -1 havoc #t~ite43; [L778] -1 havoc #t~ite41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L779] -1 #t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] -1 ~x$r_buff1_thd0~0 := #t~ite46; [L779] -1 havoc #t~ite44; [L779] -1 havoc #t~ite46; [L779] -1 havoc #t~ite45; [L780] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 2 == ~y~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] COND TRUE -1 0 != ~x$flush_delayed~0 % 256 [L781] -1 #t~ite47 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] -1 ~x~0 := #t~ite47; [L781] -1 havoc #t~ite47; [L782] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L672] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0] [L673] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L675] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L676] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L677] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L678] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L679] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L681] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L682] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L684] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L685] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L686] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L687] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L688] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L689] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L693] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L753] FCALL -1 call ~#t2477~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FCALL -1 call write~int(0, ~#t2477~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L754] -1 havoc #t~nondet17; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] FCALL -1 call ~#t2478~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FCALL -1 call write~int(1, ~#t2478~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L714-L741] 0 ~arg := #in~arg; [L717] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L718] 0 ~x$w_buff0~0 := 2; [L719] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L720] 0 ~x$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L722] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L723] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L724] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L725] 0 ~x$r_buff0_thd2~0 := 1; [L728] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L731] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L731] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1] [L694-L713] 1 ~arg := #in~arg; [L697] 1 ~y~0 := 2; [L700] 1 ~x~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256) [L703] 1 #t~ite3 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 #t~ite4 := #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, #t~ite4=1, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L703] 1 ~x~0 := #t~ite4; [L703] 1 havoc #t~ite3; [L703] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L704] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L704] 1 ~x$w_buff0_used~0 := #t~ite5; [L704] 1 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L705] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L705] 1 ~x$w_buff1_used~0 := #t~ite6; [L705] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2] [L731] 0 ~x~0 := #t~ite11; [L731] 0 havoc #t~ite11; [L731] 0 havoc #t~ite10; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L706] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L706] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L706] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L732] 0 #t~ite12 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L732] 0 ~x$w_buff0_used~0 := #t~ite12; [L732] 0 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L733] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L733] 0 ~x$w_buff1_used~0 := #t~ite13; [L733] 0 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L734] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L734] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L734] 0 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L735] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L735] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L735] 0 havoc #t~ite15; [L738] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L707] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, ~__unbuffered_cnt~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L707] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L707] 1 havoc #t~ite8; [L710] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L756] -1 havoc #t~nondet18; [L758] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L760] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L762] -1 #t~ite19 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 #t~ite20 := #t~ite19; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L762] -1 ~x~0 := #t~ite20; [L762] -1 havoc #t~ite19; [L762] -1 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L763] -1 #t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L763] -1 ~x$w_buff0_used~0 := #t~ite21; [L763] -1 havoc #t~ite21; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L764] -1 #t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L764] -1 ~x$w_buff1_used~0 := #t~ite22; [L764] -1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L765] -1 #t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L765] -1 ~x$r_buff0_thd0~0 := #t~ite23; [L765] -1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L766] -1 #t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L766] -1 ~x$r_buff1_thd0~0 := #t~ite24; [L766] -1 havoc #t~ite24; [L769] -1 ~weak$$choice0~0 := (if 0 == #t~nondet25!base + #t~nondet25!offset then 0 else 1); [L769] -1 havoc #t~nondet25; [L770] -1 ~weak$$choice2~0 := (if 0 == #t~nondet26!base + #t~nondet26!offset then 0 else 1); [L770] -1 havoc #t~nondet26; [L771] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L772] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] COND TRUE -1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256) [L773] -1 #t~ite28 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L773] -1 ~x~0 := #t~ite28; [L773] -1 havoc #t~ite28; [L773] -1 havoc #t~ite27; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L774] -1 #t~ite31 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L774] -1 ~x$w_buff0~0 := #t~ite31; [L774] -1 havoc #t~ite29; [L774] -1 havoc #t~ite31; [L774] -1 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L775] -1 #t~ite34 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L775] -1 ~x$w_buff1~0 := #t~ite34; [L775] -1 havoc #t~ite33; [L775] -1 havoc #t~ite32; [L775] -1 havoc #t~ite34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L776] -1 #t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L776] -1 ~x$w_buff0_used~0 := #t~ite37; [L776] -1 havoc #t~ite36; [L776] -1 havoc #t~ite37; [L776] -1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L777] -1 #t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L777] -1 ~x$w_buff1_used~0 := #t~ite40; [L777] -1 havoc #t~ite39; [L777] -1 havoc #t~ite38; [L777] -1 havoc #t~ite40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L778] -1 #t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L778] -1 ~x$r_buff0_thd0~0 := #t~ite43; [L778] -1 havoc #t~ite42; [L778] -1 havoc #t~ite43; [L778] -1 havoc #t~ite41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L779] -1 #t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L779] -1 ~x$r_buff1_thd0~0 := #t~ite46; [L779] -1 havoc #t~ite44; [L779] -1 havoc #t~ite46; [L779] -1 havoc #t~ite45; [L780] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 2 == ~y~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] COND TRUE -1 0 != ~x$flush_delayed~0 % 256 [L781] -1 #t~ite47 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L781] -1 ~x~0 := #t~ite47; [L781] -1 havoc #t~ite47; [L782] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=2] [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L672] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0] [L673] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0] [L675] -1 int x = 0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L676] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0] [L677] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0] [L678] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L679] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L680] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L681] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L682] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L683] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L684] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L685] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L686] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L687] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L688] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L689] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L691] -1 int y = 0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L692] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L693] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L753] -1 pthread_t t2477; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L754] FCALL, FORK -1 pthread_create(&t2477, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L755] -1 pthread_t t2478; VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L756] FCALL, FORK -1 pthread_create(&t2478, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L717] 0 x$w_buff1 = x$w_buff0 [L718] 0 x$w_buff0 = 2 [L719] 0 x$w_buff1_used = x$w_buff0_used [L720] 0 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0] [L722] 0 x$r_buff1_thd0 = x$r_buff0_thd0 [L723] 0 x$r_buff1_thd1 = x$r_buff0_thd1 [L724] 0 x$r_buff1_thd2 = x$r_buff0_thd2 [L725] 0 x$r_buff0_thd2 = (_Bool)1 [L728] 0 y = 1 VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L731] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L697] 1 y = 2 [L700] 1 x = 1 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L703] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L703] EXPR 1 x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x=1, y=2] [L703] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x)=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x=1, y=2] [L703] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L704] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L704] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L705] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L705] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L731] 0 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L706] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L706] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L732] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L732] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L733] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L733] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L734] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L734] 0 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L735] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L735] 0 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L738] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L707] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=1, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L707] 1 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L710] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L758] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L762] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L762] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L762] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L762] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L763] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L763] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L764] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L764] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L765] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L765] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L766] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L766] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L769] -1 weak$$choice0 = __VERIFIER_nondet_pointer() [L770] -1 weak$$choice2 = __VERIFIER_nondet_pointer() [L771] -1 x$flush_delayed = weak$$choice2 [L772] -1 x$mem_tmp = x VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L773] EXPR -1 !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L773] -1 x = !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) [L774] EXPR -1 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L774] -1 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) [L775] EXPR -1 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L775] -1 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) [L776] EXPR -1 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L776] -1 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) [L777] EXPR -1 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L777] -1 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L778] EXPR -1 weak$$choice2 ? x$r_buff0_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff0_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L778] -1 x$r_buff0_thd0 = weak$$choice2 ? x$r_buff0_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff0_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0)) [L779] EXPR -1 weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L779] -1 x$r_buff1_thd0 = weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L780] -1 main$tmp_guard1 = !(x == 2 && y == 2) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L781] EXPR -1 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L781] -1 x = x$flush_delayed ? x$mem_tmp : x [L782] -1 x$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] ----- [2018-11-23 03:49:18,385 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_69642bdf-4e67-44c1-b368-2141fba9f8c8/bin-2019/uautomizer/witness.graphml [2018-11-23 03:49:18,385 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 03:49:18,386 INFO L168 Benchmark]: Toolchain (without parser) took 21024.93 ms. Allocated memory was 1.0 GB in the beginning and 2.4 GB in the end (delta: 1.3 GB). Free memory was 957.6 MB in the beginning and 1.5 GB in the end (delta: -497.8 MB). Peak memory consumption was 842.3 MB. Max. memory is 11.5 GB. [2018-11-23 03:49:18,387 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 03:49:18,387 INFO L168 Benchmark]: CACSL2BoogieTranslator took 410.10 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 132.6 MB). Free memory was 957.6 MB in the beginning and 1.1 GB in the end (delta: -152.6 MB). Peak memory consumption was 36.5 MB. Max. memory is 11.5 GB. [2018-11-23 03:49:18,387 INFO L168 Benchmark]: Boogie Procedure Inliner took 34.67 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-23 03:49:18,387 INFO L168 Benchmark]: Boogie Preprocessor took 19.28 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-23 03:49:18,388 INFO L168 Benchmark]: RCFGBuilder took 498.61 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 44.5 MB). Peak memory consumption was 44.5 MB. Max. memory is 11.5 GB. [2018-11-23 03:49:18,388 INFO L168 Benchmark]: TraceAbstraction took 16256.47 ms. Allocated memory was 1.2 GB in the beginning and 2.4 GB in the end (delta: 1.2 GB). Free memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: -494.1 MB). Peak memory consumption was 713.3 MB. Max. memory is 11.5 GB. [2018-11-23 03:49:18,388 INFO L168 Benchmark]: Witness Printer took 3802.44 ms. Allocated memory is still 2.4 GB. Free memory was 1.6 GB in the beginning and 1.5 GB in the end (delta: 99.0 MB). Peak memory consumption was 99.0 MB. Max. memory is 11.5 GB. [2018-11-23 03:49:18,390 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 410.10 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 132.6 MB). Free memory was 957.6 MB in the beginning and 1.1 GB in the end (delta: -152.6 MB). Peak memory consumption was 36.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 34.67 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 19.28 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 498.61 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 44.5 MB). Peak memory consumption was 44.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 16256.47 ms. Allocated memory was 1.2 GB in the beginning and 2.4 GB in the end (delta: 1.2 GB). Free memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: -494.1 MB). Peak memory consumption was 713.3 MB. Max. memory is 11.5 GB. * Witness Printer took 3802.44 ms. Allocated memory is still 2.4 GB. Free memory was 1.6 GB in the beginning and 1.5 GB in the end (delta: 99.0 MB). Peak memory consumption was 99.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L672] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0] [L673] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0] [L675] -1 int x = 0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L676] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0] [L677] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0] [L678] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L679] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L680] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L681] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L682] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L683] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L684] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L685] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L686] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L687] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L688] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L689] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L691] -1 int y = 0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L692] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L693] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L753] -1 pthread_t t2477; VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L754] FCALL, FORK -1 pthread_create(&t2477, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L755] -1 pthread_t t2478; VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L756] FCALL, FORK -1 pthread_create(&t2478, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L717] 0 x$w_buff1 = x$w_buff0 [L718] 0 x$w_buff0 = 2 [L719] 0 x$w_buff1_used = x$w_buff0_used [L720] 0 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0] [L722] 0 x$r_buff1_thd0 = x$r_buff0_thd0 [L723] 0 x$r_buff1_thd1 = x$r_buff0_thd1 [L724] 0 x$r_buff1_thd2 = x$r_buff0_thd2 [L725] 0 x$r_buff0_thd2 = (_Bool)1 [L728] 0 y = 1 VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L731] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L697] 1 y = 2 [L700] 1 x = 1 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L703] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L703] EXPR 1 x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x=1, y=2] [L703] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x)=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x=1, y=2] [L703] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L704] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L704] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L705] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L705] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L731] 0 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L706] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L706] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L732] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L732] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L733] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L733] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L734] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L734] 0 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L735] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L735] 0 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L738] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L707] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=1, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L707] 1 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L710] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L758] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L762] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L762] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L762] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L762] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L763] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L763] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L764] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L764] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L765] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L765] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L766] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L766] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L769] -1 weak$$choice0 = __VERIFIER_nondet_pointer() [L770] -1 weak$$choice2 = __VERIFIER_nondet_pointer() [L771] -1 x$flush_delayed = weak$$choice2 [L772] -1 x$mem_tmp = x VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L773] EXPR -1 !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L773] -1 x = !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) [L774] EXPR -1 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L774] -1 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) [L775] EXPR -1 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L775] -1 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) [L776] EXPR -1 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L776] -1 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) [L777] EXPR -1 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L777] -1 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L778] EXPR -1 weak$$choice2 ? x$r_buff0_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff0_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L778] -1 x$r_buff0_thd0 = weak$$choice2 ? x$r_buff0_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff0_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0)) [L779] EXPR -1 weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L779] -1 x$r_buff1_thd0 = weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L780] -1 main$tmp_guard1 = !(x == 2 && y == 2) VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L781] EXPR -1 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L781] -1 x = x$flush_delayed ? x$mem_tmp : x [L782] -1 x$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 178 locations, 3 error locations. UNSAFE Result, 16.1s OverallTime, 28 OverallIterations, 1 TraceHistogramMax, 7.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5974 SDtfs, 5883 SDslu, 13328 SDs, 0 SdLazy, 5683 SolverSat, 415 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 284 GetRequests, 85 SyntacticMatches, 14 SemanticMatches, 185 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 190 ImplicationChecksByTransitivity, 2.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=37140occurred in iteration=2, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 3.4s AutomataMinimizationTime, 27 MinimizatonAttempts, 97372 StatesRemovedByMinimization, 25 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.9s InterpolantComputationTime, 2297 NumberOfCodeBlocks, 2297 NumberOfCodeBlocksAsserted, 28 NumberOfCheckSat, 2177 ConstructedInterpolants, 0 QuantifiedInterpolants, 457021 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 27 InterpolantComputations, 27 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...