./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ee05cb2d66f71fb2277986b04bb223cfc634fed1 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ee05cb2d66f71fb2277986b04bb223cfc634fed1 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Result: TRUE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 05:46:10,334 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 05:46:10,335 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 05:46:10,343 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 05:46:10,344 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 05:46:10,344 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 05:46:10,345 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 05:46:10,346 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 05:46:10,347 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 05:46:10,348 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 05:46:10,349 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 05:46:10,349 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 05:46:10,349 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 05:46:10,350 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 05:46:10,351 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 05:46:10,351 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 05:46:10,352 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 05:46:10,353 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 05:46:10,354 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 05:46:10,355 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 05:46:10,356 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 05:46:10,357 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 05:46:10,358 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 05:46:10,359 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 05:46:10,359 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 05:46:10,359 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 05:46:10,360 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 05:46:10,361 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 05:46:10,361 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 05:46:10,362 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 05:46:10,362 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 05:46:10,363 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 05:46:10,363 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 05:46:10,363 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 05:46:10,364 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 05:46:10,364 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 05:46:10,364 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-23 05:46:10,374 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 05:46:10,374 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 05:46:10,375 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 05:46:10,375 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 05:46:10,375 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 05:46:10,375 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 05:46:10,376 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 05:46:10,376 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 05:46:10,376 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 05:46:10,376 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 05:46:10,376 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 05:46:10,376 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 05:46:10,376 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 05:46:10,377 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 05:46:10,377 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 05:46:10,377 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 05:46:10,377 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 05:46:10,377 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 05:46:10,377 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 05:46:10,377 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 05:46:10,377 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 05:46:10,378 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 05:46:10,378 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 05:46:10,378 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 05:46:10,378 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 05:46:10,378 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 05:46:10,378 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 05:46:10,378 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 05:46:10,379 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 05:46:10,379 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 05:46:10,379 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ee05cb2d66f71fb2277986b04bb223cfc634fed1 [2018-11-23 05:46:10,401 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 05:46:10,409 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 05:46:10,412 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 05:46:10,413 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 05:46:10,413 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 05:46:10,413 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/../../sv-benchmarks/c/bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c [2018-11-23 05:46:10,450 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/data/67785e9b5/2953c5dd2f594c9d82ac81f788d82aba/FLAGf4203e869 [2018-11-23 05:46:10,854 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 05:46:10,854 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/sv-benchmarks/c/bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c [2018-11-23 05:46:10,859 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/data/67785e9b5/2953c5dd2f594c9d82ac81f788d82aba/FLAGf4203e869 [2018-11-23 05:46:10,868 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/data/67785e9b5/2953c5dd2f594c9d82ac81f788d82aba [2018-11-23 05:46:10,871 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 05:46:10,872 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 05:46:10,872 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 05:46:10,872 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 05:46:10,875 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 05:46:10,875 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 05:46:10" (1/1) ... [2018-11-23 05:46:10,877 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@76b02929 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:10, skipping insertion in model container [2018-11-23 05:46:10,878 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 05:46:10" (1/1) ... [2018-11-23 05:46:10,885 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 05:46:10,908 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 05:46:11,064 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 05:46:11,066 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 05:46:11,094 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 05:46:11,106 INFO L195 MainTranslator]: Completed translation [2018-11-23 05:46:11,106 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:11 WrapperNode [2018-11-23 05:46:11,107 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 05:46:11,107 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 05:46:11,107 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 05:46:11,107 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 05:46:11,115 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:11" (1/1) ... [2018-11-23 05:46:11,120 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:11" (1/1) ... [2018-11-23 05:46:11,176 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 05:46:11,176 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 05:46:11,177 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 05:46:11,177 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 05:46:11,185 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:11" (1/1) ... [2018-11-23 05:46:11,185 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:11" (1/1) ... [2018-11-23 05:46:11,187 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:11" (1/1) ... [2018-11-23 05:46:11,187 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:11" (1/1) ... [2018-11-23 05:46:11,192 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:11" (1/1) ... [2018-11-23 05:46:11,197 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:11" (1/1) ... [2018-11-23 05:46:11,198 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:11" (1/1) ... [2018-11-23 05:46:11,199 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 05:46:11,199 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 05:46:11,199 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 05:46:11,200 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 05:46:11,200 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:11" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 05:46:11,231 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 05:46:11,231 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 05:46:11,231 INFO L130 BoogieDeclarations]: Found specification of procedure base2flt [2018-11-23 05:46:11,231 INFO L138 BoogieDeclarations]: Found implementation of procedure base2flt [2018-11-23 05:46:11,231 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 05:46:11,231 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 05:46:11,231 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 05:46:11,232 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 05:46:11,232 INFO L130 BoogieDeclarations]: Found specification of procedure addflt [2018-11-23 05:46:11,232 INFO L138 BoogieDeclarations]: Found implementation of procedure addflt [2018-11-23 05:46:11,232 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-23 05:46:11,232 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-23 05:46:11,404 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 05:46:11,404 INFO L280 CfgBuilder]: Removed 2 assue(true) statements. [2018-11-23 05:46:11,404 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:46:11 BoogieIcfgContainer [2018-11-23 05:46:11,404 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 05:46:11,405 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 05:46:11,405 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 05:46:11,407 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 05:46:11,407 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 05:46:10" (1/3) ... [2018-11-23 05:46:11,407 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4b5b9801 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 05:46:11, skipping insertion in model container [2018-11-23 05:46:11,407 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:11" (2/3) ... [2018-11-23 05:46:11,408 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4b5b9801 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 05:46:11, skipping insertion in model container [2018-11-23 05:46:11,408 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:46:11" (3/3) ... [2018-11-23 05:46:11,409 INFO L112 eAbstractionObserver]: Analyzing ICFG soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c [2018-11-23 05:46:11,416 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 05:46:11,420 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 05:46:11,429 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 05:46:11,448 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 05:46:11,449 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 05:46:11,449 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 05:46:11,449 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 05:46:11,449 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 05:46:11,449 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 05:46:11,449 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 05:46:11,449 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 05:46:11,449 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 05:46:11,462 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states. [2018-11-23 05:46:11,466 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-23 05:46:11,466 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:11,467 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:11,468 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:11,471 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:11,472 INFO L82 PathProgramCache]: Analyzing trace with hash 1457053844, now seen corresponding path program 1 times [2018-11-23 05:46:11,473 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:46:11,473 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:46:11,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:11,503 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:11,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:11,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:11,763 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-23 05:46:11,765 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:46:11,765 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:46:11,780 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:11,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:11,827 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:11,885 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-23 05:46:11,904 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:46:11,904 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 11] total 12 [2018-11-23 05:46:11,907 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-23 05:46:11,918 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-23 05:46:11,919 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=110, Unknown=0, NotChecked=0, Total=132 [2018-11-23 05:46:11,920 INFO L87 Difference]: Start difference. First operand 56 states. Second operand 12 states. [2018-11-23 05:46:12,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:12,232 INFO L93 Difference]: Finished difference Result 157 states and 243 transitions. [2018-11-23 05:46:12,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 05:46:12,233 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 34 [2018-11-23 05:46:12,234 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:12,242 INFO L225 Difference]: With dead ends: 157 [2018-11-23 05:46:12,242 INFO L226 Difference]: Without dead ends: 99 [2018-11-23 05:46:12,245 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 31 SyntacticMatches, 1 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=68, Invalid=312, Unknown=0, NotChecked=0, Total=380 [2018-11-23 05:46:12,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-11-23 05:46:12,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 77. [2018-11-23 05:46:12,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-11-23 05:46:12,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 106 transitions. [2018-11-23 05:46:12,285 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 106 transitions. Word has length 34 [2018-11-23 05:46:12,286 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:12,286 INFO L480 AbstractCegarLoop]: Abstraction has 77 states and 106 transitions. [2018-11-23 05:46:12,286 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-23 05:46:12,286 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 106 transitions. [2018-11-23 05:46:12,288 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-23 05:46:12,288 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:12,288 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:12,289 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:12,289 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:12,289 INFO L82 PathProgramCache]: Analyzing trace with hash 1514312146, now seen corresponding path program 1 times [2018-11-23 05:46:12,289 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:46:12,289 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:46:12,290 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:12,290 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:12,290 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:12,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:12,425 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-23 05:46:12,425 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:12,425 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 05:46:12,426 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 05:46:12,426 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 05:46:12,426 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-11-23 05:46:12,427 INFO L87 Difference]: Start difference. First operand 77 states and 106 transitions. Second operand 8 states. [2018-11-23 05:46:12,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:12,504 INFO L93 Difference]: Finished difference Result 137 states and 187 transitions. [2018-11-23 05:46:12,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 05:46:12,504 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 34 [2018-11-23 05:46:12,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:12,505 INFO L225 Difference]: With dead ends: 137 [2018-11-23 05:46:12,505 INFO L226 Difference]: Without dead ends: 100 [2018-11-23 05:46:12,506 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-11-23 05:46:12,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-11-23 05:46:12,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 85. [2018-11-23 05:46:12,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-11-23 05:46:12,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 114 transitions. [2018-11-23 05:46:12,519 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 114 transitions. Word has length 34 [2018-11-23 05:46:12,519 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:12,519 INFO L480 AbstractCegarLoop]: Abstraction has 85 states and 114 transitions. [2018-11-23 05:46:12,519 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 05:46:12,520 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 114 transitions. [2018-11-23 05:46:12,521 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-11-23 05:46:12,521 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:12,521 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:12,521 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:12,521 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:12,522 INFO L82 PathProgramCache]: Analyzing trace with hash 1748410243, now seen corresponding path program 1 times [2018-11-23 05:46:12,522 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:46:12,522 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:46:12,523 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:12,523 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:12,523 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:12,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:12,684 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-23 05:46:12,684 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:46:12,685 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:46:12,703 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:12,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:12,718 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:12,782 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-23 05:46:12,796 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:46:12,797 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 11] total 13 [2018-11-23 05:46:12,797 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-23 05:46:12,797 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-23 05:46:12,797 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=130, Unknown=0, NotChecked=0, Total=156 [2018-11-23 05:46:12,798 INFO L87 Difference]: Start difference. First operand 85 states and 114 transitions. Second operand 13 states. [2018-11-23 05:46:13,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:13,050 INFO L93 Difference]: Finished difference Result 147 states and 196 transitions. [2018-11-23 05:46:13,052 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-23 05:46:13,052 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 38 [2018-11-23 05:46:13,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:13,053 INFO L225 Difference]: With dead ends: 147 [2018-11-23 05:46:13,053 INFO L226 Difference]: Without dead ends: 111 [2018-11-23 05:46:13,054 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 34 SyntacticMatches, 1 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 50 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=81, Invalid=381, Unknown=0, NotChecked=0, Total=462 [2018-11-23 05:46:13,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-11-23 05:46:13,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 77. [2018-11-23 05:46:13,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-11-23 05:46:13,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 100 transitions. [2018-11-23 05:46:13,063 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 100 transitions. Word has length 38 [2018-11-23 05:46:13,063 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:13,063 INFO L480 AbstractCegarLoop]: Abstraction has 77 states and 100 transitions. [2018-11-23 05:46:13,063 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-23 05:46:13,063 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 100 transitions. [2018-11-23 05:46:13,064 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-23 05:46:13,065 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:13,065 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:13,066 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:13,066 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:13,067 INFO L82 PathProgramCache]: Analyzing trace with hash -977604237, now seen corresponding path program 1 times [2018-11-23 05:46:13,067 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:46:13,067 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:46:13,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:13,068 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:13,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:13,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:13,176 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-23 05:46:13,177 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:13,177 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-23 05:46:13,177 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 05:46:13,177 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 05:46:13,177 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-11-23 05:46:13,177 INFO L87 Difference]: Start difference. First operand 77 states and 100 transitions. Second operand 9 states. [2018-11-23 05:46:13,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:13,246 INFO L93 Difference]: Finished difference Result 122 states and 161 transitions. [2018-11-23 05:46:13,247 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 05:46:13,247 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 42 [2018-11-23 05:46:13,247 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:13,248 INFO L225 Difference]: With dead ends: 122 [2018-11-23 05:46:13,248 INFO L226 Difference]: Without dead ends: 101 [2018-11-23 05:46:13,249 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2018-11-23 05:46:13,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states. [2018-11-23 05:46:13,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 93. [2018-11-23 05:46:13,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2018-11-23 05:46:13,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 123 transitions. [2018-11-23 05:46:13,258 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 123 transitions. Word has length 42 [2018-11-23 05:46:13,258 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:13,259 INFO L480 AbstractCegarLoop]: Abstraction has 93 states and 123 transitions. [2018-11-23 05:46:13,259 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 05:46:13,259 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 123 transitions. [2018-11-23 05:46:13,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-23 05:46:13,260 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:13,260 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:13,260 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:13,261 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:13,261 INFO L82 PathProgramCache]: Analyzing trace with hash -920345935, now seen corresponding path program 1 times [2018-11-23 05:46:13,261 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:46:13,261 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:46:13,261 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:13,261 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:13,262 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:13,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:13,385 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 6 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-23 05:46:13,386 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:46:13,386 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:46:13,395 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:13,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:13,412 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:13,438 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 3 proven. 11 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-23 05:46:13,453 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:46:13,453 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 10] total 11 [2018-11-23 05:46:13,453 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-23 05:46:13,453 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-23 05:46:13,454 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=90, Unknown=0, NotChecked=0, Total=110 [2018-11-23 05:46:13,454 INFO L87 Difference]: Start difference. First operand 93 states and 123 transitions. Second operand 11 states. [2018-11-23 05:46:13,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:13,590 INFO L93 Difference]: Finished difference Result 161 states and 217 transitions. [2018-11-23 05:46:13,590 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-23 05:46:13,591 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 42 [2018-11-23 05:46:13,591 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:13,592 INFO L225 Difference]: With dead ends: 161 [2018-11-23 05:46:13,592 INFO L226 Difference]: Without dead ends: 128 [2018-11-23 05:46:13,593 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 39 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=62, Invalid=244, Unknown=0, NotChecked=0, Total=306 [2018-11-23 05:46:13,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-11-23 05:46:13,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 103. [2018-11-23 05:46:13,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-11-23 05:46:13,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 134 transitions. [2018-11-23 05:46:13,605 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 134 transitions. Word has length 42 [2018-11-23 05:46:13,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:13,605 INFO L480 AbstractCegarLoop]: Abstraction has 103 states and 134 transitions. [2018-11-23 05:46:13,605 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-23 05:46:13,605 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 134 transitions. [2018-11-23 05:46:13,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-23 05:46:13,606 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:13,606 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:13,607 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:13,607 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:13,607 INFO L82 PathProgramCache]: Analyzing trace with hash -774274828, now seen corresponding path program 1 times [2018-11-23 05:46:13,607 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:46:13,607 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:46:13,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:13,608 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:13,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:13,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:13,697 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-23 05:46:13,698 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:13,698 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-23 05:46:13,698 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-23 05:46:13,698 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-23 05:46:13,698 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-11-23 05:46:13,698 INFO L87 Difference]: Start difference. First operand 103 states and 134 transitions. Second operand 10 states. [2018-11-23 05:46:15,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:15,934 INFO L93 Difference]: Finished difference Result 162 states and 222 transitions. [2018-11-23 05:46:15,934 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-23 05:46:15,934 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-11-23 05:46:15,935 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:15,935 INFO L225 Difference]: With dead ends: 162 [2018-11-23 05:46:15,935 INFO L226 Difference]: Without dead ends: 136 [2018-11-23 05:46:15,936 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=149, Unknown=0, NotChecked=0, Total=182 [2018-11-23 05:46:15,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-11-23 05:46:15,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 118. [2018-11-23 05:46:15,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-11-23 05:46:15,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 159 transitions. [2018-11-23 05:46:15,944 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 159 transitions. Word has length 42 [2018-11-23 05:46:15,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:15,945 INFO L480 AbstractCegarLoop]: Abstraction has 118 states and 159 transitions. [2018-11-23 05:46:15,945 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-23 05:46:15,945 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 159 transitions. [2018-11-23 05:46:15,945 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-23 05:46:15,946 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:15,946 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:15,946 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:15,946 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:15,946 INFO L82 PathProgramCache]: Analyzing trace with hash -717016526, now seen corresponding path program 2 times [2018-11-23 05:46:15,946 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:46:15,946 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:46:15,947 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:15,947 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:15,947 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:15,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:16,079 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-23 05:46:16,079 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:16,079 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2018-11-23 05:46:16,079 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-23 05:46:16,080 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-23 05:46:16,080 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=131, Unknown=0, NotChecked=0, Total=156 [2018-11-23 05:46:16,080 INFO L87 Difference]: Start difference. First operand 118 states and 159 transitions. Second operand 13 states. [2018-11-23 05:46:16,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:16,266 INFO L93 Difference]: Finished difference Result 152 states and 204 transitions. [2018-11-23 05:46:16,267 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 05:46:16,267 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 42 [2018-11-23 05:46:16,267 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:16,268 INFO L225 Difference]: With dead ends: 152 [2018-11-23 05:46:16,268 INFO L226 Difference]: Without dead ends: 150 [2018-11-23 05:46:16,269 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=229, Unknown=0, NotChecked=0, Total=272 [2018-11-23 05:46:16,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-11-23 05:46:16,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 129. [2018-11-23 05:46:16,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2018-11-23 05:46:16,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 172 transitions. [2018-11-23 05:46:16,280 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 172 transitions. Word has length 42 [2018-11-23 05:46:16,280 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:16,280 INFO L480 AbstractCegarLoop]: Abstraction has 129 states and 172 transitions. [2018-11-23 05:46:16,280 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-23 05:46:16,280 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 172 transitions. [2018-11-23 05:46:16,281 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-23 05:46:16,281 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:16,281 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:16,281 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:16,282 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:16,282 INFO L82 PathProgramCache]: Analyzing trace with hash 749157176, now seen corresponding path program 1 times [2018-11-23 05:46:16,282 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:46:16,282 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:46:16,282 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:16,283 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:46:16,283 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:16,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:16,370 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-23 05:46:16,370 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:46:16,370 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:46:16,377 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:16,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:16,394 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:16,407 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-23 05:46:16,421 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:46:16,422 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2018-11-23 05:46:16,422 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 05:46:16,422 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 05:46:16,422 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-11-23 05:46:16,422 INFO L87 Difference]: Start difference. First operand 129 states and 172 transitions. Second operand 8 states. [2018-11-23 05:46:16,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:16,476 INFO L93 Difference]: Finished difference Result 200 states and 268 transitions. [2018-11-23 05:46:16,477 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 05:46:16,478 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 42 [2018-11-23 05:46:16,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:16,479 INFO L225 Difference]: With dead ends: 200 [2018-11-23 05:46:16,479 INFO L226 Difference]: Without dead ends: 174 [2018-11-23 05:46:16,479 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 41 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-11-23 05:46:16,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-11-23 05:46:16,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 165. [2018-11-23 05:46:16,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-11-23 05:46:16,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 219 transitions. [2018-11-23 05:46:16,491 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 219 transitions. Word has length 42 [2018-11-23 05:46:16,491 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:16,491 INFO L480 AbstractCegarLoop]: Abstraction has 165 states and 219 transitions. [2018-11-23 05:46:16,491 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 05:46:16,491 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 219 transitions. [2018-11-23 05:46:16,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-23 05:46:16,492 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:16,492 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:16,492 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:16,493 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:16,493 INFO L82 PathProgramCache]: Analyzing trace with hash 806415478, now seen corresponding path program 1 times [2018-11-23 05:46:16,493 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:46:16,493 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:46:16,493 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:16,494 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:16,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:16,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 05:46:16,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 05:46:16,525 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] CALL call ULTIMATE.init(); [?] assume true; [?] RET #141#return; [?] CALL call #t~ret9 := main(); [?] havoc ~a~0;~ma~2 := #t~nondet0;havoc #t~nondet0;assume -128 <= #t~nondet1 && #t~nondet1 <= 127;~ea~2 := #t~nondet1;havoc #t~nondet1;havoc ~b~0;~mb~2 := #t~nondet2;havoc #t~nondet2;assume -128 <= #t~nondet3 && #t~nondet3 <= 127;~eb~2 := #t~nondet3;havoc #t~nondet3;havoc ~r_add1~0;havoc ~r_add2~0;havoc ~zero~0;havoc ~tmp~2;havoc ~tmp___0~0;havoc ~__retres14~0; VAL [main_~ea~2=127, main_~eb~2=0, main_~ma~2=33554432, main_~mb~2=16777216] [?] CALL call #t~ret4 := base2flt(0, 0); VAL [|base2flt_#in~e|=0, |base2flt_#in~m|=0] [?] ~m := #in~m;~e := #in~e;havoc ~res~0;havoc ~__retres4~0; VAL [base2flt_~e=0, base2flt_~m=0, |base2flt_#in~e|=0, |base2flt_#in~m|=0] [?] assume 0 == ~m % 4294967296;~__retres4~0 := 0; VAL [base2flt_~__retres4~0=0, base2flt_~e=0, base2flt_~m=0, |base2flt_#in~e|=0, |base2flt_#in~m|=0] [?] #res := ~__retres4~0; VAL [base2flt_~__retres4~0=0, base2flt_~e=0, base2flt_~m=0, |base2flt_#in~e|=0, |base2flt_#in~m|=0, |base2flt_#res|=0] [?] assume true; VAL [base2flt_~__retres4~0=0, base2flt_~e=0, base2flt_~m=0, |base2flt_#in~e|=0, |base2flt_#in~m|=0, |base2flt_#res|=0] [?] RET #145#return; VAL [main_~ea~2=127, main_~eb~2=0, main_~ma~2=33554432, main_~mb~2=16777216, |main_#t~ret4|=0] [?] ~zero~0 := #t~ret4;havoc #t~ret4; VAL [main_~ea~2=127, main_~eb~2=0, main_~ma~2=33554432, main_~mb~2=16777216, main_~zero~0=0] [?] CALL call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [|base2flt_#in~e|=127, |base2flt_#in~m|=33554432] [?] ~m := #in~m;~e := #in~e;havoc ~res~0;havoc ~__retres4~0; VAL [base2flt_~e=127, base2flt_~m=33554432, |base2flt_#in~e|=127, |base2flt_#in~m|=33554432] [?] assume !(0 == ~m % 4294967296); VAL [base2flt_~e=127, base2flt_~m=33554432, |base2flt_#in~e|=127, |base2flt_#in~m|=33554432] [?] assume !(~m % 4294967296 < 16777216); VAL [base2flt_~e=127, base2flt_~m=33554432, |base2flt_#in~e|=127, |base2flt_#in~m|=33554432] [?] assume !false; VAL [base2flt_~e=127, base2flt_~m=33554432, |base2flt_#in~e|=127, |base2flt_#in~m|=33554432] [?] assume ~m % 4294967296 >= 33554432; VAL [base2flt_~e=127, base2flt_~m=33554432, |base2flt_#in~e|=127, |base2flt_#in~m|=33554432] [?] assume ~e >= 127;~__retres4~0 := 4294967295; VAL [base2flt_~__retres4~0=4294967295, base2flt_~e=127, base2flt_~m=33554432, |base2flt_#in~e|=127, |base2flt_#in~m|=33554432] [?] #res := ~__retres4~0; VAL [base2flt_~__retres4~0=4294967295, base2flt_~e=127, base2flt_~m=33554432, |base2flt_#in~e|=127, |base2flt_#in~m|=33554432, |base2flt_#res|=4294967295] [?] assume true; VAL [base2flt_~__retres4~0=4294967295, base2flt_~e=127, base2flt_~m=33554432, |base2flt_#in~e|=127, |base2flt_#in~m|=33554432, |base2flt_#res|=4294967295] [?] RET #147#return; VAL [main_~ea~2=127, main_~eb~2=0, main_~ma~2=33554432, main_~mb~2=16777216, main_~zero~0=0, |main_#t~ret5|=4294967295] [?] ~a~0 := #t~ret5;havoc #t~ret5; VAL [main_~a~0=4294967295, main_~ea~2=127, main_~eb~2=0, main_~ma~2=33554432, main_~mb~2=16777216, main_~zero~0=0] [?] CALL call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [|base2flt_#in~e|=0, |base2flt_#in~m|=16777216] [?] ~m := #in~m;~e := #in~e;havoc ~res~0;havoc ~__retres4~0; VAL [base2flt_~e=0, base2flt_~m=16777216, |base2flt_#in~e|=0, |base2flt_#in~m|=16777216] [?] assume !(0 == ~m % 4294967296); VAL [base2flt_~e=0, base2flt_~m=16777216, |base2flt_#in~e|=0, |base2flt_#in~m|=16777216] [?] assume !(~m % 4294967296 < 16777216); VAL [base2flt_~e=0, base2flt_~m=16777216, |base2flt_#in~e|=0, |base2flt_#in~m|=16777216] [?] assume !false; VAL [base2flt_~e=0, base2flt_~m=16777216, |base2flt_#in~e|=0, |base2flt_#in~m|=16777216] [?] assume !(~m % 4294967296 >= 33554432); VAL [base2flt_~e=0, base2flt_~m=16777216, |base2flt_#in~e|=0, |base2flt_#in~m|=16777216] [?] ~m := ~bitwiseAnd(~m, ~bitwiseComplement(16777216));~res~0 := ~bitwiseOr(~m, 16777216 * (128 + ~e));~__retres4~0 := ~res~0; VAL [base2flt_~__retres4~0=36028797002186752, base2flt_~e=0, base2flt_~res~0=36028797002186752, |base2flt_#in~e|=0, |base2flt_#in~m|=16777216] [?] #res := ~__retres4~0; VAL [base2flt_~__retres4~0=36028797002186752, base2flt_~e=0, base2flt_~res~0=36028797002186752, |base2flt_#in~e|=0, |base2flt_#in~m|=16777216, |base2flt_#res|=36028797002186752] [?] assume true; VAL [base2flt_~__retres4~0=36028797002186752, base2flt_~e=0, base2flt_~res~0=36028797002186752, |base2flt_#in~e|=0, |base2flt_#in~m|=16777216, |base2flt_#res|=36028797002186752] [?] RET #149#return; VAL [main_~a~0=4294967295, main_~ea~2=127, main_~eb~2=0, main_~ma~2=33554432, main_~mb~2=16777216, main_~zero~0=0, |main_#t~ret6|=36028797002186752] [?] ~b~0 := #t~ret6;havoc #t~ret6; VAL [main_~a~0=4294967295, main_~b~0=36028797002186752, main_~ea~2=127, main_~eb~2=0, main_~ma~2=33554432, main_~mb~2=16777216, main_~zero~0=0] [?] CALL call #t~ret7 := addflt(~a~0, ~b~0); VAL [|addflt_#in~a|=4294967295, |addflt_#in~b|=36028797002186752] [?] ~a := #in~a;~b := #in~b;havoc ~res~1;havoc ~ma~0;havoc ~mb~0;havoc ~delta~0;havoc ~ea~0;havoc ~eb~0;havoc ~tmp~0;havoc ~__retres10~0; VAL [addflt_~a=4294967295, addflt_~b=36028797002186752, |addflt_#in~a|=4294967295, |addflt_#in~b|=36028797002186752] [?] assume !(~a % 4294967296 < ~b % 4294967296); VAL [addflt_~a=4294967295, addflt_~b=36028797002186752, |addflt_#in~a|=4294967295, |addflt_#in~b|=36028797002186752] [?] assume !(0 == ~b % 4294967296);~ma~0 := ~bitwiseAnd(~a, 16777215);~ea~0 := (if ~a / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~a / 16777216 % 4294967296 % 4294967296 else ~a / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128;~ma~0 := ~bitwiseOr(~ma~0, 16777216);~mb~0 := ~bitwiseAnd(~b, 16777215);~eb~0 := (if ~b / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~b / 16777216 % 4294967296 % 4294967296 else ~b / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128;~mb~0 := ~bitwiseOr(~mb~0, 16777216); VAL [addflt_~a=4294967295, addflt_~b=36028797002186752, addflt_~ea~0=127, addflt_~eb~0=2147483519, |addflt_#in~a|=4294967295, |addflt_#in~b|=36028797002186752] [?] CALL call __VERIFIER_assert((if ~ea~0 >= ~eb~0 then 1 else 0)); VAL [|__VERIFIER_assert_#in~cond|=0] [?] ~cond := #in~cond; VAL [__VERIFIER_assert_~cond=0, |__VERIFIER_assert_#in~cond|=0] [?] assume 0 == ~cond; VAL [__VERIFIER_assert_~cond=0, |__VERIFIER_assert_#in~cond|=0] [?] assume !false; VAL [__VERIFIER_assert_~cond=0, |__VERIFIER_assert_#in~cond|=0] [?] CALL call ULTIMATE.init(); [?] ensures true; [?] RET call ULTIMATE.init(); [?] CALL call #t~ret9 := main(); [L215] havoc ~a~0; [L216] ~ma~2 := #t~nondet0; [L216] havoc #t~nondet0; [L217] assume -128 <= #t~nondet1 && #t~nondet1 <= 127; [L217] ~ea~2 := #t~nondet1; [L217] havoc #t~nondet1; [L218] havoc ~b~0; [L219] ~mb~2 := #t~nondet2; [L219] havoc #t~nondet2; [L220] assume -128 <= #t~nondet3 && #t~nondet3 <= 127; [L220] ~eb~2 := #t~nondet3; [L220] havoc #t~nondet3; [L221] havoc ~r_add1~0; [L222] havoc ~r_add2~0; [L223] havoc ~zero~0; [L224] havoc ~tmp~2; [L225] havoc ~tmp___0~0; [L226] havoc ~__retres14~0; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] CALL call #t~ret4 := base2flt(0, 0); VAL [#in~e=0, #in~m=0] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=0, ~e=0, ~m=0] [L19-L24] assume 0 == ~m % 4294967296; [L20] ~__retres4~0 := 0; VAL [#in~e=0, #in~m=0, ~__retres4~0=0, ~e=0, ~m=0] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=0, #res=0, ~__retres4~0=0, ~e=0, ~m=0] [L14-L72] ensures true; VAL [#in~e=0, #in~m=0, #res=0, ~__retres4~0=0, ~e=0, ~m=0] [L230] RET call #t~ret4 := base2flt(0, 0); VAL [#t~ret4=0, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] ~zero~0 := #t~ret4; [L230] havoc #t~ret4; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] CALL call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#in~e=127, #in~m=33554432] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L19-L24] assume !(0 == ~m % 4294967296); VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L25-L65] assume !(~m % 4294967296 < 16777216); VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L47-L62] assume !false; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L49-L53] assume ~m % 4294967296 >= 33554432; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L54-L59] assume ~e >= 127; [L55] ~__retres4~0 := 4294967295; VAL [#in~e=127, #in~m=33554432, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L70] #res := ~__retres4~0; VAL [#in~e=127, #in~m=33554432, #res=4294967295, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L14-L72] ensures true; VAL [#in~e=127, #in~m=33554432, #res=4294967295, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L231] RET call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#t~ret5=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] ~a~0 := #t~ret5; [L231] havoc #t~ret5; VAL [~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] CALL call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#in~e=0, #in~m=16777216] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L19-L24] assume !(0 == ~m % 4294967296); VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L25-L65] assume !(~m % 4294967296 < 16777216); VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L47-L62] assume !false; VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L49-L53] assume !(~m % 4294967296 >= 33554432); VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L66] ~m := ~bitwiseAnd(~m, ~bitwiseComplement(16777216)); [L67] ~res~0 := ~bitwiseOr(~m, 16777216 * (128 + ~e)); [L68] ~__retres4~0 := ~res~0; VAL [#in~e=0, #in~m=16777216, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=16777216, #res=36028797002186752, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L14-L72] ensures true; VAL [#in~e=0, #in~m=16777216, #res=36028797002186752, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L232] RET call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#t~ret6=36028797002186752, ~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] ~b~0 := #t~ret6; [L232] havoc #t~ret6; VAL [~a~0=4294967295, ~b~0=36028797002186752, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L233] CALL call #t~ret7 := addflt(~a~0, ~b~0); VAL [#in~a=4294967295, #in~b=36028797002186752] [L73-L136] ~a := #in~a; [L73-L136] ~b := #in~b; [L74] havoc ~res~1; [L75] havoc ~ma~0; [L76] havoc ~mb~0; [L77] havoc ~delta~0; [L78] havoc ~ea~0; [L79] havoc ~eb~0; [L80] havoc ~tmp~0; [L81] havoc ~__retres10~0; VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L84-L90] assume !(~a % 4294967296 < ~b % 4294967296); VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L91-L96] assume !(0 == ~b % 4294967296); [L98] ~ma~0 := ~bitwiseAnd(~a, 16777215); [L99] ~ea~0 := (if ~a / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~a / 16777216 % 4294967296 % 4294967296 else ~a / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L100] ~ma~0 := ~bitwiseOr(~ma~0, 16777216); [L101] ~mb~0 := ~bitwiseAnd(~b, 16777215); [L102] ~eb~0 := (if ~b / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~b / 16777216 % 4294967296 % 4294967296 else ~b / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L103] ~mb~0 := ~bitwiseOr(~mb~0, 16777216); VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752, ~ea~0=127, ~eb~0=2147483519] [L104] CALL call __VERIFIER_assert((if ~ea~0 >= ~eb~0 then 1 else 0)); VAL [#in~cond=0] [L5-L10] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L6-L8] assume 0 == ~cond; VAL [#in~cond=0, ~cond=0] [L7] assert false; VAL [#in~cond=0, ~cond=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] CALL call ULTIMATE.init(); [?] ensures true; [?] RET call ULTIMATE.init(); [?] CALL call #t~ret9 := main(); [L215] havoc ~a~0; [L216] ~ma~2 := #t~nondet0; [L216] havoc #t~nondet0; [L217] assume -128 <= #t~nondet1 && #t~nondet1 <= 127; [L217] ~ea~2 := #t~nondet1; [L217] havoc #t~nondet1; [L218] havoc ~b~0; [L219] ~mb~2 := #t~nondet2; [L219] havoc #t~nondet2; [L220] assume -128 <= #t~nondet3 && #t~nondet3 <= 127; [L220] ~eb~2 := #t~nondet3; [L220] havoc #t~nondet3; [L221] havoc ~r_add1~0; [L222] havoc ~r_add2~0; [L223] havoc ~zero~0; [L224] havoc ~tmp~2; [L225] havoc ~tmp___0~0; [L226] havoc ~__retres14~0; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] CALL call #t~ret4 := base2flt(0, 0); VAL [#in~e=0, #in~m=0] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=0, ~e=0, ~m=0] [L19-L24] assume 0 == ~m % 4294967296; [L20] ~__retres4~0 := 0; VAL [#in~e=0, #in~m=0, ~__retres4~0=0, ~e=0, ~m=0] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=0, #res=0, ~__retres4~0=0, ~e=0, ~m=0] [L14-L72] ensures true; VAL [#in~e=0, #in~m=0, #res=0, ~__retres4~0=0, ~e=0, ~m=0] [L230] RET call #t~ret4 := base2flt(0, 0); VAL [#t~ret4=0, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] ~zero~0 := #t~ret4; [L230] havoc #t~ret4; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] CALL call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#in~e=127, #in~m=33554432] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L19-L24] assume !(0 == ~m % 4294967296); VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L25-L65] assume !(~m % 4294967296 < 16777216); VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L47-L62] assume !false; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L49-L53] assume ~m % 4294967296 >= 33554432; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L54-L59] assume ~e >= 127; [L55] ~__retres4~0 := 4294967295; VAL [#in~e=127, #in~m=33554432, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L70] #res := ~__retres4~0; VAL [#in~e=127, #in~m=33554432, #res=4294967295, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L14-L72] ensures true; VAL [#in~e=127, #in~m=33554432, #res=4294967295, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L231] RET call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#t~ret5=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] ~a~0 := #t~ret5; [L231] havoc #t~ret5; VAL [~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] CALL call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#in~e=0, #in~m=16777216] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L19-L24] assume !(0 == ~m % 4294967296); VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L25-L65] assume !(~m % 4294967296 < 16777216); VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L47-L62] assume !false; VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L49-L53] assume !(~m % 4294967296 >= 33554432); VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L66] ~m := ~bitwiseAnd(~m, ~bitwiseComplement(16777216)); [L67] ~res~0 := ~bitwiseOr(~m, 16777216 * (128 + ~e)); [L68] ~__retres4~0 := ~res~0; VAL [#in~e=0, #in~m=16777216, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=16777216, #res=36028797002186752, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L14-L72] ensures true; VAL [#in~e=0, #in~m=16777216, #res=36028797002186752, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L232] RET call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#t~ret6=36028797002186752, ~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] ~b~0 := #t~ret6; [L232] havoc #t~ret6; VAL [~a~0=4294967295, ~b~0=36028797002186752, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L233] CALL call #t~ret7 := addflt(~a~0, ~b~0); VAL [#in~a=4294967295, #in~b=36028797002186752] [L73-L136] ~a := #in~a; [L73-L136] ~b := #in~b; [L74] havoc ~res~1; [L75] havoc ~ma~0; [L76] havoc ~mb~0; [L77] havoc ~delta~0; [L78] havoc ~ea~0; [L79] havoc ~eb~0; [L80] havoc ~tmp~0; [L81] havoc ~__retres10~0; VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L84-L90] assume !(~a % 4294967296 < ~b % 4294967296); VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L91-L96] assume !(0 == ~b % 4294967296); [L98] ~ma~0 := ~bitwiseAnd(~a, 16777215); [L99] ~ea~0 := (if ~a / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~a / 16777216 % 4294967296 % 4294967296 else ~a / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L100] ~ma~0 := ~bitwiseOr(~ma~0, 16777216); [L101] ~mb~0 := ~bitwiseAnd(~b, 16777215); [L102] ~eb~0 := (if ~b / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~b / 16777216 % 4294967296 % 4294967296 else ~b / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L103] ~mb~0 := ~bitwiseOr(~mb~0, 16777216); VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752, ~ea~0=127, ~eb~0=2147483519] [L104] CALL call __VERIFIER_assert((if ~ea~0 >= ~eb~0 then 1 else 0)); VAL [#in~cond=0] [L5-L10] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L6-L8] assume 0 == ~cond; VAL [#in~cond=0, ~cond=0] [L7] assert false; VAL [#in~cond=0, ~cond=0] [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret9 := main(); [L215] havoc ~a~0; [L216] ~ma~2 := #t~nondet0; [L216] havoc #t~nondet0; [L217] assume -128 <= #t~nondet1 && #t~nondet1 <= 127; [L217] ~ea~2 := #t~nondet1; [L217] havoc #t~nondet1; [L218] havoc ~b~0; [L219] ~mb~2 := #t~nondet2; [L219] havoc #t~nondet2; [L220] assume -128 <= #t~nondet3 && #t~nondet3 <= 127; [L220] ~eb~2 := #t~nondet3; [L220] havoc #t~nondet3; [L221] havoc ~r_add1~0; [L222] havoc ~r_add2~0; [L223] havoc ~zero~0; [L224] havoc ~tmp~2; [L225] havoc ~tmp___0~0; [L226] havoc ~__retres14~0; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] CALL call #t~ret4 := base2flt(0, 0); VAL [#in~e=0, #in~m=0] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=0, ~e=0, ~m=0] [L19] COND TRUE 0 == ~m % 4294967296 [L20] ~__retres4~0 := 0; VAL [#in~e=0, #in~m=0, ~__retres4~0=0, ~e=0, ~m=0] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=0, #res=0, ~__retres4~0=0, ~e=0, ~m=0] [L230] RET call #t~ret4 := base2flt(0, 0); VAL [#t~ret4=0, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] ~zero~0 := #t~ret4; [L230] havoc #t~ret4; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] CALL call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#in~e=127, #in~m=33554432] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L19] COND FALSE !(0 == ~m % 4294967296) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L25] COND FALSE !(~m % 4294967296 < 16777216) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L47-L62] COND FALSE !(false) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L49] COND TRUE ~m % 4294967296 >= 33554432 VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L54] COND TRUE ~e >= 127 [L55] ~__retres4~0 := 4294967295; VAL [#in~e=127, #in~m=33554432, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L70] #res := ~__retres4~0; VAL [#in~e=127, #in~m=33554432, #res=4294967295, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L231] RET call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#t~ret5=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] ~a~0 := #t~ret5; [L231] havoc #t~ret5; VAL [~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] CALL call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#in~e=0, #in~m=16777216] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L19] COND FALSE !(0 == ~m % 4294967296) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L25] COND FALSE !(~m % 4294967296 < 16777216) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L47-L62] COND FALSE !(false) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L49] COND FALSE !(~m % 4294967296 >= 33554432) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L66] ~m := ~bitwiseAnd(~m, ~bitwiseComplement(16777216)); [L67] ~res~0 := ~bitwiseOr(~m, 16777216 * (128 + ~e)); [L68] ~__retres4~0 := ~res~0; VAL [#in~e=0, #in~m=16777216, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=16777216, #res=36028797002186752, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L232] RET call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#t~ret6=36028797002186752, ~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] ~b~0 := #t~ret6; [L232] havoc #t~ret6; VAL [~a~0=4294967295, ~b~0=36028797002186752, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L233] CALL call #t~ret7 := addflt(~a~0, ~b~0); VAL [#in~a=4294967295, #in~b=36028797002186752] [L73-L136] ~a := #in~a; [L73-L136] ~b := #in~b; [L74] havoc ~res~1; [L75] havoc ~ma~0; [L76] havoc ~mb~0; [L77] havoc ~delta~0; [L78] havoc ~ea~0; [L79] havoc ~eb~0; [L80] havoc ~tmp~0; [L81] havoc ~__retres10~0; VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L84] COND FALSE !(~a % 4294967296 < ~b % 4294967296) VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L91] COND FALSE !(0 == ~b % 4294967296) [L98] ~ma~0 := ~bitwiseAnd(~a, 16777215); [L99] ~ea~0 := (if ~a / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~a / 16777216 % 4294967296 % 4294967296 else ~a / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L100] ~ma~0 := ~bitwiseOr(~ma~0, 16777216); [L101] ~mb~0 := ~bitwiseAnd(~b, 16777215); [L102] ~eb~0 := (if ~b / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~b / 16777216 % 4294967296 % 4294967296 else ~b / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L103] ~mb~0 := ~bitwiseOr(~mb~0, 16777216); VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752, ~ea~0=127, ~eb~0=2147483519] [L104] CALL call __VERIFIER_assert((if ~ea~0 >= ~eb~0 then 1 else 0)); VAL [#in~cond=0] [L5-L10] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L6] COND TRUE 0 == ~cond VAL [#in~cond=0, ~cond=0] [L7] assert false; VAL [#in~cond=0, ~cond=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret9 := main(); [L215] havoc ~a~0; [L216] ~ma~2 := #t~nondet0; [L216] havoc #t~nondet0; [L217] assume -128 <= #t~nondet1 && #t~nondet1 <= 127; [L217] ~ea~2 := #t~nondet1; [L217] havoc #t~nondet1; [L218] havoc ~b~0; [L219] ~mb~2 := #t~nondet2; [L219] havoc #t~nondet2; [L220] assume -128 <= #t~nondet3 && #t~nondet3 <= 127; [L220] ~eb~2 := #t~nondet3; [L220] havoc #t~nondet3; [L221] havoc ~r_add1~0; [L222] havoc ~r_add2~0; [L223] havoc ~zero~0; [L224] havoc ~tmp~2; [L225] havoc ~tmp___0~0; [L226] havoc ~__retres14~0; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] CALL call #t~ret4 := base2flt(0, 0); VAL [#in~e=0, #in~m=0] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=0, ~e=0, ~m=0] [L19] COND TRUE 0 == ~m % 4294967296 [L20] ~__retres4~0 := 0; VAL [#in~e=0, #in~m=0, ~__retres4~0=0, ~e=0, ~m=0] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=0, #res=0, ~__retres4~0=0, ~e=0, ~m=0] [L230] RET call #t~ret4 := base2flt(0, 0); VAL [#t~ret4=0, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] ~zero~0 := #t~ret4; [L230] havoc #t~ret4; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] CALL call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#in~e=127, #in~m=33554432] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L19] COND FALSE !(0 == ~m % 4294967296) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L25] COND FALSE !(~m % 4294967296 < 16777216) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L47-L62] COND FALSE !(false) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L49] COND TRUE ~m % 4294967296 >= 33554432 VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L54] COND TRUE ~e >= 127 [L55] ~__retres4~0 := 4294967295; VAL [#in~e=127, #in~m=33554432, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L70] #res := ~__retres4~0; VAL [#in~e=127, #in~m=33554432, #res=4294967295, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L231] RET call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#t~ret5=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] ~a~0 := #t~ret5; [L231] havoc #t~ret5; VAL [~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] CALL call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#in~e=0, #in~m=16777216] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L19] COND FALSE !(0 == ~m % 4294967296) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L25] COND FALSE !(~m % 4294967296 < 16777216) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L47-L62] COND FALSE !(false) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L49] COND FALSE !(~m % 4294967296 >= 33554432) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L66] ~m := ~bitwiseAnd(~m, ~bitwiseComplement(16777216)); [L67] ~res~0 := ~bitwiseOr(~m, 16777216 * (128 + ~e)); [L68] ~__retres4~0 := ~res~0; VAL [#in~e=0, #in~m=16777216, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=16777216, #res=36028797002186752, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L232] RET call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#t~ret6=36028797002186752, ~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] ~b~0 := #t~ret6; [L232] havoc #t~ret6; VAL [~a~0=4294967295, ~b~0=36028797002186752, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L233] CALL call #t~ret7 := addflt(~a~0, ~b~0); VAL [#in~a=4294967295, #in~b=36028797002186752] [L73-L136] ~a := #in~a; [L73-L136] ~b := #in~b; [L74] havoc ~res~1; [L75] havoc ~ma~0; [L76] havoc ~mb~0; [L77] havoc ~delta~0; [L78] havoc ~ea~0; [L79] havoc ~eb~0; [L80] havoc ~tmp~0; [L81] havoc ~__retres10~0; VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L84] COND FALSE !(~a % 4294967296 < ~b % 4294967296) VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L91] COND FALSE !(0 == ~b % 4294967296) [L98] ~ma~0 := ~bitwiseAnd(~a, 16777215); [L99] ~ea~0 := (if ~a / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~a / 16777216 % 4294967296 % 4294967296 else ~a / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L100] ~ma~0 := ~bitwiseOr(~ma~0, 16777216); [L101] ~mb~0 := ~bitwiseAnd(~b, 16777215); [L102] ~eb~0 := (if ~b / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~b / 16777216 % 4294967296 % 4294967296 else ~b / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L103] ~mb~0 := ~bitwiseOr(~mb~0, 16777216); VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752, ~ea~0=127, ~eb~0=2147483519] [L104] CALL call __VERIFIER_assert((if ~ea~0 >= ~eb~0 then 1 else 0)); VAL [#in~cond=0] [L5-L10] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L6] COND TRUE 0 == ~cond VAL [#in~cond=0, ~cond=0] [L7] assert false; VAL [#in~cond=0, ~cond=0] [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret9 := main(); [L215] havoc ~a~0; [L216] ~ma~2 := #t~nondet0; [L216] havoc #t~nondet0; [L217] assume -128 <= #t~nondet1 && #t~nondet1 <= 127; [L217] ~ea~2 := #t~nondet1; [L217] havoc #t~nondet1; [L218] havoc ~b~0; [L219] ~mb~2 := #t~nondet2; [L219] havoc #t~nondet2; [L220] assume -128 <= #t~nondet3 && #t~nondet3 <= 127; [L220] ~eb~2 := #t~nondet3; [L220] havoc #t~nondet3; [L221] havoc ~r_add1~0; [L222] havoc ~r_add2~0; [L223] havoc ~zero~0; [L224] havoc ~tmp~2; [L225] havoc ~tmp___0~0; [L226] havoc ~__retres14~0; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] CALL call #t~ret4 := base2flt(0, 0); VAL [#in~e=0, #in~m=0] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=0, ~e=0, ~m=0] [L19] COND TRUE 0 == ~m % 4294967296 [L20] ~__retres4~0 := 0; VAL [#in~e=0, #in~m=0, ~__retres4~0=0, ~e=0, ~m=0] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=0, #res=0, ~__retres4~0=0, ~e=0, ~m=0] [L230] RET call #t~ret4 := base2flt(0, 0); VAL [#t~ret4=0, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] ~zero~0 := #t~ret4; [L230] havoc #t~ret4; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] CALL call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#in~e=127, #in~m=33554432] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L19] COND FALSE !(0 == ~m % 4294967296) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L25] COND FALSE !(~m % 4294967296 < 16777216) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L47-L62] COND FALSE !(false) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L49] COND TRUE ~m % 4294967296 >= 33554432 VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L54] COND TRUE ~e >= 127 [L55] ~__retres4~0 := 4294967295; VAL [#in~e=127, #in~m=33554432, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L70] #res := ~__retres4~0; VAL [#in~e=127, #in~m=33554432, #res=4294967295, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L231] RET call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#t~ret5=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] ~a~0 := #t~ret5; [L231] havoc #t~ret5; VAL [~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] CALL call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#in~e=0, #in~m=16777216] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L19] COND FALSE !(0 == ~m % 4294967296) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L25] COND FALSE !(~m % 4294967296 < 16777216) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L47-L62] COND FALSE !(false) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L49] COND FALSE !(~m % 4294967296 >= 33554432) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L66] ~m := ~bitwiseAnd(~m, ~bitwiseComplement(16777216)); [L67] ~res~0 := ~bitwiseOr(~m, 16777216 * (128 + ~e)); [L68] ~__retres4~0 := ~res~0; VAL [#in~e=0, #in~m=16777216, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=16777216, #res=36028797002186752, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L232] RET call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#t~ret6=36028797002186752, ~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] ~b~0 := #t~ret6; [L232] havoc #t~ret6; VAL [~a~0=4294967295, ~b~0=36028797002186752, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L233] CALL call #t~ret7 := addflt(~a~0, ~b~0); VAL [#in~a=4294967295, #in~b=36028797002186752] [L73-L136] ~a := #in~a; [L73-L136] ~b := #in~b; [L74] havoc ~res~1; [L75] havoc ~ma~0; [L76] havoc ~mb~0; [L77] havoc ~delta~0; [L78] havoc ~ea~0; [L79] havoc ~eb~0; [L80] havoc ~tmp~0; [L81] havoc ~__retres10~0; VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L84] COND FALSE !(~a % 4294967296 < ~b % 4294967296) VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L91] COND FALSE !(0 == ~b % 4294967296) [L98] ~ma~0 := ~bitwiseAnd(~a, 16777215); [L99] ~ea~0 := (if ~a / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~a / 16777216 % 4294967296 % 4294967296 else ~a / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L100] ~ma~0 := ~bitwiseOr(~ma~0, 16777216); [L101] ~mb~0 := ~bitwiseAnd(~b, 16777215); [L102] ~eb~0 := (if ~b / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~b / 16777216 % 4294967296 % 4294967296 else ~b / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L103] ~mb~0 := ~bitwiseOr(~mb~0, 16777216); VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752, ~ea~0=127, ~eb~0=2147483519] [L104] CALL call __VERIFIER_assert((if ~ea~0 >= ~eb~0 then 1 else 0)); VAL [#in~cond=0] [L5-L10] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L6] COND TRUE 0 == ~cond VAL [#in~cond=0, ~cond=0] [L7] assert false; VAL [#in~cond=0, ~cond=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret9 := main(); [L215] havoc ~a~0; [L216] ~ma~2 := #t~nondet0; [L216] havoc #t~nondet0; [L217] assume -128 <= #t~nondet1 && #t~nondet1 <= 127; [L217] ~ea~2 := #t~nondet1; [L217] havoc #t~nondet1; [L218] havoc ~b~0; [L219] ~mb~2 := #t~nondet2; [L219] havoc #t~nondet2; [L220] assume -128 <= #t~nondet3 && #t~nondet3 <= 127; [L220] ~eb~2 := #t~nondet3; [L220] havoc #t~nondet3; [L221] havoc ~r_add1~0; [L222] havoc ~r_add2~0; [L223] havoc ~zero~0; [L224] havoc ~tmp~2; [L225] havoc ~tmp___0~0; [L226] havoc ~__retres14~0; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] CALL call #t~ret4 := base2flt(0, 0); VAL [#in~e=0, #in~m=0] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=0, ~e=0, ~m=0] [L19] COND TRUE 0 == ~m % 4294967296 [L20] ~__retres4~0 := 0; VAL [#in~e=0, #in~m=0, ~__retres4~0=0, ~e=0, ~m=0] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=0, #res=0, ~__retres4~0=0, ~e=0, ~m=0] [L230] RET call #t~ret4 := base2flt(0, 0); VAL [#t~ret4=0, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] ~zero~0 := #t~ret4; [L230] havoc #t~ret4; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] CALL call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#in~e=127, #in~m=33554432] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L19] COND FALSE !(0 == ~m % 4294967296) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L25] COND FALSE !(~m % 4294967296 < 16777216) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L47-L62] COND FALSE !(false) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L49] COND TRUE ~m % 4294967296 >= 33554432 VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L54] COND TRUE ~e >= 127 [L55] ~__retres4~0 := 4294967295; VAL [#in~e=127, #in~m=33554432, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L70] #res := ~__retres4~0; VAL [#in~e=127, #in~m=33554432, #res=4294967295, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L231] RET call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#t~ret5=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] ~a~0 := #t~ret5; [L231] havoc #t~ret5; VAL [~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] CALL call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#in~e=0, #in~m=16777216] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L19] COND FALSE !(0 == ~m % 4294967296) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L25] COND FALSE !(~m % 4294967296 < 16777216) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L47-L62] COND FALSE !(false) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L49] COND FALSE !(~m % 4294967296 >= 33554432) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L66] ~m := ~bitwiseAnd(~m, ~bitwiseComplement(16777216)); [L67] ~res~0 := ~bitwiseOr(~m, 16777216 * (128 + ~e)); [L68] ~__retres4~0 := ~res~0; VAL [#in~e=0, #in~m=16777216, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=16777216, #res=36028797002186752, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L232] RET call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#t~ret6=36028797002186752, ~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] ~b~0 := #t~ret6; [L232] havoc #t~ret6; VAL [~a~0=4294967295, ~b~0=36028797002186752, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L233] CALL call #t~ret7 := addflt(~a~0, ~b~0); VAL [#in~a=4294967295, #in~b=36028797002186752] [L73-L136] ~a := #in~a; [L73-L136] ~b := #in~b; [L74] havoc ~res~1; [L75] havoc ~ma~0; [L76] havoc ~mb~0; [L77] havoc ~delta~0; [L78] havoc ~ea~0; [L79] havoc ~eb~0; [L80] havoc ~tmp~0; [L81] havoc ~__retres10~0; VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L84] COND FALSE !(~a % 4294967296 < ~b % 4294967296) VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L91] COND FALSE !(0 == ~b % 4294967296) [L98] ~ma~0 := ~bitwiseAnd(~a, 16777215); [L99] ~ea~0 := (if ~a / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~a / 16777216 % 4294967296 % 4294967296 else ~a / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L100] ~ma~0 := ~bitwiseOr(~ma~0, 16777216); [L101] ~mb~0 := ~bitwiseAnd(~b, 16777215); [L102] ~eb~0 := (if ~b / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~b / 16777216 % 4294967296 % 4294967296 else ~b / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L103] ~mb~0 := ~bitwiseOr(~mb~0, 16777216); VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752, ~ea~0=127, ~eb~0=2147483519] [L104] CALL call __VERIFIER_assert((if ~ea~0 >= ~eb~0 then 1 else 0)); VAL [#in~cond=0] [L5-L10] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L6] COND TRUE 0 == ~cond VAL [#in~cond=0, ~cond=0] [L7] assert false; VAL [#in~cond=0, ~cond=0] [L215] unsigned int a ; [L216] unsigned int ma = __VERIFIER_nondet_uint(); [L217] signed char ea = __VERIFIER_nondet_char(); [L218] unsigned int b ; [L219] unsigned int mb = __VERIFIER_nondet_uint(); [L220] signed char eb = __VERIFIER_nondet_char(); [L221] unsigned int r_add1 ; [L222] unsigned int r_add2 ; [L223] unsigned int zero ; [L224] int tmp ; [L225] int tmp___0 ; [L226] int __retres14 ; VAL [ea=127, eb=0, ma=33554432, mb=16777216] [L230] CALL, EXPR base2flt(0, 0) VAL [\old(e)=0, \old(m)=0] [L15] unsigned int res ; [L16] unsigned int __retres4 ; VAL [\old(e)=0, \old(m)=0, e=0, m=0] [L19] COND TRUE ! m [L20] __retres4 = 0U VAL [\old(e)=0, \old(m)=0, __retres4=0, e=0, m=0] [L70] return (__retres4); VAL [\old(e)=0, \old(m)=0, \result=0, __retres4=0, e=0, m=0] [L230] RET, EXPR base2flt(0, 0) VAL [base2flt(0, 0)=0, ea=127, eb=0, ma=33554432, mb=16777216] [L230] zero = base2flt(0, 0) [L231] CALL, EXPR base2flt(ma, ea) VAL [\old(e)=127, \old(m)=33554432] [L15] unsigned int res ; [L16] unsigned int __retres4 ; VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L19] COND FALSE !(! m) VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L25] COND FALSE !(m < 1U << 24U) VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L47] COND TRUE 1 VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L49] COND TRUE m >= 1U << 25U VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L54] COND TRUE e >= 127 [L55] __retres4 = 4294967295U VAL [\old(e)=127, \old(m)=33554432, __retres4=4294967295, e=127, m=33554432] [L70] return (__retres4); VAL [\old(e)=127, \old(m)=33554432, \result=4294967295, __retres4=4294967295, e=127, m=33554432] [L231] RET, EXPR base2flt(ma, ea) VAL [base2flt(ma, ea)=4294967295, ea=127, eb=0, ma=33554432, mb=16777216, zero=0] [L231] a = base2flt(ma, ea) [L232] CALL, EXPR base2flt(mb, eb) VAL [\old(e)=0, \old(m)=16777216] [L15] unsigned int res ; [L16] unsigned int __retres4 ; VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L19] COND FALSE !(! m) VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L25] COND FALSE !(m < 1U << 24U) VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L47] COND TRUE 1 VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L49] COND FALSE !(m >= 1U << 25U) VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L66] m = m & ~ (1U << 24U) [L67] res = m | (unsigned int )((e + 128) << 24U) [L68] __retres4 = res VAL [\old(e)=0, \old(m)=16777216, __retres4=4278190080, e=0, res=4278190080] [L70] return (__retres4); VAL [\old(e)=0, \old(m)=16777216, \result=36028797002186752, __retres4=4278190080, e=0, res=4278190080] [L232] RET, EXPR base2flt(mb, eb) VAL [a=4294967295, base2flt(mb, eb)=36028797002186752, ea=127, eb=0, ma=33554432, mb=16777216, zero=0] [L232] b = base2flt(mb, eb) [L233] CALL addflt(a, b) VAL [\old(a)=4294967295, \old(b)=4278190080] [L74] unsigned int res ; [L75] unsigned int ma ; [L76] unsigned int mb ; [L77] unsigned int delta ; [L78] int ea ; [L79] int eb ; [L80] unsigned int tmp ; [L81] unsigned int __retres10 ; VAL [\old(a)=4294967295, \old(b)=4278190080, a=4294967295, b=4278190080] [L84] COND FALSE !(a < b) VAL [\old(a)=4294967295, \old(b)=4278190080, a=4294967295, b=4278190080] [L91] COND FALSE !(! b) [L98] ma = a & ((1U << 24U) - 1U) [L99] ea = (int )(a >> 24U) - 128 [L100] ma = ma | (1U << 24U) [L101] mb = b & ((1U << 24U) - 1U) [L102] eb = (int )(b >> 24U) - 128 [L103] mb = mb | (1U << 24U) VAL [\old(a)=4294967295, \old(b)=4278190080, a=4294967295, b=4278190080, ea=127, eb=2147483519] [L104] CALL __VERIFIER_assert(ea >= eb) VAL [\old(cond)=0] [L6] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L7] __VERIFIER_error() VAL [\old(cond)=0, cond=0] ----- [2018-11-23 05:46:16,566 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 05:46:16 BoogieIcfgContainer [2018-11-23 05:46:16,566 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 05:46:16,567 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 05:46:16,567 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 05:46:16,567 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 05:46:16,567 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:46:11" (3/4) ... [2018-11-23 05:46:16,570 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-11-23 05:46:16,570 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 05:46:16,571 INFO L168 Benchmark]: Toolchain (without parser) took 5699.82 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 243.8 MB). Free memory was 958.1 MB in the beginning and 995.9 MB in the end (delta: -37.9 MB). Peak memory consumption was 205.9 MB. Max. memory is 11.5 GB. [2018-11-23 05:46:16,572 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 05:46:16,573 INFO L168 Benchmark]: CACSL2BoogieTranslator took 234.51 ms. Allocated memory is still 1.0 GB. Free memory was 958.1 MB in the beginning and 941.9 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-23 05:46:16,573 INFO L168 Benchmark]: Boogie Procedure Inliner took 69.16 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 195.6 MB). Free memory was 941.9 MB in the beginning and 1.2 GB in the end (delta: -249.0 MB). Peak memory consumption was 14.3 MB. Max. memory is 11.5 GB. [2018-11-23 05:46:16,573 INFO L168 Benchmark]: Boogie Preprocessor took 22.78 ms. Allocated memory is still 1.2 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 05:46:16,574 INFO L168 Benchmark]: RCFGBuilder took 204.97 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 20.3 MB). Peak memory consumption was 20.3 MB. Max. memory is 11.5 GB. [2018-11-23 05:46:16,574 INFO L168 Benchmark]: TraceAbstraction took 5161.67 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 48.2 MB). Free memory was 1.2 GB in the beginning and 995.9 MB in the end (delta: 174.8 MB). Peak memory consumption was 223.0 MB. Max. memory is 11.5 GB. [2018-11-23 05:46:16,575 INFO L168 Benchmark]: Witness Printer took 3.68 ms. Allocated memory is still 1.3 GB. Free memory is still 995.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 05:46:16,577 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 234.51 ms. Allocated memory is still 1.0 GB. Free memory was 958.1 MB in the beginning and 941.9 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 69.16 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 195.6 MB). Free memory was 941.9 MB in the beginning and 1.2 GB in the end (delta: -249.0 MB). Peak memory consumption was 14.3 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 22.78 ms. Allocated memory is still 1.2 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 204.97 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 20.3 MB). Peak memory consumption was 20.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 5161.67 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 48.2 MB). Free memory was 1.2 GB in the beginning and 995.9 MB in the end (delta: 174.8 MB). Peak memory consumption was 223.0 MB. Max. memory is 11.5 GB. * Witness Printer took 3.68 ms. Allocated memory is still 1.3 GB. Free memory is still 995.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 7]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of bitwiseOr at line 100, overapproximation of bitwiseAnd at line 98. Possible FailurePath: [L215] unsigned int a ; [L216] unsigned int ma = __VERIFIER_nondet_uint(); [L217] signed char ea = __VERIFIER_nondet_char(); [L218] unsigned int b ; [L219] unsigned int mb = __VERIFIER_nondet_uint(); [L220] signed char eb = __VERIFIER_nondet_char(); [L221] unsigned int r_add1 ; [L222] unsigned int r_add2 ; [L223] unsigned int zero ; [L224] int tmp ; [L225] int tmp___0 ; [L226] int __retres14 ; VAL [ea=127, eb=0, ma=33554432, mb=16777216] [L230] CALL, EXPR base2flt(0, 0) VAL [\old(e)=0, \old(m)=0] [L15] unsigned int res ; [L16] unsigned int __retres4 ; VAL [\old(e)=0, \old(m)=0, e=0, m=0] [L19] COND TRUE ! m [L20] __retres4 = 0U VAL [\old(e)=0, \old(m)=0, __retres4=0, e=0, m=0] [L70] return (__retres4); VAL [\old(e)=0, \old(m)=0, \result=0, __retres4=0, e=0, m=0] [L230] RET, EXPR base2flt(0, 0) VAL [base2flt(0, 0)=0, ea=127, eb=0, ma=33554432, mb=16777216] [L230] zero = base2flt(0, 0) [L231] CALL, EXPR base2flt(ma, ea) VAL [\old(e)=127, \old(m)=33554432] [L15] unsigned int res ; [L16] unsigned int __retres4 ; VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L19] COND FALSE !(! m) VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L25] COND FALSE !(m < 1U << 24U) VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L47] COND TRUE 1 VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L49] COND TRUE m >= 1U << 25U VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L54] COND TRUE e >= 127 [L55] __retres4 = 4294967295U VAL [\old(e)=127, \old(m)=33554432, __retres4=4294967295, e=127, m=33554432] [L70] return (__retres4); VAL [\old(e)=127, \old(m)=33554432, \result=4294967295, __retres4=4294967295, e=127, m=33554432] [L231] RET, EXPR base2flt(ma, ea) VAL [base2flt(ma, ea)=4294967295, ea=127, eb=0, ma=33554432, mb=16777216, zero=0] [L231] a = base2flt(ma, ea) [L232] CALL, EXPR base2flt(mb, eb) VAL [\old(e)=0, \old(m)=16777216] [L15] unsigned int res ; [L16] unsigned int __retres4 ; VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L19] COND FALSE !(! m) VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L25] COND FALSE !(m < 1U << 24U) VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L47] COND TRUE 1 VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L49] COND FALSE !(m >= 1U << 25U) VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L66] m = m & ~ (1U << 24U) [L67] res = m | (unsigned int )((e + 128) << 24U) [L68] __retres4 = res VAL [\old(e)=0, \old(m)=16777216, __retres4=4278190080, e=0, res=4278190080] [L70] return (__retres4); VAL [\old(e)=0, \old(m)=16777216, \result=36028797002186752, __retres4=4278190080, e=0, res=4278190080] [L232] RET, EXPR base2flt(mb, eb) VAL [a=4294967295, base2flt(mb, eb)=36028797002186752, ea=127, eb=0, ma=33554432, mb=16777216, zero=0] [L232] b = base2flt(mb, eb) [L233] CALL addflt(a, b) VAL [\old(a)=4294967295, \old(b)=4278190080] [L74] unsigned int res ; [L75] unsigned int ma ; [L76] unsigned int mb ; [L77] unsigned int delta ; [L78] int ea ; [L79] int eb ; [L80] unsigned int tmp ; [L81] unsigned int __retres10 ; VAL [\old(a)=4294967295, \old(b)=4278190080, a=4294967295, b=4278190080] [L84] COND FALSE !(a < b) VAL [\old(a)=4294967295, \old(b)=4278190080, a=4294967295, b=4278190080] [L91] COND FALSE !(! b) [L98] ma = a & ((1U << 24U) - 1U) [L99] ea = (int )(a >> 24U) - 128 [L100] ma = ma | (1U << 24U) [L101] mb = b & ((1U << 24U) - 1U) [L102] eb = (int )(b >> 24U) - 128 [L103] mb = mb | (1U << 24U) VAL [\old(a)=4294967295, \old(b)=4278190080, a=4294967295, b=4278190080, ea=127, eb=2147483519] [L104] CALL __VERIFIER_assert(ea >= eb) VAL [\old(cond)=0] [L6] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L7] __VERIFIER_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 6 procedures, 56 locations, 1 error locations. UNSAFE Result, 5.1s OverallTime, 9 OverallIterations, 3 TraceHistogramMax, 3.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 619 SDtfs, 334 SDslu, 4534 SDs, 0 SdLazy, 1149 SolverSat, 50 SolverUnsat, 1 SolverUnknown, 0 SolverNotchecked, 2.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 273 GetRequests, 159 SyntacticMatches, 7 SemanticMatches, 107 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 140 ImplicationChecksByTransitivity, 1.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=165occurred in iteration=8, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 8 MinimizatonAttempts, 152 StatesRemovedByMinimization, 8 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.0s InterpolantComputationTime, 514 NumberOfCodeBlocks, 514 NumberOfCodeBlocksAsserted, 13 NumberOfCheckSat, 460 ConstructedInterpolants, 1 QuantifiedInterpolants, 52168 SizeOfPredicates, 17 NumberOfNonLiveVariables, 482 ConjunctsInSsa, 77 ConjunctsInUnsatCore, 12 InterpolantComputations, 4 PerfectInterpolantSequences, 155/203 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request... ### Bit-precise run ### This is Ultimate 0.1.23-aa41828 [2018-11-23 05:46:18,018 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 05:46:18,019 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 05:46:18,027 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 05:46:18,027 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 05:46:18,027 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 05:46:18,028 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 05:46:18,029 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 05:46:18,030 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 05:46:18,031 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 05:46:18,032 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 05:46:18,032 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 05:46:18,032 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 05:46:18,033 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 05:46:18,034 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 05:46:18,034 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 05:46:18,035 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 05:46:18,036 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 05:46:18,037 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 05:46:18,039 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 05:46:18,039 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 05:46:18,040 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 05:46:18,042 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 05:46:18,042 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 05:46:18,042 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 05:46:18,043 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 05:46:18,043 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 05:46:18,044 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 05:46:18,044 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 05:46:18,045 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 05:46:18,045 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 05:46:18,046 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 05:46:18,046 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 05:46:18,046 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 05:46:18,047 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 05:46:18,047 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 05:46:18,048 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Bitvector.epf [2018-11-23 05:46:18,058 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 05:46:18,058 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 05:46:18,058 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 05:46:18,058 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 05:46:18,059 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 05:46:18,059 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 05:46:18,059 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 05:46:18,059 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 05:46:18,060 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 05:46:18,060 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 05:46:18,060 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 05:46:18,060 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 05:46:18,060 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 05:46:18,060 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 05:46:18,060 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-23 05:46:18,060 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-23 05:46:18,061 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 05:46:18,061 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 05:46:18,061 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 05:46:18,061 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 05:46:18,061 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 05:46:18,061 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 05:46:18,062 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 05:46:18,062 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 05:46:18,062 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 05:46:18,062 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 05:46:18,062 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 05:46:18,062 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 05:46:18,062 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-23 05:46:18,063 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 05:46:18,063 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-23 05:46:18,063 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-23 05:46:18,063 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ee05cb2d66f71fb2277986b04bb223cfc634fed1 [2018-11-23 05:46:18,093 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 05:46:18,103 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 05:46:18,105 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 05:46:18,107 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 05:46:18,107 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 05:46:18,107 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/../../sv-benchmarks/c/bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c [2018-11-23 05:46:18,153 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/data/885e4e338/30559f362e314fb1b55164a916f4fee9/FLAG1701715b4 [2018-11-23 05:46:18,488 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 05:46:18,489 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/sv-benchmarks/c/bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c [2018-11-23 05:46:18,493 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/data/885e4e338/30559f362e314fb1b55164a916f4fee9/FLAG1701715b4 [2018-11-23 05:46:18,916 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/data/885e4e338/30559f362e314fb1b55164a916f4fee9 [2018-11-23 05:46:18,918 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 05:46:18,919 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 05:46:18,920 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 05:46:18,920 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 05:46:18,923 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 05:46:18,924 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 05:46:18" (1/1) ... [2018-11-23 05:46:18,926 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@679a0c60 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:18, skipping insertion in model container [2018-11-23 05:46:18,926 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 05:46:18" (1/1) ... [2018-11-23 05:46:18,933 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 05:46:18,954 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 05:46:19,114 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 05:46:19,118 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 05:46:19,145 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 05:46:19,154 INFO L195 MainTranslator]: Completed translation [2018-11-23 05:46:19,155 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:19 WrapperNode [2018-11-23 05:46:19,155 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 05:46:19,156 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 05:46:19,156 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 05:46:19,156 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 05:46:19,163 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:19" (1/1) ... [2018-11-23 05:46:19,174 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:19" (1/1) ... [2018-11-23 05:46:19,178 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 05:46:19,178 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 05:46:19,179 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 05:46:19,179 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 05:46:19,185 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:19" (1/1) ... [2018-11-23 05:46:19,185 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:19" (1/1) ... [2018-11-23 05:46:19,187 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:19" (1/1) ... [2018-11-23 05:46:19,187 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:19" (1/1) ... [2018-11-23 05:46:19,193 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:19" (1/1) ... [2018-11-23 05:46:19,198 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:19" (1/1) ... [2018-11-23 05:46:19,200 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:19" (1/1) ... [2018-11-23 05:46:19,202 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 05:46:19,203 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 05:46:19,203 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 05:46:19,203 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 05:46:19,204 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:19" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 05:46:19,270 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 05:46:19,270 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 05:46:19,271 INFO L130 BoogieDeclarations]: Found specification of procedure base2flt [2018-11-23 05:46:19,271 INFO L138 BoogieDeclarations]: Found implementation of procedure base2flt [2018-11-23 05:46:19,271 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 05:46:19,271 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 05:46:19,271 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 05:46:19,271 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 05:46:19,271 INFO L130 BoogieDeclarations]: Found specification of procedure addflt [2018-11-23 05:46:19,271 INFO L138 BoogieDeclarations]: Found implementation of procedure addflt [2018-11-23 05:46:19,271 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-23 05:46:19,272 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-23 05:46:19,475 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 05:46:19,475 INFO L280 CfgBuilder]: Removed 2 assue(true) statements. [2018-11-23 05:46:19,476 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:46:19 BoogieIcfgContainer [2018-11-23 05:46:19,476 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 05:46:19,477 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 05:46:19,477 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 05:46:19,479 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 05:46:19,479 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 05:46:18" (1/3) ... [2018-11-23 05:46:19,479 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5f1d691f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 05:46:19, skipping insertion in model container [2018-11-23 05:46:19,479 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:19" (2/3) ... [2018-11-23 05:46:19,480 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5f1d691f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 05:46:19, skipping insertion in model container [2018-11-23 05:46:19,480 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:46:19" (3/3) ... [2018-11-23 05:46:19,481 INFO L112 eAbstractionObserver]: Analyzing ICFG soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c [2018-11-23 05:46:19,487 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 05:46:19,492 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 05:46:19,501 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 05:46:19,519 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 05:46:19,520 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 05:46:19,520 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 05:46:19,520 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 05:46:19,520 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 05:46:19,520 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 05:46:19,520 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 05:46:19,520 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 05:46:19,520 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 05:46:19,530 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states. [2018-11-23 05:46:19,534 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-23 05:46:19,535 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:19,535 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:19,537 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:19,540 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:19,540 INFO L82 PathProgramCache]: Analyzing trace with hash 1457053844, now seen corresponding path program 1 times [2018-11-23 05:46:19,542 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:19,543 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:19,555 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:19,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:19,603 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:19,706 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-23 05:46:19,706 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:46:19,767 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-23 05:46:19,771 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:46:19,771 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 9 [2018-11-23 05:46:19,774 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 05:46:19,782 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 05:46:19,782 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-11-23 05:46:19,784 INFO L87 Difference]: Start difference. First operand 56 states. Second operand 9 states. [2018-11-23 05:46:19,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:19,946 INFO L93 Difference]: Finished difference Result 136 states and 204 transitions. [2018-11-23 05:46:19,946 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 05:46:19,948 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 34 [2018-11-23 05:46:19,948 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:19,956 INFO L225 Difference]: With dead ends: 136 [2018-11-23 05:46:19,956 INFO L226 Difference]: Without dead ends: 78 [2018-11-23 05:46:19,959 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 71 GetRequests, 60 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=122, Unknown=0, NotChecked=0, Total=156 [2018-11-23 05:46:19,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2018-11-23 05:46:19,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 64. [2018-11-23 05:46:19,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-11-23 05:46:19,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 86 transitions. [2018-11-23 05:46:19,994 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 86 transitions. Word has length 34 [2018-11-23 05:46:19,995 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:19,995 INFO L480 AbstractCegarLoop]: Abstraction has 64 states and 86 transitions. [2018-11-23 05:46:19,995 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 05:46:19,995 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 86 transitions. [2018-11-23 05:46:19,997 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-11-23 05:46:19,997 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:19,998 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:19,998 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:19,998 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:19,998 INFO L82 PathProgramCache]: Analyzing trace with hash 1790976707, now seen corresponding path program 1 times [2018-11-23 05:46:19,999 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:19,999 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:20,016 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:20,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:20,044 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:20,098 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-23 05:46:20,098 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:46:20,175 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-23 05:46:20,179 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:46:20,179 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2018-11-23 05:46:20,180 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 05:46:20,181 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 05:46:20,181 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-11-23 05:46:20,181 INFO L87 Difference]: Start difference. First operand 64 states and 86 transitions. Second operand 8 states. [2018-11-23 05:46:20,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:20,300 INFO L93 Difference]: Finished difference Result 117 states and 164 transitions. [2018-11-23 05:46:20,301 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 05:46:20,301 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 38 [2018-11-23 05:46:20,301 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:20,303 INFO L225 Difference]: With dead ends: 117 [2018-11-23 05:46:20,303 INFO L226 Difference]: Without dead ends: 91 [2018-11-23 05:46:20,304 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 67 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-11-23 05:46:20,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-11-23 05:46:20,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 84. [2018-11-23 05:46:20,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-11-23 05:46:20,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 118 transitions. [2018-11-23 05:46:20,318 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 118 transitions. Word has length 38 [2018-11-23 05:46:20,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:20,318 INFO L480 AbstractCegarLoop]: Abstraction has 84 states and 118 transitions. [2018-11-23 05:46:20,318 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 05:46:20,319 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 118 transitions. [2018-11-23 05:46:20,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-11-23 05:46:20,320 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:20,320 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:20,320 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:20,321 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:20,321 INFO L82 PathProgramCache]: Analyzing trace with hash 1848235009, now seen corresponding path program 1 times [2018-11-23 05:46:20,321 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:20,321 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:20,334 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:20,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:20,361 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:20,413 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-23 05:46:20,413 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 05:46:20,414 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:20,415 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 05:46:20,415 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 05:46:20,415 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 05:46:20,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-11-23 05:46:20,416 INFO L87 Difference]: Start difference. First operand 84 states and 118 transitions. Second operand 8 states. [2018-11-23 05:46:20,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:20,493 INFO L93 Difference]: Finished difference Result 161 states and 218 transitions. [2018-11-23 05:46:20,494 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 05:46:20,494 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 38 [2018-11-23 05:46:20,494 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:20,496 INFO L225 Difference]: With dead ends: 161 [2018-11-23 05:46:20,496 INFO L226 Difference]: Without dead ends: 121 [2018-11-23 05:46:20,496 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 31 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-11-23 05:46:20,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-11-23 05:46:20,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 92. [2018-11-23 05:46:20,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-11-23 05:46:20,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 126 transitions. [2018-11-23 05:46:20,511 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 126 transitions. Word has length 38 [2018-11-23 05:46:20,511 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:20,511 INFO L480 AbstractCegarLoop]: Abstraction has 92 states and 126 transitions. [2018-11-23 05:46:20,511 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 05:46:20,511 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 126 transitions. [2018-11-23 05:46:20,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-23 05:46:20,513 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:20,513 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:20,513 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:20,513 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:20,514 INFO L82 PathProgramCache]: Analyzing trace with hash -977604237, now seen corresponding path program 1 times [2018-11-23 05:46:20,514 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:20,514 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:20,531 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:20,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:20,557 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:20,603 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-23 05:46:20,604 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 05:46:20,606 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:20,606 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-23 05:46:20,606 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 05:46:20,607 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 05:46:20,607 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-11-23 05:46:20,607 INFO L87 Difference]: Start difference. First operand 92 states and 126 transitions. Second operand 9 states. [2018-11-23 05:46:20,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:20,723 INFO L93 Difference]: Finished difference Result 136 states and 182 transitions. [2018-11-23 05:46:20,723 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 05:46:20,723 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 42 [2018-11-23 05:46:20,724 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:20,725 INFO L225 Difference]: With dead ends: 136 [2018-11-23 05:46:20,725 INFO L226 Difference]: Without dead ends: 115 [2018-11-23 05:46:20,725 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 35 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=34, Invalid=122, Unknown=0, NotChecked=0, Total=156 [2018-11-23 05:46:20,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-11-23 05:46:20,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 100. [2018-11-23 05:46:20,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 100 states. [2018-11-23 05:46:20,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 135 transitions. [2018-11-23 05:46:20,739 INFO L78 Accepts]: Start accepts. Automaton has 100 states and 135 transitions. Word has length 42 [2018-11-23 05:46:20,739 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:20,739 INFO L480 AbstractCegarLoop]: Abstraction has 100 states and 135 transitions. [2018-11-23 05:46:20,739 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 05:46:20,739 INFO L276 IsEmpty]: Start isEmpty. Operand 100 states and 135 transitions. [2018-11-23 05:46:20,741 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-23 05:46:20,741 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:20,741 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:20,741 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:20,741 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:20,741 INFO L82 PathProgramCache]: Analyzing trace with hash -717016526, now seen corresponding path program 2 times [2018-11-23 05:46:20,742 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:20,742 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:20,753 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 05:46:20,770 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-23 05:46:20,770 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:46:20,774 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:20,883 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-23 05:46:20,884 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 05:46:20,885 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:20,885 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-23 05:46:20,885 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-23 05:46:20,886 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-23 05:46:20,886 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=110, Unknown=0, NotChecked=0, Total=132 [2018-11-23 05:46:20,886 INFO L87 Difference]: Start difference. First operand 100 states and 135 transitions. Second operand 12 states. [2018-11-23 05:46:21,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:21,113 INFO L93 Difference]: Finished difference Result 195 states and 263 transitions. [2018-11-23 05:46:21,114 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 05:46:21,114 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 42 [2018-11-23 05:46:21,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:21,116 INFO L225 Difference]: With dead ends: 195 [2018-11-23 05:46:21,116 INFO L226 Difference]: Without dead ends: 160 [2018-11-23 05:46:21,117 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 31 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2018-11-23 05:46:21,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-11-23 05:46:21,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 148. [2018-11-23 05:46:21,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-11-23 05:46:21,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 196 transitions. [2018-11-23 05:46:21,133 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 196 transitions. Word has length 42 [2018-11-23 05:46:21,134 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:21,134 INFO L480 AbstractCegarLoop]: Abstraction has 148 states and 196 transitions. [2018-11-23 05:46:21,134 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-23 05:46:21,134 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 196 transitions. [2018-11-23 05:46:21,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-23 05:46:21,135 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:21,135 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:21,136 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:21,136 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:21,136 INFO L82 PathProgramCache]: Analyzing trace with hash 806415478, now seen corresponding path program 1 times [2018-11-23 05:46:21,136 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:21,136 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:21,151 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:46:21,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:21,178 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:21,253 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-23 05:46:21,253 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:46:21,415 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:46:21,415 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:46:21,432 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:21,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:21,444 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:21,454 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-23 05:46:21,455 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:46:21,475 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:46:21,476 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2018-11-23 05:46:21,476 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-23 05:46:21,476 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-23 05:46:21,476 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2018-11-23 05:46:21,477 INFO L87 Difference]: Start difference. First operand 148 states and 196 transitions. Second operand 11 states. [2018-11-23 05:46:21,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:21,659 INFO L93 Difference]: Finished difference Result 207 states and 267 transitions. [2018-11-23 05:46:21,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 05:46:21,660 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 42 [2018-11-23 05:46:21,660 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:21,661 INFO L225 Difference]: With dead ends: 207 [2018-11-23 05:46:21,661 INFO L226 Difference]: Without dead ends: 176 [2018-11-23 05:46:21,662 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 106 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=62, Invalid=358, Unknown=0, NotChecked=0, Total=420 [2018-11-23 05:46:21,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2018-11-23 05:46:21,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 156. [2018-11-23 05:46:21,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-11-23 05:46:21,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 201 transitions. [2018-11-23 05:46:21,677 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 201 transitions. Word has length 42 [2018-11-23 05:46:21,677 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:21,677 INFO L480 AbstractCegarLoop]: Abstraction has 156 states and 201 transitions. [2018-11-23 05:46:21,677 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-23 05:46:21,677 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 201 transitions. [2018-11-23 05:46:21,678 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-23 05:46:21,678 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:21,678 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:21,678 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:21,678 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:21,678 INFO L82 PathProgramCache]: Analyzing trace with hash -1035766736, now seen corresponding path program 1 times [2018-11-23 05:46:21,679 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:21,679 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:21,690 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:21,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:21,717 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:21,795 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-23 05:46:21,795 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 05:46:21,796 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:21,796 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-23 05:46:21,797 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-23 05:46:21,797 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-23 05:46:21,797 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=111, Unknown=0, NotChecked=0, Total=132 [2018-11-23 05:46:21,797 INFO L87 Difference]: Start difference. First operand 156 states and 201 transitions. Second operand 12 states. [2018-11-23 05:46:22,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:22,064 INFO L93 Difference]: Finished difference Result 206 states and 264 transitions. [2018-11-23 05:46:22,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-23 05:46:22,064 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 42 [2018-11-23 05:46:22,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:22,065 INFO L225 Difference]: With dead ends: 206 [2018-11-23 05:46:22,065 INFO L226 Difference]: Without dead ends: 175 [2018-11-23 05:46:22,066 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 31 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2018-11-23 05:46:22,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2018-11-23 05:46:22,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 151. [2018-11-23 05:46:22,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-11-23 05:46:22,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 192 transitions. [2018-11-23 05:46:22,080 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 192 transitions. Word has length 42 [2018-11-23 05:46:22,080 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:22,080 INFO L480 AbstractCegarLoop]: Abstraction has 151 states and 192 transitions. [2018-11-23 05:46:22,080 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-23 05:46:22,080 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 192 transitions. [2018-11-23 05:46:22,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-23 05:46:22,081 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:22,081 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:22,081 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:22,082 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:22,082 INFO L82 PathProgramCache]: Analyzing trace with hash 487665268, now seen corresponding path program 1 times [2018-11-23 05:46:22,082 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:22,082 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:22,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:22,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:22,127 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:22,159 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-23 05:46:22,160 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 05:46:22,161 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:22,161 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 05:46:22,161 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 05:46:22,162 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 05:46:22,162 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 05:46:22,162 INFO L87 Difference]: Start difference. First operand 151 states and 192 transitions. Second operand 6 states. [2018-11-23 05:46:23,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:23,338 INFO L93 Difference]: Finished difference Result 196 states and 247 transitions. [2018-11-23 05:46:23,339 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 05:46:23,339 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 42 [2018-11-23 05:46:23,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:23,340 INFO L225 Difference]: With dead ends: 196 [2018-11-23 05:46:23,340 INFO L226 Difference]: Without dead ends: 194 [2018-11-23 05:46:23,341 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-11-23 05:46:23,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194 states. [2018-11-23 05:46:23,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194 to 157. [2018-11-23 05:46:23,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-11-23 05:46:23,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 199 transitions. [2018-11-23 05:46:23,358 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 199 transitions. Word has length 42 [2018-11-23 05:46:23,358 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:23,358 INFO L480 AbstractCegarLoop]: Abstraction has 157 states and 199 transitions. [2018-11-23 05:46:23,358 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 05:46:23,358 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 199 transitions. [2018-11-23 05:46:23,359 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-23 05:46:23,359 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:23,359 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:23,359 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:23,360 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:23,360 INFO L82 PathProgramCache]: Analyzing trace with hash 544923570, now seen corresponding path program 1 times [2018-11-23 05:46:23,360 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:23,360 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:23,373 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:23,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:23,404 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:23,439 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-23 05:46:23,439 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 05:46:23,442 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:23,443 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 05:46:23,443 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 05:46:23,443 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 05:46:23,443 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 05:46:23,443 INFO L87 Difference]: Start difference. First operand 157 states and 199 transitions. Second operand 6 states. [2018-11-23 05:46:26,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:26,572 INFO L93 Difference]: Finished difference Result 174 states and 217 transitions. [2018-11-23 05:46:26,572 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 05:46:26,573 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 42 [2018-11-23 05:46:26,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:26,574 INFO L225 Difference]: With dead ends: 174 [2018-11-23 05:46:26,574 INFO L226 Difference]: Without dead ends: 172 [2018-11-23 05:46:26,574 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-11-23 05:46:26,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-11-23 05:46:26,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 155. [2018-11-23 05:46:26,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 155 states. [2018-11-23 05:46:26,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 195 transitions. [2018-11-23 05:46:26,589 INFO L78 Accepts]: Start accepts. Automaton has 155 states and 195 transitions. Word has length 42 [2018-11-23 05:46:26,590 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:26,590 INFO L480 AbstractCegarLoop]: Abstraction has 155 states and 195 transitions. [2018-11-23 05:46:26,590 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 05:46:26,590 INFO L276 IsEmpty]: Start isEmpty. Operand 155 states and 195 transitions. [2018-11-23 05:46:26,591 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-23 05:46:26,591 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:26,591 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:26,591 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:26,591 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:26,592 INFO L82 PathProgramCache]: Analyzing trace with hash -1597355174, now seen corresponding path program 1 times [2018-11-23 05:46:26,592 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:26,592 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:26,613 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:26,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:26,632 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:26,665 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-23 05:46:26,665 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:46:26,735 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-23 05:46:26,737 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:46:26,737 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 10 [2018-11-23 05:46:26,737 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-23 05:46:26,737 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-23 05:46:26,737 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2018-11-23 05:46:26,738 INFO L87 Difference]: Start difference. First operand 155 states and 195 transitions. Second operand 10 states. [2018-11-23 05:46:26,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:26,924 INFO L93 Difference]: Finished difference Result 212 states and 273 transitions. [2018-11-23 05:46:26,924 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 05:46:26,924 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 47 [2018-11-23 05:46:26,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:26,926 INFO L225 Difference]: With dead ends: 212 [2018-11-23 05:46:26,926 INFO L226 Difference]: Without dead ends: 201 [2018-11-23 05:46:26,926 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 84 SyntacticMatches, 4 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 1 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2018-11-23 05:46:26,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2018-11-23 05:46:26,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 169. [2018-11-23 05:46:26,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 169 states. [2018-11-23 05:46:26,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 214 transitions. [2018-11-23 05:46:26,944 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 214 transitions. Word has length 47 [2018-11-23 05:46:26,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:26,944 INFO L480 AbstractCegarLoop]: Abstraction has 169 states and 214 transitions. [2018-11-23 05:46:26,944 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-23 05:46:26,944 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 214 transitions. [2018-11-23 05:46:26,945 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-23 05:46:26,945 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:26,945 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:26,945 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:26,945 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:26,945 INFO L82 PathProgramCache]: Analyzing trace with hash -896290596, now seen corresponding path program 1 times [2018-11-23 05:46:26,946 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:26,946 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:26,969 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:26,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:26,989 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:27,072 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 05:46:27,072 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:46:27,178 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 05:46:27,180 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:46:27,180 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 14 [2018-11-23 05:46:27,180 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-23 05:46:27,180 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-23 05:46:27,181 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=152, Unknown=0, NotChecked=0, Total=182 [2018-11-23 05:46:27,181 INFO L87 Difference]: Start difference. First operand 169 states and 214 transitions. Second operand 14 states. [2018-11-23 05:46:27,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:27,423 INFO L93 Difference]: Finished difference Result 235 states and 301 transitions. [2018-11-23 05:46:27,424 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 05:46:27,424 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 47 [2018-11-23 05:46:27,424 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:27,425 INFO L225 Difference]: With dead ends: 235 [2018-11-23 05:46:27,426 INFO L226 Difference]: Without dead ends: 228 [2018-11-23 05:46:27,426 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 80 SyntacticMatches, 1 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=91, Invalid=329, Unknown=0, NotChecked=0, Total=420 [2018-11-23 05:46:27,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states. [2018-11-23 05:46:27,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 188. [2018-11-23 05:46:27,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 188 states. [2018-11-23 05:46:27,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 240 transitions. [2018-11-23 05:46:27,449 INFO L78 Accepts]: Start accepts. Automaton has 188 states and 240 transitions. Word has length 47 [2018-11-23 05:46:27,450 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:27,450 INFO L480 AbstractCegarLoop]: Abstraction has 188 states and 240 transitions. [2018-11-23 05:46:27,450 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-23 05:46:27,450 INFO L276 IsEmpty]: Start isEmpty. Operand 188 states and 240 transitions. [2018-11-23 05:46:27,452 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-23 05:46:27,452 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:27,452 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:27,452 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:27,452 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:27,452 INFO L82 PathProgramCache]: Analyzing trace with hash 1716473666, now seen corresponding path program 1 times [2018-11-23 05:46:27,453 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:27,453 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:27,478 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:27,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:27,499 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:27,573 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 05:46:27,573 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:46:27,703 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 05:46:27,710 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:46:27,710 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 16 [2018-11-23 05:46:27,710 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-23 05:46:27,711 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-23 05:46:27,711 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=203, Unknown=0, NotChecked=0, Total=240 [2018-11-23 05:46:27,711 INFO L87 Difference]: Start difference. First operand 188 states and 240 transitions. Second operand 16 states. [2018-11-23 05:46:28,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:28,011 INFO L93 Difference]: Finished difference Result 244 states and 315 transitions. [2018-11-23 05:46:28,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 05:46:28,011 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 49 [2018-11-23 05:46:28,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:28,013 INFO L225 Difference]: With dead ends: 244 [2018-11-23 05:46:28,013 INFO L226 Difference]: Without dead ends: 236 [2018-11-23 05:46:28,013 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 82 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=100, Invalid=406, Unknown=0, NotChecked=0, Total=506 [2018-11-23 05:46:28,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-11-23 05:46:28,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 207. [2018-11-23 05:46:28,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-11-23 05:46:28,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 265 transitions. [2018-11-23 05:46:28,035 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 265 transitions. Word has length 49 [2018-11-23 05:46:28,035 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:28,035 INFO L480 AbstractCegarLoop]: Abstraction has 207 states and 265 transitions. [2018-11-23 05:46:28,036 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-23 05:46:28,036 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 265 transitions. [2018-11-23 05:46:28,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-23 05:46:28,037 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:28,037 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:28,037 INFO L423 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:28,037 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:28,037 INFO L82 PathProgramCache]: Analyzing trace with hash 1773731968, now seen corresponding path program 1 times [2018-11-23 05:46:28,037 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:28,037 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:28,055 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:28,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:28,099 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:28,119 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-11-23 05:46:28,120 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 05:46:28,122 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:28,122 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 05:46:28,122 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 05:46:28,123 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 05:46:28,123 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 05:46:28,123 INFO L87 Difference]: Start difference. First operand 207 states and 265 transitions. Second operand 6 states. [2018-11-23 05:46:28,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:28,207 INFO L93 Difference]: Finished difference Result 215 states and 272 transitions. [2018-11-23 05:46:28,208 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 05:46:28,208 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 49 [2018-11-23 05:46:28,208 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:28,209 INFO L225 Difference]: With dead ends: 215 [2018-11-23 05:46:28,209 INFO L226 Difference]: Without dead ends: 196 [2018-11-23 05:46:28,209 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 44 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-11-23 05:46:28,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states. [2018-11-23 05:46:28,228 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 196. [2018-11-23 05:46:28,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 196 states. [2018-11-23 05:46:28,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 246 transitions. [2018-11-23 05:46:28,229 INFO L78 Accepts]: Start accepts. Automaton has 196 states and 246 transitions. Word has length 49 [2018-11-23 05:46:28,230 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:28,230 INFO L480 AbstractCegarLoop]: Abstraction has 196 states and 246 transitions. [2018-11-23 05:46:28,230 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 05:46:28,231 INFO L276 IsEmpty]: Start isEmpty. Operand 196 states and 246 transitions. [2018-11-23 05:46:28,231 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-23 05:46:28,232 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:28,232 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:28,232 INFO L423 AbstractCegarLoop]: === Iteration 14 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:28,232 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:28,232 INFO L82 PathProgramCache]: Analyzing trace with hash 2005355055, now seen corresponding path program 1 times [2018-11-23 05:46:28,232 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:28,232 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:28,257 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:28,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:28,306 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:28,411 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-23 05:46:28,411 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 05:46:28,413 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:28,413 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2018-11-23 05:46:28,413 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-23 05:46:28,413 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-23 05:46:28,413 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=130, Unknown=0, NotChecked=0, Total=156 [2018-11-23 05:46:28,414 INFO L87 Difference]: Start difference. First operand 196 states and 246 transitions. Second operand 13 states. [2018-11-23 05:46:28,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:28,608 INFO L93 Difference]: Finished difference Result 285 states and 369 transitions. [2018-11-23 05:46:28,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 05:46:28,609 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 50 [2018-11-23 05:46:28,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:28,610 INFO L225 Difference]: With dead ends: 285 [2018-11-23 05:46:28,610 INFO L226 Difference]: Without dead ends: 233 [2018-11-23 05:46:28,611 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 38 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=225, Unknown=0, NotChecked=0, Total=272 [2018-11-23 05:46:28,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states. [2018-11-23 05:46:28,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 206. [2018-11-23 05:46:28,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-11-23 05:46:28,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 256 transitions. [2018-11-23 05:46:28,630 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 256 transitions. Word has length 50 [2018-11-23 05:46:28,630 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:28,630 INFO L480 AbstractCegarLoop]: Abstraction has 206 states and 256 transitions. [2018-11-23 05:46:28,630 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-23 05:46:28,630 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 256 transitions. [2018-11-23 05:46:28,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-23 05:46:28,631 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:28,631 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:28,632 INFO L423 AbstractCegarLoop]: === Iteration 15 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:28,632 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:28,632 INFO L82 PathProgramCache]: Analyzing trace with hash -802652045, now seen corresponding path program 1 times [2018-11-23 05:46:28,632 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:28,632 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:28,657 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:28,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:28,705 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:30,812 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-23 05:46:30,812 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:46:30,936 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:46:30,936 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:46:30,942 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:30,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:30,955 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:30,963 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-23 05:46:30,963 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:46:31,041 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:46:31,041 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2018-11-23 05:46:31,041 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-23 05:46:31,041 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-23 05:46:31,041 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=150, Unknown=1, NotChecked=0, Total=182 [2018-11-23 05:46:31,042 INFO L87 Difference]: Start difference. First operand 206 states and 256 transitions. Second operand 11 states. [2018-11-23 05:46:33,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:33,385 INFO L93 Difference]: Finished difference Result 274 states and 343 transitions. [2018-11-23 05:46:33,385 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 05:46:33,385 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 50 [2018-11-23 05:46:33,386 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:33,386 INFO L225 Difference]: With dead ends: 274 [2018-11-23 05:46:33,387 INFO L226 Difference]: Without dead ends: 229 [2018-11-23 05:46:33,387 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 101 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=63, Invalid=277, Unknown=2, NotChecked=0, Total=342 [2018-11-23 05:46:33,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 229 states. [2018-11-23 05:46:33,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 229 to 204. [2018-11-23 05:46:33,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204 states. [2018-11-23 05:46:33,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 252 transitions. [2018-11-23 05:46:33,408 INFO L78 Accepts]: Start accepts. Automaton has 204 states and 252 transitions. Word has length 50 [2018-11-23 05:46:33,409 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:33,409 INFO L480 AbstractCegarLoop]: Abstraction has 204 states and 252 transitions. [2018-11-23 05:46:33,409 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-23 05:46:33,409 INFO L276 IsEmpty]: Start isEmpty. Operand 204 states and 252 transitions. [2018-11-23 05:46:33,410 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-23 05:46:33,410 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:33,410 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:33,410 INFO L423 AbstractCegarLoop]: === Iteration 16 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:33,410 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:33,410 INFO L82 PathProgramCache]: Analyzing trace with hash -526602707, now seen corresponding path program 1 times [2018-11-23 05:46:33,411 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:33,411 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:33,428 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:33,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:33,463 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:35,581 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-23 05:46:35,582 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 05:46:35,583 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:35,583 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-23 05:46:35,583 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-23 05:46:35,583 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-23 05:46:35,584 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=110, Unknown=1, NotChecked=0, Total=132 [2018-11-23 05:46:35,584 INFO L87 Difference]: Start difference. First operand 204 states and 252 transitions. Second operand 12 states. [2018-11-23 05:46:39,326 WARN L180 SmtUtils]: Spent 2.02 s on a formula simplification that was a NOOP. DAG size: 25 [2018-11-23 05:46:43,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:43,512 INFO L93 Difference]: Finished difference Result 271 states and 337 transitions. [2018-11-23 05:46:43,513 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 05:46:43,513 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 50 [2018-11-23 05:46:43,513 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:43,514 INFO L225 Difference]: With dead ends: 271 [2018-11-23 05:46:43,515 INFO L226 Difference]: Without dead ends: 226 [2018-11-23 05:46:43,515 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 8.3s TimeCoverageRelationStatistics Valid=93, Invalid=368, Unknown=1, NotChecked=0, Total=462 [2018-11-23 05:46:43,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states. [2018-11-23 05:46:43,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 202. [2018-11-23 05:46:43,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 202 states. [2018-11-23 05:46:43,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202 states to 202 states and 248 transitions. [2018-11-23 05:46:43,539 INFO L78 Accepts]: Start accepts. Automaton has 202 states and 248 transitions. Word has length 50 [2018-11-23 05:46:43,540 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:43,540 INFO L480 AbstractCegarLoop]: Abstraction has 202 states and 248 transitions. [2018-11-23 05:46:43,540 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-23 05:46:43,540 INFO L276 IsEmpty]: Start isEmpty. Operand 202 states and 248 transitions. [2018-11-23 05:46:43,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-11-23 05:46:43,541 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:43,541 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:43,541 INFO L423 AbstractCegarLoop]: === Iteration 17 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:43,542 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:43,542 INFO L82 PathProgramCache]: Analyzing trace with hash -1278128413, now seen corresponding path program 1 times [2018-11-23 05:46:43,542 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:43,542 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:43,561 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:43,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:43,589 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:43,626 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-11-23 05:46:43,627 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 05:46:43,628 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:43,628 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 05:46:43,628 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 05:46:43,629 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 05:46:43,629 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-11-23 05:46:43,629 INFO L87 Difference]: Start difference. First operand 202 states and 248 transitions. Second operand 8 states. [2018-11-23 05:46:43,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:43,812 INFO L93 Difference]: Finished difference Result 260 states and 324 transitions. [2018-11-23 05:46:43,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 05:46:43,813 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 54 [2018-11-23 05:46:43,813 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:43,814 INFO L225 Difference]: With dead ends: 260 [2018-11-23 05:46:43,814 INFO L226 Difference]: Without dead ends: 234 [2018-11-23 05:46:43,814 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 48 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-11-23 05:46:43,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234 states. [2018-11-23 05:46:43,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234 to 224. [2018-11-23 05:46:43,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 224 states. [2018-11-23 05:46:43,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224 states to 224 states and 279 transitions. [2018-11-23 05:46:43,835 INFO L78 Accepts]: Start accepts. Automaton has 224 states and 279 transitions. Word has length 54 [2018-11-23 05:46:43,835 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:43,835 INFO L480 AbstractCegarLoop]: Abstraction has 224 states and 279 transitions. [2018-11-23 05:46:43,835 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 05:46:43,835 INFO L276 IsEmpty]: Start isEmpty. Operand 224 states and 279 transitions. [2018-11-23 05:46:43,836 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-23 05:46:43,836 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:43,836 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:43,836 INFO L423 AbstractCegarLoop]: === Iteration 18 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:43,837 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:43,837 INFO L82 PathProgramCache]: Analyzing trace with hash 960357489, now seen corresponding path program 1 times [2018-11-23 05:46:43,837 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:46:43,837 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:46:43,858 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:43,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:43,906 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:46:50,074 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-23 05:46:50,075 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 05:46:50,082 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:50,082 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 05:46:50,083 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 05:46:50,083 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 05:46:50,083 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=37, Unknown=3, NotChecked=0, Total=56 [2018-11-23 05:46:50,083 INFO L87 Difference]: Start difference. First operand 224 states and 279 transitions. Second operand 8 states. [2018-11-23 05:46:58,294 WARN L180 SmtUtils]: Spent 1.97 s on a formula simplification. DAG size of input: 25 DAG size of output: 15 [2018-11-23 05:47:04,522 WARN L180 SmtUtils]: Spent 2.03 s on a formula simplification that was a NOOP. DAG size: 21 [2018-11-23 05:47:06,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:06,683 INFO L93 Difference]: Finished difference Result 255 states and 319 transitions. [2018-11-23 05:47:06,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 05:47:06,685 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 50 [2018-11-23 05:47:06,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:06,686 INFO L225 Difference]: With dead ends: 255 [2018-11-23 05:47:06,686 INFO L226 Difference]: Without dead ends: 253 [2018-11-23 05:47:06,686 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 43 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 13.6s TimeCoverageRelationStatistics Valid=33, Invalid=74, Unknown=3, NotChecked=0, Total=110 [2018-11-23 05:47:06,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 253 states. [2018-11-23 05:47:06,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 253 to 230. [2018-11-23 05:47:06,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-11-23 05:47:06,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 286 transitions. [2018-11-23 05:47:06,709 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 286 transitions. Word has length 50 [2018-11-23 05:47:06,710 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:06,710 INFO L480 AbstractCegarLoop]: Abstraction has 230 states and 286 transitions. [2018-11-23 05:47:06,710 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 05:47:06,710 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 286 transitions. [2018-11-23 05:47:06,711 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-11-23 05:47:06,711 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:06,711 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:06,711 INFO L423 AbstractCegarLoop]: === Iteration 19 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:06,712 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:06,712 INFO L82 PathProgramCache]: Analyzing trace with hash -614439095, now seen corresponding path program 1 times [2018-11-23 05:47:06,712 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:06,712 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 22 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:06,724 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:47:06,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:47:06,742 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:06,798 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-23 05:47:06,798 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:47:06,923 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-23 05:47:06,924 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:47:06,925 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 16 [2018-11-23 05:47:06,925 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-23 05:47:06,925 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-23 05:47:06,925 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-11-23 05:47:06,925 INFO L87 Difference]: Start difference. First operand 230 states and 286 transitions. Second operand 16 states. [2018-11-23 05:47:07,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:07,321 INFO L93 Difference]: Finished difference Result 275 states and 348 transitions. [2018-11-23 05:47:07,321 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-23 05:47:07,321 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 51 [2018-11-23 05:47:07,322 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:07,322 INFO L225 Difference]: With dead ends: 275 [2018-11-23 05:47:07,322 INFO L226 Difference]: Without dead ends: 266 [2018-11-23 05:47:07,323 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 87 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 48 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=96, Invalid=554, Unknown=0, NotChecked=0, Total=650 [2018-11-23 05:47:07,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 266 states. [2018-11-23 05:47:07,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 266 to 230. [2018-11-23 05:47:07,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-11-23 05:47:07,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 285 transitions. [2018-11-23 05:47:07,349 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 285 transitions. Word has length 51 [2018-11-23 05:47:07,349 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:07,349 INFO L480 AbstractCegarLoop]: Abstraction has 230 states and 285 transitions. [2018-11-23 05:47:07,349 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-23 05:47:07,350 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 285 transitions. [2018-11-23 05:47:07,350 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-11-23 05:47:07,350 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:07,351 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:07,351 INFO L423 AbstractCegarLoop]: === Iteration 20 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:07,351 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:07,351 INFO L82 PathProgramCache]: Analyzing trace with hash 1494907781, now seen corresponding path program 1 times [2018-11-23 05:47:07,351 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:07,351 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:07,365 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:47:07,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:47:07,380 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:07,461 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 05:47:07,461 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:47:07,721 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 05:47:07,722 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:47:07,722 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 24 [2018-11-23 05:47:07,723 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-23 05:47:07,723 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-23 05:47:07,723 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=496, Unknown=0, NotChecked=0, Total=552 [2018-11-23 05:47:07,723 INFO L87 Difference]: Start difference. First operand 230 states and 285 transitions. Second operand 24 states. [2018-11-23 05:47:08,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:08,539 INFO L93 Difference]: Finished difference Result 302 states and 396 transitions. [2018-11-23 05:47:08,539 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-11-23 05:47:08,539 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 51 [2018-11-23 05:47:08,540 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:08,541 INFO L225 Difference]: With dead ends: 302 [2018-11-23 05:47:08,541 INFO L226 Difference]: Without dead ends: 287 [2018-11-23 05:47:08,542 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 117 GetRequests, 78 SyntacticMatches, 1 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 163 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=199, Invalid=1361, Unknown=0, NotChecked=0, Total=1560 [2018-11-23 05:47:08,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 287 states. [2018-11-23 05:47:08,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 287 to 235. [2018-11-23 05:47:08,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 235 states. [2018-11-23 05:47:08,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 235 states to 235 states and 299 transitions. [2018-11-23 05:47:08,576 INFO L78 Accepts]: Start accepts. Automaton has 235 states and 299 transitions. Word has length 51 [2018-11-23 05:47:08,577 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:08,577 INFO L480 AbstractCegarLoop]: Abstraction has 235 states and 299 transitions. [2018-11-23 05:47:08,577 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-23 05:47:08,577 INFO L276 IsEmpty]: Start isEmpty. Operand 235 states and 299 transitions. [2018-11-23 05:47:08,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-11-23 05:47:08,578 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:08,578 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:08,578 INFO L423 AbstractCegarLoop]: === Iteration 21 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:08,578 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:08,579 INFO L82 PathProgramCache]: Analyzing trace with hash 32918923, now seen corresponding path program 2 times [2018-11-23 05:47:08,579 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:08,579 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 24 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:08,598 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 05:47:08,614 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:47:08,614 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:47:08,616 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:08,667 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-23 05:47:08,667 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:47:08,793 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-23 05:47:08,794 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:47:08,794 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 14 [2018-11-23 05:47:08,794 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-23 05:47:08,794 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-23 05:47:08,794 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2018-11-23 05:47:08,795 INFO L87 Difference]: Start difference. First operand 235 states and 299 transitions. Second operand 14 states. [2018-11-23 05:47:09,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:09,140 INFO L93 Difference]: Finished difference Result 283 states and 376 transitions. [2018-11-23 05:47:09,140 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 05:47:09,141 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 51 [2018-11-23 05:47:09,141 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:09,141 INFO L225 Difference]: With dead ends: 283 [2018-11-23 05:47:09,142 INFO L226 Difference]: Without dead ends: 276 [2018-11-23 05:47:09,142 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 89 SyntacticMatches, 2 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=84, Invalid=422, Unknown=0, NotChecked=0, Total=506 [2018-11-23 05:47:09,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276 states. [2018-11-23 05:47:09,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276 to 243. [2018-11-23 05:47:09,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 243 states. [2018-11-23 05:47:09,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 243 states to 243 states and 318 transitions. [2018-11-23 05:47:09,173 INFO L78 Accepts]: Start accepts. Automaton has 243 states and 318 transitions. Word has length 51 [2018-11-23 05:47:09,173 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:09,173 INFO L480 AbstractCegarLoop]: Abstraction has 243 states and 318 transitions. [2018-11-23 05:47:09,173 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-23 05:47:09,173 INFO L276 IsEmpty]: Start isEmpty. Operand 243 states and 318 transitions. [2018-11-23 05:47:09,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-11-23 05:47:09,174 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:09,174 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:09,175 INFO L423 AbstractCegarLoop]: === Iteration 22 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:09,175 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:09,175 INFO L82 PathProgramCache]: Analyzing trace with hash 1866743247, now seen corresponding path program 2 times [2018-11-23 05:47:09,175 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:09,175 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:09,197 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 05:47:09,217 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:47:09,217 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:47:09,220 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:09,290 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 05:47:09,291 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:47:09,565 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 05:47:09,566 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:47:09,567 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 24 [2018-11-23 05:47:09,567 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-23 05:47:09,567 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-23 05:47:09,567 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=496, Unknown=0, NotChecked=0, Total=552 [2018-11-23 05:47:09,567 INFO L87 Difference]: Start difference. First operand 243 states and 318 transitions. Second operand 24 states. [2018-11-23 05:47:10,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:10,561 INFO L93 Difference]: Finished difference Result 303 states and 399 transitions. [2018-11-23 05:47:10,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-23 05:47:10,562 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 51 [2018-11-23 05:47:10,562 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:10,563 INFO L225 Difference]: With dead ends: 303 [2018-11-23 05:47:10,563 INFO L226 Difference]: Without dead ends: 270 [2018-11-23 05:47:10,564 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 116 GetRequests, 78 SyntacticMatches, 1 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 149 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=184, Invalid=1298, Unknown=0, NotChecked=0, Total=1482 [2018-11-23 05:47:10,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states. [2018-11-23 05:47:10,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 223. [2018-11-23 05:47:10,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 223 states. [2018-11-23 05:47:10,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 223 states to 223 states and 292 transitions. [2018-11-23 05:47:10,585 INFO L78 Accepts]: Start accepts. Automaton has 223 states and 292 transitions. Word has length 51 [2018-11-23 05:47:10,585 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:10,585 INFO L480 AbstractCegarLoop]: Abstraction has 223 states and 292 transitions. [2018-11-23 05:47:10,585 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-23 05:47:10,585 INFO L276 IsEmpty]: Start isEmpty. Operand 223 states and 292 transitions. [2018-11-23 05:47:10,586 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-11-23 05:47:10,586 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:10,586 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:10,586 INFO L423 AbstractCegarLoop]: === Iteration 23 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:10,587 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:10,587 INFO L82 PathProgramCache]: Analyzing trace with hash -528325640, now seen corresponding path program 1 times [2018-11-23 05:47:10,587 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:10,587 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 26 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:10,604 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:47:10,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:47:10,641 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:17,803 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-23 05:47:17,803 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 05:47:17,804 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:47:17,804 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 05:47:17,805 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 05:47:17,805 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 05:47:17,805 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=37, Unknown=3, NotChecked=0, Total=56 [2018-11-23 05:47:17,805 INFO L87 Difference]: Start difference. First operand 223 states and 292 transitions. Second operand 8 states. [2018-11-23 05:47:31,020 WARN L180 SmtUtils]: Spent 4.04 s on a formula simplification that was a NOOP. DAG size: 24 [2018-11-23 05:47:37,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:37,223 INFO L93 Difference]: Finished difference Result 246 states and 320 transitions. [2018-11-23 05:47:37,223 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 05:47:37,223 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 51 [2018-11-23 05:47:37,223 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:37,224 INFO L225 Difference]: With dead ends: 246 [2018-11-23 05:47:37,224 INFO L226 Difference]: Without dead ends: 220 [2018-11-23 05:47:37,224 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 44 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 11.2s TimeCoverageRelationStatistics Valid=25, Invalid=62, Unknown=3, NotChecked=0, Total=90 [2018-11-23 05:47:37,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220 states. [2018-11-23 05:47:37,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220 to 203. [2018-11-23 05:47:37,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2018-11-23 05:47:37,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 267 transitions. [2018-11-23 05:47:37,256 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 267 transitions. Word has length 51 [2018-11-23 05:47:37,256 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:37,256 INFO L480 AbstractCegarLoop]: Abstraction has 203 states and 267 transitions. [2018-11-23 05:47:37,256 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 05:47:37,257 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 267 transitions. [2018-11-23 05:47:37,257 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-23 05:47:37,257 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:37,258 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:37,258 INFO L423 AbstractCegarLoop]: === Iteration 24 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:37,258 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:37,258 INFO L82 PathProgramCache]: Analyzing trace with hash -1304588962, now seen corresponding path program 1 times [2018-11-23 05:47:37,258 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:37,258 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:37,281 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:47:37,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:47:37,299 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:37,327 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-23 05:47:37,327 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 05:47:37,329 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:47:37,329 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 05:47:37,329 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 05:47:37,329 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 05:47:37,329 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 05:47:37,329 INFO L87 Difference]: Start difference. First operand 203 states and 267 transitions. Second operand 5 states. [2018-11-23 05:47:37,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:37,401 INFO L93 Difference]: Finished difference Result 243 states and 341 transitions. [2018-11-23 05:47:37,401 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 05:47:37,401 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 57 [2018-11-23 05:47:37,401 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:37,402 INFO L225 Difference]: With dead ends: 243 [2018-11-23 05:47:37,402 INFO L226 Difference]: Without dead ends: 232 [2018-11-23 05:47:37,403 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 05:47:37,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232 states. [2018-11-23 05:47:37,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232 to 218. [2018-11-23 05:47:37,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 218 states. [2018-11-23 05:47:37,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 303 transitions. [2018-11-23 05:47:37,428 INFO L78 Accepts]: Start accepts. Automaton has 218 states and 303 transitions. Word has length 57 [2018-11-23 05:47:37,428 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:37,428 INFO L480 AbstractCegarLoop]: Abstraction has 218 states and 303 transitions. [2018-11-23 05:47:37,428 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 05:47:37,428 INFO L276 IsEmpty]: Start isEmpty. Operand 218 states and 303 transitions. [2018-11-23 05:47:37,429 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-23 05:47:37,429 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:37,430 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:37,430 INFO L423 AbstractCegarLoop]: === Iteration 25 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:37,430 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:37,430 INFO L82 PathProgramCache]: Analyzing trace with hash 1712427967, now seen corresponding path program 1 times [2018-11-23 05:47:37,430 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:37,430 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 28 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:37,453 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:47:37,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:47:37,473 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:37,540 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 6 proven. 7 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-23 05:47:37,541 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:47:37,706 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 5 proven. 8 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-23 05:47:37,707 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:47:37,707 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 18 [2018-11-23 05:47:37,707 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-23 05:47:37,707 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-23 05:47:37,708 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=257, Unknown=0, NotChecked=0, Total=306 [2018-11-23 05:47:37,708 INFO L87 Difference]: Start difference. First operand 218 states and 303 transitions. Second operand 18 states. [2018-11-23 05:47:38,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:38,109 INFO L93 Difference]: Finished difference Result 253 states and 345 transitions. [2018-11-23 05:47:38,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 05:47:38,110 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 64 [2018-11-23 05:47:38,111 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:38,112 INFO L225 Difference]: With dead ends: 253 [2018-11-23 05:47:38,112 INFO L226 Difference]: Without dead ends: 244 [2018-11-23 05:47:38,112 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 130 GetRequests, 110 SyntacticMatches, 1 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 55 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=71, Invalid=349, Unknown=0, NotChecked=0, Total=420 [2018-11-23 05:47:38,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 244 states. [2018-11-23 05:47:38,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 244 to 223. [2018-11-23 05:47:38,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 223 states. [2018-11-23 05:47:38,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 223 states to 223 states and 309 transitions. [2018-11-23 05:47:38,149 INFO L78 Accepts]: Start accepts. Automaton has 223 states and 309 transitions. Word has length 64 [2018-11-23 05:47:38,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:38,150 INFO L480 AbstractCegarLoop]: Abstraction has 223 states and 309 transitions. [2018-11-23 05:47:38,150 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-23 05:47:38,150 INFO L276 IsEmpty]: Start isEmpty. Operand 223 states and 309 transitions. [2018-11-23 05:47:38,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-23 05:47:38,151 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:38,151 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:38,151 INFO L423 AbstractCegarLoop]: === Iteration 26 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:38,151 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:38,151 INFO L82 PathProgramCache]: Analyzing trace with hash -1835326830, now seen corresponding path program 1 times [2018-11-23 05:47:38,152 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:38,152 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:38,172 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:47:38,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:47:38,199 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:38,245 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-23 05:47:38,246 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:47:38,457 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-23 05:47:38,459 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:47:38,459 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 11 [2018-11-23 05:47:38,459 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-23 05:47:38,459 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-23 05:47:38,459 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-11-23 05:47:38,460 INFO L87 Difference]: Start difference. First operand 223 states and 309 transitions. Second operand 11 states. [2018-11-23 05:47:38,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:38,685 INFO L93 Difference]: Finished difference Result 249 states and 341 transitions. [2018-11-23 05:47:38,686 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 05:47:38,686 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 64 [2018-11-23 05:47:38,686 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:38,687 INFO L225 Difference]: With dead ends: 249 [2018-11-23 05:47:38,687 INFO L226 Difference]: Without dead ends: 231 [2018-11-23 05:47:38,687 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 118 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=56, Invalid=154, Unknown=0, NotChecked=0, Total=210 [2018-11-23 05:47:38,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231 states. [2018-11-23 05:47:38,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231 to 226. [2018-11-23 05:47:38,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-11-23 05:47:38,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 313 transitions. [2018-11-23 05:47:38,727 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 313 transitions. Word has length 64 [2018-11-23 05:47:38,728 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:38,728 INFO L480 AbstractCegarLoop]: Abstraction has 226 states and 313 transitions. [2018-11-23 05:47:38,728 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-23 05:47:38,728 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 313 transitions. [2018-11-23 05:47:38,729 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-23 05:47:38,729 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:38,729 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:38,729 INFO L423 AbstractCegarLoop]: === Iteration 27 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:38,729 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:38,729 INFO L82 PathProgramCache]: Analyzing trace with hash -1527151470, now seen corresponding path program 2 times [2018-11-23 05:47:38,730 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:38,730 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 30 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:38,749 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 05:47:38,797 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:47:38,797 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:47:38,800 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:38,854 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-23 05:47:38,854 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:47:38,920 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-23 05:47:38,922 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:47:38,922 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 11 [2018-11-23 05:47:38,923 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-23 05:47:38,923 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-23 05:47:38,923 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-11-23 05:47:38,923 INFO L87 Difference]: Start difference. First operand 226 states and 313 transitions. Second operand 11 states. [2018-11-23 05:47:39,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:39,083 INFO L93 Difference]: Finished difference Result 244 states and 336 transitions. [2018-11-23 05:47:39,083 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 05:47:39,083 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 64 [2018-11-23 05:47:39,083 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:39,084 INFO L225 Difference]: With dead ends: 244 [2018-11-23 05:47:39,084 INFO L226 Difference]: Without dead ends: 226 [2018-11-23 05:47:39,085 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 132 GetRequests, 118 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=66, Invalid=174, Unknown=0, NotChecked=0, Total=240 [2018-11-23 05:47:39,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states. [2018-11-23 05:47:39,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 221. [2018-11-23 05:47:39,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 221 states. [2018-11-23 05:47:39,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 304 transitions. [2018-11-23 05:47:39,122 INFO L78 Accepts]: Start accepts. Automaton has 221 states and 304 transitions. Word has length 64 [2018-11-23 05:47:39,123 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:39,123 INFO L480 AbstractCegarLoop]: Abstraction has 221 states and 304 transitions. [2018-11-23 05:47:39,123 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-23 05:47:39,123 INFO L276 IsEmpty]: Start isEmpty. Operand 221 states and 304 transitions. [2018-11-23 05:47:39,124 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-11-23 05:47:39,124 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:39,124 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:39,124 INFO L423 AbstractCegarLoop]: === Iteration 28 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:39,124 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:39,125 INFO L82 PathProgramCache]: Analyzing trace with hash 218346458, now seen corresponding path program 1 times [2018-11-23 05:47:39,125 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:39,125 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:39,139 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:47:39,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:47:39,160 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:39,215 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-23 05:47:39,215 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:47:39,292 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-23 05:47:39,293 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:47:39,293 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 11 [2018-11-23 05:47:39,294 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-23 05:47:39,294 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-23 05:47:39,294 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-11-23 05:47:39,294 INFO L87 Difference]: Start difference. First operand 221 states and 304 transitions. Second operand 11 states. [2018-11-23 05:47:39,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:39,446 INFO L93 Difference]: Finished difference Result 237 states and 320 transitions. [2018-11-23 05:47:39,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 05:47:39,446 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 66 [2018-11-23 05:47:39,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:39,447 INFO L225 Difference]: With dead ends: 237 [2018-11-23 05:47:39,447 INFO L226 Difference]: Without dead ends: 223 [2018-11-23 05:47:39,448 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 135 GetRequests, 122 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=56, Invalid=154, Unknown=0, NotChecked=0, Total=210 [2018-11-23 05:47:39,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2018-11-23 05:47:39,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 218. [2018-11-23 05:47:39,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 218 states. [2018-11-23 05:47:39,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 298 transitions. [2018-11-23 05:47:39,475 INFO L78 Accepts]: Start accepts. Automaton has 218 states and 298 transitions. Word has length 66 [2018-11-23 05:47:39,475 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:39,475 INFO L480 AbstractCegarLoop]: Abstraction has 218 states and 298 transitions. [2018-11-23 05:47:39,475 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-23 05:47:39,476 INFO L276 IsEmpty]: Start isEmpty. Operand 218 states and 298 transitions. [2018-11-23 05:47:39,477 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-11-23 05:47:39,477 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:39,477 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:39,477 INFO L423 AbstractCegarLoop]: === Iteration 29 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:39,477 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:39,477 INFO L82 PathProgramCache]: Analyzing trace with hash 166673046, now seen corresponding path program 2 times [2018-11-23 05:47:39,478 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:39,478 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 32 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:39,495 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 05:47:39,528 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:47:39,528 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:47:39,531 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:39,575 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-23 05:47:39,575 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:47:39,646 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-23 05:47:39,649 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:47:39,649 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 11 [2018-11-23 05:47:39,649 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-23 05:47:39,649 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-23 05:47:39,650 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-11-23 05:47:39,650 INFO L87 Difference]: Start difference. First operand 218 states and 298 transitions. Second operand 11 states. [2018-11-23 05:47:39,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:39,802 INFO L93 Difference]: Finished difference Result 234 states and 314 transitions. [2018-11-23 05:47:39,802 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 05:47:39,802 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 66 [2018-11-23 05:47:39,803 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:39,803 INFO L225 Difference]: With dead ends: 234 [2018-11-23 05:47:39,803 INFO L226 Difference]: Without dead ends: 217 [2018-11-23 05:47:39,803 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 122 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=66, Invalid=174, Unknown=0, NotChecked=0, Total=240 [2018-11-23 05:47:39,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states. [2018-11-23 05:47:39,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 207. [2018-11-23 05:47:39,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-11-23 05:47:39,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 280 transitions. [2018-11-23 05:47:39,825 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 280 transitions. Word has length 66 [2018-11-23 05:47:39,825 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:39,825 INFO L480 AbstractCegarLoop]: Abstraction has 207 states and 280 transitions. [2018-11-23 05:47:39,826 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-23 05:47:39,826 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 280 transitions. [2018-11-23 05:47:39,827 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-11-23 05:47:39,827 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:39,827 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:39,827 INFO L423 AbstractCegarLoop]: === Iteration 30 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:39,827 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:39,827 INFO L82 PathProgramCache]: Analyzing trace with hash -1109140964, now seen corresponding path program 1 times [2018-11-23 05:47:39,828 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:39,828 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:39,849 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:47:39,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:47:39,877 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:39,968 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 15 proven. 3 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-23 05:47:39,968 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:47:40,136 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 15 proven. 3 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-23 05:47:40,137 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:47:40,138 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 16 [2018-11-23 05:47:40,138 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-23 05:47:40,138 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-23 05:47:40,138 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-11-23 05:47:40,138 INFO L87 Difference]: Start difference. First operand 207 states and 280 transitions. Second operand 16 states. [2018-11-23 05:47:40,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:40,459 INFO L93 Difference]: Finished difference Result 232 states and 305 transitions. [2018-11-23 05:47:40,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-23 05:47:40,459 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 71 [2018-11-23 05:47:40,459 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:40,460 INFO L225 Difference]: With dead ends: 232 [2018-11-23 05:47:40,460 INFO L226 Difference]: Without dead ends: 220 [2018-11-23 05:47:40,461 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 152 GetRequests, 127 SyntacticMatches, 3 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=90, Invalid=462, Unknown=0, NotChecked=0, Total=552 [2018-11-23 05:47:40,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220 states. [2018-11-23 05:47:40,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220 to 202. [2018-11-23 05:47:40,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 202 states. [2018-11-23 05:47:40,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202 states to 202 states and 265 transitions. [2018-11-23 05:47:40,487 INFO L78 Accepts]: Start accepts. Automaton has 202 states and 265 transitions. Word has length 71 [2018-11-23 05:47:40,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:40,487 INFO L480 AbstractCegarLoop]: Abstraction has 202 states and 265 transitions. [2018-11-23 05:47:40,487 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-23 05:47:40,487 INFO L276 IsEmpty]: Start isEmpty. Operand 202 states and 265 transitions. [2018-11-23 05:47:40,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-11-23 05:47:40,488 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:40,488 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:40,488 INFO L423 AbstractCegarLoop]: === Iteration 31 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:40,488 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:40,488 INFO L82 PathProgramCache]: Analyzing trace with hash 1043562547, now seen corresponding path program 1 times [2018-11-23 05:47:40,488 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:40,489 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 34 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:40,501 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:47:40,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:47:40,591 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:40,972 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 7 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-23 05:47:40,972 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:47:42,146 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 8 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-23 05:47:42,147 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:47:42,147 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13] total 22 [2018-11-23 05:47:42,147 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-23 05:47:42,148 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-23 05:47:42,148 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=390, Unknown=0, NotChecked=0, Total=462 [2018-11-23 05:47:42,148 INFO L87 Difference]: Start difference. First operand 202 states and 265 transitions. Second operand 22 states. [2018-11-23 05:47:42,508 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 46 [2018-11-23 05:47:42,926 WARN L180 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 43 [2018-11-23 05:47:43,269 WARN L180 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 38 [2018-11-23 05:47:43,725 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 40 [2018-11-23 05:47:44,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:44,669 INFO L93 Difference]: Finished difference Result 255 states and 343 transitions. [2018-11-23 05:47:44,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 05:47:44,670 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 71 [2018-11-23 05:47:44,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:44,671 INFO L225 Difference]: With dead ends: 255 [2018-11-23 05:47:44,671 INFO L226 Difference]: Without dead ends: 244 [2018-11-23 05:47:44,671 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 118 SyntacticMatches, 3 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 76 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=185, Invalid=807, Unknown=0, NotChecked=0, Total=992 [2018-11-23 05:47:44,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 244 states. [2018-11-23 05:47:44,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 244 to 217. [2018-11-23 05:47:44,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 217 states. [2018-11-23 05:47:44,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 292 transitions. [2018-11-23 05:47:44,701 INFO L78 Accepts]: Start accepts. Automaton has 217 states and 292 transitions. Word has length 71 [2018-11-23 05:47:44,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:44,701 INFO L480 AbstractCegarLoop]: Abstraction has 217 states and 292 transitions. [2018-11-23 05:47:44,701 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-23 05:47:44,701 INFO L276 IsEmpty]: Start isEmpty. Operand 217 states and 292 transitions. [2018-11-23 05:47:44,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-11-23 05:47:44,701 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:44,702 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:44,702 INFO L423 AbstractCegarLoop]: === Iteration 32 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:44,702 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:44,702 INFO L82 PathProgramCache]: Analyzing trace with hash 1017205495, now seen corresponding path program 2 times [2018-11-23 05:47:44,702 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:44,702 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:44,722 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 05:47:44,806 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:47:44,806 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:47:44,818 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:45,154 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 7 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-23 05:47:45,154 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:47:46,233 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 8 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-23 05:47:46,234 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:47:46,234 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13] total 22 [2018-11-23 05:47:46,235 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-23 05:47:46,235 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-23 05:47:46,235 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=391, Unknown=0, NotChecked=0, Total=462 [2018-11-23 05:47:46,235 INFO L87 Difference]: Start difference. First operand 217 states and 292 transitions. Second operand 22 states. [2018-11-23 05:47:46,906 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 44 [2018-11-23 05:47:47,395 WARN L180 SmtUtils]: Spent 203.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 41 [2018-11-23 05:47:47,790 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 37 [2018-11-23 05:47:48,205 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 40 [2018-11-23 05:47:49,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:49,173 INFO L93 Difference]: Finished difference Result 261 states and 352 transitions. [2018-11-23 05:47:49,174 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-23 05:47:49,174 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 71 [2018-11-23 05:47:49,174 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:49,175 INFO L225 Difference]: With dead ends: 261 [2018-11-23 05:47:49,175 INFO L226 Difference]: Without dead ends: 250 [2018-11-23 05:47:49,176 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 120 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 75 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=186, Invalid=806, Unknown=0, NotChecked=0, Total=992 [2018-11-23 05:47:49,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 250 states. [2018-11-23 05:47:49,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 250 to 226. [2018-11-23 05:47:49,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-11-23 05:47:49,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 307 transitions. [2018-11-23 05:47:49,220 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 307 transitions. Word has length 71 [2018-11-23 05:47:49,220 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:49,220 INFO L480 AbstractCegarLoop]: Abstraction has 226 states and 307 transitions. [2018-11-23 05:47:49,220 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-23 05:47:49,220 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 307 transitions. [2018-11-23 05:47:49,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-11-23 05:47:49,221 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:49,221 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:49,221 INFO L423 AbstractCegarLoop]: === Iteration 33 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:49,221 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:49,221 INFO L82 PathProgramCache]: Analyzing trace with hash 1098580064, now seen corresponding path program 1 times [2018-11-23 05:47:49,222 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:49,222 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 36 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:49,244 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:47:49,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:47:49,269 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:49,381 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 8 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-23 05:47:49,381 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:47:49,457 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:47:49,457 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:47:49,465 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:47:49,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:47:49,520 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:50,606 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-23 05:47:50,606 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 05:47:50,621 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 05:47:50,622 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [18] imperfect sequences [13] total 29 [2018-11-23 05:47:50,622 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-11-23 05:47:50,622 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-11-23 05:47:50,622 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=785, Unknown=0, NotChecked=0, Total=870 [2018-11-23 05:47:50,622 INFO L87 Difference]: Start difference. First operand 226 states and 307 transitions. Second operand 29 states. [2018-11-23 05:47:52,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:52,376 INFO L93 Difference]: Finished difference Result 256 states and 338 transitions. [2018-11-23 05:47:52,377 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-23 05:47:52,377 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 71 [2018-11-23 05:47:52,377 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:52,378 INFO L225 Difference]: With dead ends: 256 [2018-11-23 05:47:52,378 INFO L226 Difference]: Without dead ends: 247 [2018-11-23 05:47:52,378 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 161 GetRequests, 118 SyntacticMatches, 3 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 303 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=204, Invalid=1518, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 05:47:52,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247 states. [2018-11-23 05:47:52,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247 to 226. [2018-11-23 05:47:52,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-11-23 05:47:52,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 306 transitions. [2018-11-23 05:47:52,404 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 306 transitions. Word has length 71 [2018-11-23 05:47:52,404 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:52,405 INFO L480 AbstractCegarLoop]: Abstraction has 226 states and 306 transitions. [2018-11-23 05:47:52,405 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-11-23 05:47:52,405 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 306 transitions. [2018-11-23 05:47:52,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-11-23 05:47:52,405 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:52,405 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:52,405 INFO L423 AbstractCegarLoop]: === Iteration 34 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:52,406 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:52,406 INFO L82 PathProgramCache]: Analyzing trace with hash -1669060429, now seen corresponding path program 1 times [2018-11-23 05:47:52,406 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:52,406 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 38 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:52,420 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:47:52,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:47:52,493 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:52,890 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-11-23 05:47:52,890 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:47:53,022 WARN L180 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 45 DAG size of output: 43 [2018-11-23 05:47:54,417 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 9 proven. 11 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-11-23 05:47:54,419 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:47:54,419 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14] total 23 [2018-11-23 05:47:54,419 INFO L459 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-11-23 05:47:54,419 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-11-23 05:47:54,420 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=98, Invalid=408, Unknown=0, NotChecked=0, Total=506 [2018-11-23 05:47:54,420 INFO L87 Difference]: Start difference. First operand 226 states and 306 transitions. Second operand 23 states. [2018-11-23 05:47:55,697 WARN L180 SmtUtils]: Spent 235.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 46 [2018-11-23 05:47:57,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:57,134 INFO L93 Difference]: Finished difference Result 260 states and 345 transitions. [2018-11-23 05:47:57,136 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-23 05:47:57,136 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 76 [2018-11-23 05:47:57,137 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:57,137 INFO L225 Difference]: With dead ends: 260 [2018-11-23 05:47:57,138 INFO L226 Difference]: Without dead ends: 249 [2018-11-23 05:47:57,138 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 159 GetRequests, 127 SyntacticMatches, 3 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 163 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=201, Invalid=729, Unknown=0, NotChecked=0, Total=930 [2018-11-23 05:47:57,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states. [2018-11-23 05:47:57,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 228. [2018-11-23 05:47:57,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-11-23 05:47:57,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 302 transitions. [2018-11-23 05:47:57,170 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 302 transitions. Word has length 76 [2018-11-23 05:47:57,170 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:57,170 INFO L480 AbstractCegarLoop]: Abstraction has 228 states and 302 transitions. [2018-11-23 05:47:57,170 INFO L481 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-11-23 05:47:57,170 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 302 transitions. [2018-11-23 05:47:57,171 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-23 05:47:57,171 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:57,171 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:57,171 INFO L423 AbstractCegarLoop]: === Iteration 35 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:57,172 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:57,172 INFO L82 PathProgramCache]: Analyzing trace with hash 1038546648, now seen corresponding path program 1 times [2018-11-23 05:47:57,172 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:57,172 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:57,186 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:47:57,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:47:57,207 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:57,248 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-11-23 05:47:57,248 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:47:57,283 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-11-23 05:47:57,284 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:47:57,285 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-11-23 05:47:57,285 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 05:47:57,285 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 05:47:57,285 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 05:47:57,285 INFO L87 Difference]: Start difference. First operand 228 states and 302 transitions. Second operand 6 states. [2018-11-23 05:47:57,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:57,330 INFO L93 Difference]: Finished difference Result 243 states and 318 transitions. [2018-11-23 05:47:57,330 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 05:47:57,330 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2018-11-23 05:47:57,331 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:57,332 INFO L225 Difference]: With dead ends: 243 [2018-11-23 05:47:57,332 INFO L226 Difference]: Without dead ends: 238 [2018-11-23 05:47:57,332 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 146 GetRequests, 139 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 05:47:57,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 238 states. [2018-11-23 05:47:57,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 238 to 228. [2018-11-23 05:47:57,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-11-23 05:47:57,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 302 transitions. [2018-11-23 05:47:57,359 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 302 transitions. Word has length 73 [2018-11-23 05:47:57,359 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:57,359 INFO L480 AbstractCegarLoop]: Abstraction has 228 states and 302 transitions. [2018-11-23 05:47:57,359 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 05:47:57,359 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 302 transitions. [2018-11-23 05:47:57,360 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-23 05:47:57,360 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:57,360 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:57,361 INFO L423 AbstractCegarLoop]: === Iteration 36 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:57,361 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:57,361 INFO L82 PathProgramCache]: Analyzing trace with hash 1937569667, now seen corresponding path program 1 times [2018-11-23 05:47:57,361 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:47:57,361 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 40 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:47:57,373 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:47:57,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:47:57,442 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:47:57,760 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 7 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-23 05:47:57,760 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:47:58,865 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 8 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-23 05:47:58,866 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:47:58,866 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13] total 22 [2018-11-23 05:47:58,866 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-23 05:47:58,867 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-23 05:47:58,867 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=76, Invalid=386, Unknown=0, NotChecked=0, Total=462 [2018-11-23 05:47:58,867 INFO L87 Difference]: Start difference. First operand 228 states and 302 transitions. Second operand 22 states. [2018-11-23 05:47:59,414 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 41 [2018-11-23 05:47:59,887 WARN L180 SmtUtils]: Spent 135.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 38 [2018-11-23 05:48:00,165 WARN L180 SmtUtils]: Spent 150.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 40 [2018-11-23 05:48:00,663 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 43 [2018-11-23 05:48:01,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:48:01,328 INFO L93 Difference]: Finished difference Result 255 states and 331 transitions. [2018-11-23 05:48:01,329 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-23 05:48:01,330 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 73 [2018-11-23 05:48:01,330 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:48:01,330 INFO L225 Difference]: With dead ends: 255 [2018-11-23 05:48:01,330 INFO L226 Difference]: Without dead ends: 244 [2018-11-23 05:48:01,331 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 155 GetRequests, 124 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 78 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=196, Invalid=796, Unknown=0, NotChecked=0, Total=992 [2018-11-23 05:48:01,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 244 states. [2018-11-23 05:48:01,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 244 to 231. [2018-11-23 05:48:01,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 231 states. [2018-11-23 05:48:01,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 231 states to 231 states and 303 transitions. [2018-11-23 05:48:01,359 INFO L78 Accepts]: Start accepts. Automaton has 231 states and 303 transitions. Word has length 73 [2018-11-23 05:48:01,359 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:48:01,359 INFO L480 AbstractCegarLoop]: Abstraction has 231 states and 303 transitions. [2018-11-23 05:48:01,359 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-23 05:48:01,359 INFO L276 IsEmpty]: Start isEmpty. Operand 231 states and 303 transitions. [2018-11-23 05:48:01,360 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-11-23 05:48:01,360 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:48:01,360 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:48:01,360 INFO L423 AbstractCegarLoop]: === Iteration 37 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:48:01,361 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:48:01,361 INFO L82 PathProgramCache]: Analyzing trace with hash -1573324402, now seen corresponding path program 1 times [2018-11-23 05:48:01,361 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:48:01,361 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:48:01,374 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:48:01,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:48:01,452 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:48:01,791 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 6 proven. 13 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-11-23 05:48:01,791 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:48:02,513 WARN L180 SmtUtils]: Spent 199.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 46 [2018-11-23 05:48:03,439 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 6 proven. 14 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-11-23 05:48:03,441 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:48:03,441 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 15] total 24 [2018-11-23 05:48:03,441 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-23 05:48:03,442 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-23 05:48:03,442 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=473, Unknown=0, NotChecked=0, Total=552 [2018-11-23 05:48:03,442 INFO L87 Difference]: Start difference. First operand 231 states and 303 transitions. Second operand 24 states. [2018-11-23 05:48:06,057 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 29 [2018-11-23 05:48:06,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:48:06,625 INFO L93 Difference]: Finished difference Result 327 states and 409 transitions. [2018-11-23 05:48:06,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-11-23 05:48:06,627 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 77 [2018-11-23 05:48:06,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:48:06,628 INFO L225 Difference]: With dead ends: 327 [2018-11-23 05:48:06,628 INFO L226 Difference]: Without dead ends: 235 [2018-11-23 05:48:06,629 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 168 GetRequests, 130 SyntacticMatches, 1 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 146 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=262, Invalid=1220, Unknown=0, NotChecked=0, Total=1482 [2018-11-23 05:48:06,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235 states. [2018-11-23 05:48:06,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235 to 221. [2018-11-23 05:48:06,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 221 states. [2018-11-23 05:48:06,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 285 transitions. [2018-11-23 05:48:06,656 INFO L78 Accepts]: Start accepts. Automaton has 221 states and 285 transitions. Word has length 77 [2018-11-23 05:48:06,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:48:06,657 INFO L480 AbstractCegarLoop]: Abstraction has 221 states and 285 transitions. [2018-11-23 05:48:06,657 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-23 05:48:06,657 INFO L276 IsEmpty]: Start isEmpty. Operand 221 states and 285 transitions. [2018-11-23 05:48:06,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-23 05:48:06,658 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:48:06,658 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:48:06,658 INFO L423 AbstractCegarLoop]: === Iteration 38 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:48:06,658 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:48:06,658 INFO L82 PathProgramCache]: Analyzing trace with hash -880217657, now seen corresponding path program 2 times [2018-11-23 05:48:06,658 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:48:06,658 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 42 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:48:06,672 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 05:48:06,743 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:48:06,743 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:48:06,755 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:48:07,077 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 7 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-23 05:48:07,077 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:48:08,130 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 8 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-23 05:48:08,132 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:48:08,132 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13] total 22 [2018-11-23 05:48:08,132 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-23 05:48:08,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-23 05:48:08,132 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=388, Unknown=0, NotChecked=0, Total=462 [2018-11-23 05:48:08,133 INFO L87 Difference]: Start difference. First operand 221 states and 285 transitions. Second operand 22 states. [2018-11-23 05:48:08,643 WARN L180 SmtUtils]: Spent 214.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 41 [2018-11-23 05:48:09,217 WARN L180 SmtUtils]: Spent 261.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 38 [2018-11-23 05:48:09,643 WARN L180 SmtUtils]: Spent 232.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 40 [2018-11-23 05:48:09,917 WARN L180 SmtUtils]: Spent 183.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 43 [2018-11-23 05:48:10,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:48:10,845 INFO L93 Difference]: Finished difference Result 247 states and 314 transitions. [2018-11-23 05:48:10,846 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 05:48:10,846 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 73 [2018-11-23 05:48:10,847 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:48:10,848 INFO L225 Difference]: With dead ends: 247 [2018-11-23 05:48:10,848 INFO L226 Difference]: Without dead ends: 230 [2018-11-23 05:48:10,848 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 155 GetRequests, 124 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 80 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=192, Invalid=800, Unknown=0, NotChecked=0, Total=992 [2018-11-23 05:48:10,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230 states. [2018-11-23 05:48:10,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230 to 215. [2018-11-23 05:48:10,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 215 states. [2018-11-23 05:48:10,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215 states to 215 states and 272 transitions. [2018-11-23 05:48:10,875 INFO L78 Accepts]: Start accepts. Automaton has 215 states and 272 transitions. Word has length 73 [2018-11-23 05:48:10,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:48:10,875 INFO L480 AbstractCegarLoop]: Abstraction has 215 states and 272 transitions. [2018-11-23 05:48:10,875 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-23 05:48:10,875 INFO L276 IsEmpty]: Start isEmpty. Operand 215 states and 272 transitions. [2018-11-23 05:48:10,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-11-23 05:48:10,876 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:48:10,876 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:48:10,877 INFO L423 AbstractCegarLoop]: === Iteration 39 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:48:10,877 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:48:10,877 INFO L82 PathProgramCache]: Analyzing trace with hash -1211717294, now seen corresponding path program 2 times [2018-11-23 05:48:10,877 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:48:10,877 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:48:10,891 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 05:48:10,975 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:48:10,975 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:48:10,993 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:48:11,354 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 6 proven. 13 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-11-23 05:48:11,354 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:48:12,198 WARN L180 SmtUtils]: Spent 111.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 41 [2018-11-23 05:48:13,280 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 9 proven. 11 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-11-23 05:48:13,282 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:48:13,282 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15] total 25 [2018-11-23 05:48:13,282 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-11-23 05:48:13,283 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-11-23 05:48:13,283 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=100, Invalid=500, Unknown=0, NotChecked=0, Total=600 [2018-11-23 05:48:13,283 INFO L87 Difference]: Start difference. First operand 215 states and 272 transitions. Second operand 25 states. [2018-11-23 05:48:15,211 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 35 DAG size of output: 33 [2018-11-23 05:48:15,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:48:15,693 INFO L93 Difference]: Finished difference Result 254 states and 316 transitions. [2018-11-23 05:48:15,695 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-11-23 05:48:15,695 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 77 [2018-11-23 05:48:15,695 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:48:15,696 INFO L225 Difference]: With dead ends: 254 [2018-11-23 05:48:15,696 INFO L226 Difference]: Without dead ends: 212 [2018-11-23 05:48:15,697 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 164 GetRequests, 127 SyntacticMatches, 3 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 124 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=230, Invalid=1030, Unknown=0, NotChecked=0, Total=1260 [2018-11-23 05:48:15,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states. [2018-11-23 05:48:15,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 201. [2018-11-23 05:48:15,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 201 states. [2018-11-23 05:48:15,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 250 transitions. [2018-11-23 05:48:15,742 INFO L78 Accepts]: Start accepts. Automaton has 201 states and 250 transitions. Word has length 77 [2018-11-23 05:48:15,742 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:48:15,743 INFO L480 AbstractCegarLoop]: Abstraction has 201 states and 250 transitions. [2018-11-23 05:48:15,743 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-11-23 05:48:15,743 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 250 transitions. [2018-11-23 05:48:15,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2018-11-23 05:48:15,743 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:48:15,744 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:48:15,744 INFO L423 AbstractCegarLoop]: === Iteration 40 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:48:15,744 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:48:15,744 INFO L82 PathProgramCache]: Analyzing trace with hash 1374225982, now seen corresponding path program 1 times [2018-11-23 05:48:15,744 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:48:15,744 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 44 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:48:15,755 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:48:15,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:48:15,777 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:48:15,803 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-11-23 05:48:15,803 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 05:48:15,804 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:48:15,805 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 05:48:15,805 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 05:48:15,805 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 05:48:15,805 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 05:48:15,805 INFO L87 Difference]: Start difference. First operand 201 states and 250 transitions. Second operand 6 states. [2018-11-23 05:48:15,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:48:15,851 INFO L93 Difference]: Finished difference Result 216 states and 266 transitions. [2018-11-23 05:48:15,852 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 05:48:15,852 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 75 [2018-11-23 05:48:15,852 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:48:15,853 INFO L225 Difference]: With dead ends: 216 [2018-11-23 05:48:15,853 INFO L226 Difference]: Without dead ends: 204 [2018-11-23 05:48:15,853 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 70 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 05:48:15,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204 states. [2018-11-23 05:48:15,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204 to 201. [2018-11-23 05:48:15,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 201 states. [2018-11-23 05:48:15,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 244 transitions. [2018-11-23 05:48:15,886 INFO L78 Accepts]: Start accepts. Automaton has 201 states and 244 transitions. Word has length 75 [2018-11-23 05:48:15,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:48:15,886 INFO L480 AbstractCegarLoop]: Abstraction has 201 states and 244 transitions. [2018-11-23 05:48:15,886 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 05:48:15,886 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 244 transitions. [2018-11-23 05:48:15,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-11-23 05:48:15,887 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:48:15,887 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:48:15,887 INFO L423 AbstractCegarLoop]: === Iteration 41 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:48:15,887 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:48:15,887 INFO L82 PathProgramCache]: Analyzing trace with hash 1637188566, now seen corresponding path program 1 times [2018-11-23 05:48:15,887 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:48:15,887 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:48:15,900 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:48:15,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:48:15,956 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:48:16,154 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 18 proven. 3 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-23 05:48:16,154 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:48:16,317 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:48:16,317 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:48:16,324 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:48:16,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:48:16,344 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:48:16,594 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 24 proven. 3 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-23 05:48:16,595 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:48:16,822 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:48:16,822 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 15] total 15 [2018-11-23 05:48:16,823 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-23 05:48:16,823 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-23 05:48:16,823 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-11-23 05:48:16,823 INFO L87 Difference]: Start difference. First operand 201 states and 244 transitions. Second operand 15 states. [2018-11-23 05:48:17,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:48:17,711 INFO L93 Difference]: Finished difference Result 223 states and 271 transitions. [2018-11-23 05:48:17,711 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 05:48:17,712 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 80 [2018-11-23 05:48:17,712 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:48:17,712 INFO L225 Difference]: With dead ends: 223 [2018-11-23 05:48:17,712 INFO L226 Difference]: Without dead ends: 214 [2018-11-23 05:48:17,713 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 161 SyntacticMatches, 2 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 43 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=67, Invalid=439, Unknown=0, NotChecked=0, Total=506 [2018-11-23 05:48:17,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states. [2018-11-23 05:48:17,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 207. [2018-11-23 05:48:17,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-11-23 05:48:17,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 255 transitions. [2018-11-23 05:48:17,736 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 255 transitions. Word has length 80 [2018-11-23 05:48:17,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:48:17,736 INFO L480 AbstractCegarLoop]: Abstraction has 207 states and 255 transitions. [2018-11-23 05:48:17,736 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-23 05:48:17,736 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 255 transitions. [2018-11-23 05:48:17,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-11-23 05:48:17,736 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:48:17,736 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:48:17,737 INFO L423 AbstractCegarLoop]: === Iteration 42 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:48:17,737 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:48:17,737 INFO L82 PathProgramCache]: Analyzing trace with hash -1359709994, now seen corresponding path program 1 times [2018-11-23 05:48:17,737 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:48:17,737 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:48:17,749 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:48:17,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:48:17,845 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:48:18,441 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 8 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-11-23 05:48:18,441 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:48:20,916 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 9 proven. 6 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-23 05:48:20,917 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:48:20,917 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15] total 26 [2018-11-23 05:48:20,917 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-23 05:48:20,917 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-23 05:48:20,918 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=114, Invalid=536, Unknown=0, NotChecked=0, Total=650 [2018-11-23 05:48:20,918 INFO L87 Difference]: Start difference. First operand 207 states and 255 transitions. Second operand 26 states. [2018-11-23 05:48:22,756 WARN L180 SmtUtils]: Spent 188.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 32 [2018-11-23 05:48:23,096 WARN L180 SmtUtils]: Spent 186.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 38 [2018-11-23 05:48:24,483 WARN L180 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 38 [2018-11-23 05:48:25,539 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 36 [2018-11-23 05:48:25,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:48:25,955 INFO L93 Difference]: Finished difference Result 250 states and 304 transitions. [2018-11-23 05:48:25,956 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-23 05:48:25,956 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 80 [2018-11-23 05:48:25,956 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:48:25,957 INFO L225 Difference]: With dead ends: 250 [2018-11-23 05:48:25,957 INFO L226 Difference]: Without dead ends: 220 [2018-11-23 05:48:25,957 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 174 GetRequests, 133 SyntacticMatches, 2 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 136 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=318, Invalid=1322, Unknown=0, NotChecked=0, Total=1640 [2018-11-23 05:48:25,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220 states. [2018-11-23 05:48:25,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220 to 180. [2018-11-23 05:48:25,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2018-11-23 05:48:25,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 223 transitions. [2018-11-23 05:48:25,978 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 223 transitions. Word has length 80 [2018-11-23 05:48:25,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:48:25,978 INFO L480 AbstractCegarLoop]: Abstraction has 180 states and 223 transitions. [2018-11-23 05:48:25,978 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-23 05:48:25,978 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 223 transitions. [2018-11-23 05:48:25,978 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-11-23 05:48:25,978 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:48:25,978 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:48:25,979 INFO L423 AbstractCegarLoop]: === Iteration 43 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:48:25,979 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:48:25,979 INFO L82 PathProgramCache]: Analyzing trace with hash -1037358574, now seen corresponding path program 2 times [2018-11-23 05:48:25,979 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:48:25,979 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 48 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:48:25,991 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 05:48:26,093 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:48:26,093 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:48:26,110 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:48:26,737 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 8 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-11-23 05:48:26,737 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:48:29,251 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 9 proven. 6 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-23 05:48:29,252 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:48:29,252 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15] total 26 [2018-11-23 05:48:29,252 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-23 05:48:29,253 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-23 05:48:29,253 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=109, Invalid=541, Unknown=0, NotChecked=0, Total=650 [2018-11-23 05:48:29,253 INFO L87 Difference]: Start difference. First operand 180 states and 223 transitions. Second operand 26 states. [2018-11-23 05:48:29,592 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 29 [2018-11-23 05:48:30,076 WARN L180 SmtUtils]: Spent 205.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 38 [2018-11-23 05:48:30,651 WARN L180 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 37 [2018-11-23 05:48:31,315 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 32 [2018-11-23 05:48:31,658 WARN L180 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 35 [2018-11-23 05:48:32,136 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 29 [2018-11-23 05:48:32,710 WARN L180 SmtUtils]: Spent 409.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 38 [2018-11-23 05:48:33,354 WARN L180 SmtUtils]: Spent 406.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 38 [2018-11-23 05:48:34,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:48:34,848 INFO L93 Difference]: Finished difference Result 237 states and 286 transitions. [2018-11-23 05:48:34,849 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-11-23 05:48:34,849 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 80 [2018-11-23 05:48:34,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:48:34,850 INFO L225 Difference]: With dead ends: 237 [2018-11-23 05:48:34,850 INFO L226 Difference]: Without dead ends: 217 [2018-11-23 05:48:34,851 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 174 GetRequests, 133 SyntacticMatches, 2 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 140 ImplicationChecksByTransitivity, 5.9s TimeCoverageRelationStatistics Valid=313, Invalid=1327, Unknown=0, NotChecked=0, Total=1640 [2018-11-23 05:48:34,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states. [2018-11-23 05:48:34,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 185. [2018-11-23 05:48:34,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 185 states. [2018-11-23 05:48:34,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 226 transitions. [2018-11-23 05:48:34,872 INFO L78 Accepts]: Start accepts. Automaton has 185 states and 226 transitions. Word has length 80 [2018-11-23 05:48:34,872 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:48:34,873 INFO L480 AbstractCegarLoop]: Abstraction has 185 states and 226 transitions. [2018-11-23 05:48:34,873 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-23 05:48:34,873 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 226 transitions. [2018-11-23 05:48:34,873 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-11-23 05:48:34,873 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:48:34,873 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:48:34,873 INFO L423 AbstractCegarLoop]: === Iteration 44 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:48:34,873 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:48:34,873 INFO L82 PathProgramCache]: Analyzing trace with hash 1128172057, now seen corresponding path program 1 times [2018-11-23 05:48:34,874 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:48:34,874 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:48:34,887 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:48:34,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:48:34,910 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:48:34,968 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 17 proven. 5 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-23 05:48:34,969 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:48:35,114 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 19 proven. 3 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-23 05:48:35,115 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:48:35,115 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10] total 18 [2018-11-23 05:48:35,115 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-23 05:48:35,115 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-23 05:48:35,115 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=263, Unknown=0, NotChecked=0, Total=306 [2018-11-23 05:48:35,116 INFO L87 Difference]: Start difference. First operand 185 states and 226 transitions. Second operand 18 states. [2018-11-23 05:48:35,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:48:35,571 INFO L93 Difference]: Finished difference Result 207 states and 251 transitions. [2018-11-23 05:48:35,572 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 05:48:35,572 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 81 [2018-11-23 05:48:35,572 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:48:35,573 INFO L225 Difference]: With dead ends: 207 [2018-11-23 05:48:35,573 INFO L226 Difference]: Without dead ends: 158 [2018-11-23 05:48:35,573 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 172 GetRequests, 149 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 36 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=94, Invalid=506, Unknown=0, NotChecked=0, Total=600 [2018-11-23 05:48:35,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states. [2018-11-23 05:48:35,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 149. [2018-11-23 05:48:35,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-11-23 05:48:35,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 187 transitions. [2018-11-23 05:48:35,590 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 187 transitions. Word has length 81 [2018-11-23 05:48:35,591 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:48:35,591 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 187 transitions. [2018-11-23 05:48:35,591 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-23 05:48:35,591 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 187 transitions. [2018-11-23 05:48:35,591 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-11-23 05:48:35,591 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:48:35,591 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:48:35,591 INFO L423 AbstractCegarLoop]: === Iteration 45 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:48:35,591 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:48:35,592 INFO L82 PathProgramCache]: Analyzing trace with hash -1581370087, now seen corresponding path program 1 times [2018-11-23 05:48:35,592 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:48:35,592 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 50 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:48:35,606 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:48:35,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:48:35,628 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:48:35,683 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-23 05:48:35,683 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:48:35,808 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-23 05:48:35,809 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:48:35,809 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 15 [2018-11-23 05:48:35,809 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-23 05:48:35,809 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-23 05:48:35,809 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2018-11-23 05:48:35,809 INFO L87 Difference]: Start difference. First operand 149 states and 187 transitions. Second operand 15 states. [2018-11-23 05:48:36,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:48:36,157 INFO L93 Difference]: Finished difference Result 169 states and 208 transitions. [2018-11-23 05:48:36,158 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-23 05:48:36,158 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 81 [2018-11-23 05:48:36,158 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:48:36,159 INFO L225 Difference]: With dead ends: 169 [2018-11-23 05:48:36,159 INFO L226 Difference]: Without dead ends: 145 [2018-11-23 05:48:36,159 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 168 GetRequests, 146 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=99, Invalid=363, Unknown=0, NotChecked=0, Total=462 [2018-11-23 05:48:36,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-11-23 05:48:36,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 145. [2018-11-23 05:48:36,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-11-23 05:48:36,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 180 transitions. [2018-11-23 05:48:36,177 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 180 transitions. Word has length 81 [2018-11-23 05:48:36,177 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:48:36,177 INFO L480 AbstractCegarLoop]: Abstraction has 145 states and 180 transitions. [2018-11-23 05:48:36,177 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-23 05:48:36,177 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 180 transitions. [2018-11-23 05:48:36,178 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-11-23 05:48:36,178 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:48:36,178 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:48:36,178 INFO L423 AbstractCegarLoop]: === Iteration 46 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:48:36,178 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:48:36,178 INFO L82 PathProgramCache]: Analyzing trace with hash 1716375510, now seen corresponding path program 1 times [2018-11-23 05:48:36,179 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:48:36,179 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:48:36,201 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:48:36,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:48:36,296 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:48:36,899 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 8 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-11-23 05:48:36,899 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:48:39,157 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-23 05:48:39,158 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:48:39,158 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15] total 26 [2018-11-23 05:48:39,158 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-23 05:48:39,158 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-23 05:48:39,159 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=557, Unknown=0, NotChecked=0, Total=650 [2018-11-23 05:48:39,159 INFO L87 Difference]: Start difference. First operand 145 states and 180 transitions. Second operand 26 states. [2018-11-23 05:48:39,725 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 44 [2018-11-23 05:48:42,428 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 36 [2018-11-23 05:48:43,252 WARN L180 SmtUtils]: Spent 203.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 41 [2018-11-23 05:48:43,943 WARN L180 SmtUtils]: Spent 205.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 45 [2018-11-23 05:48:44,443 WARN L180 SmtUtils]: Spent 182.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 45 [2018-11-23 05:48:44,763 WARN L180 SmtUtils]: Spent 174.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 42 [2018-11-23 05:48:45,440 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 50 [2018-11-23 05:48:45,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:48:45,958 INFO L93 Difference]: Finished difference Result 189 states and 230 transitions. [2018-11-23 05:48:45,960 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-11-23 05:48:45,960 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 78 [2018-11-23 05:48:45,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:48:45,961 INFO L225 Difference]: With dead ends: 189 [2018-11-23 05:48:45,961 INFO L226 Difference]: Without dead ends: 165 [2018-11-23 05:48:45,961 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 179 GetRequests, 128 SyntacticMatches, 3 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 301 ImplicationChecksByTransitivity, 6.5s TimeCoverageRelationStatistics Valid=430, Invalid=2020, Unknown=0, NotChecked=0, Total=2450 [2018-11-23 05:48:45,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-11-23 05:48:45,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 153. [2018-11-23 05:48:45,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 153 states. [2018-11-23 05:48:45,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 188 transitions. [2018-11-23 05:48:45,994 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 188 transitions. Word has length 78 [2018-11-23 05:48:45,994 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:48:45,994 INFO L480 AbstractCegarLoop]: Abstraction has 153 states and 188 transitions. [2018-11-23 05:48:45,994 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-23 05:48:45,994 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 188 transitions. [2018-11-23 05:48:45,995 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-11-23 05:48:45,995 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:48:45,995 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:48:45,995 INFO L423 AbstractCegarLoop]: === Iteration 47 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:48:45,995 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:48:45,995 INFO L82 PathProgramCache]: Analyzing trace with hash -178410659, now seen corresponding path program 2 times [2018-11-23 05:48:45,996 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:48:45,996 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 52 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:48:46,010 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 05:48:46,055 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:48:46,055 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:48:46,058 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:48:46,119 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-23 05:48:46,119 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:48:46,240 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-23 05:48:46,241 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:48:46,241 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 15 [2018-11-23 05:48:46,241 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-23 05:48:46,242 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-23 05:48:46,242 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2018-11-23 05:48:46,242 INFO L87 Difference]: Start difference. First operand 153 states and 188 transitions. Second operand 15 states. [2018-11-23 05:48:46,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:48:46,618 INFO L93 Difference]: Finished difference Result 160 states and 194 transitions. [2018-11-23 05:48:46,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 05:48:46,619 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 81 [2018-11-23 05:48:46,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:48:46,619 INFO L225 Difference]: With dead ends: 160 [2018-11-23 05:48:46,619 INFO L226 Difference]: Without dead ends: 110 [2018-11-23 05:48:46,620 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 168 GetRequests, 146 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=102, Invalid=360, Unknown=0, NotChecked=0, Total=462 [2018-11-23 05:48:46,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2018-11-23 05:48:46,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 107. [2018-11-23 05:48:46,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107 states. [2018-11-23 05:48:46,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 134 transitions. [2018-11-23 05:48:46,631 INFO L78 Accepts]: Start accepts. Automaton has 107 states and 134 transitions. Word has length 81 [2018-11-23 05:48:46,631 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:48:46,631 INFO L480 AbstractCegarLoop]: Abstraction has 107 states and 134 transitions. [2018-11-23 05:48:46,631 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-23 05:48:46,631 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 134 transitions. [2018-11-23 05:48:46,632 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-11-23 05:48:46,632 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:48:46,632 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:48:46,632 INFO L423 AbstractCegarLoop]: === Iteration 48 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:48:46,632 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:48:46,632 INFO L82 PathProgramCache]: Analyzing trace with hash -1512796842, now seen corresponding path program 2 times [2018-11-23 05:48:46,632 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:48:46,632 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:48:46,647 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 05:48:46,747 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:48:46,747 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:48:46,764 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:48:47,381 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 8 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-11-23 05:48:47,382 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:48:49,678 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-23 05:48:49,680 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:48:49,680 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15] total 26 [2018-11-23 05:48:49,680 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-23 05:48:49,680 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-23 05:48:49,680 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=559, Unknown=0, NotChecked=0, Total=650 [2018-11-23 05:48:49,681 INFO L87 Difference]: Start difference. First operand 107 states and 134 transitions. Second operand 26 states. [2018-11-23 05:48:50,228 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 55 [2018-11-23 05:48:51,188 WARN L180 SmtUtils]: Spent 275.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 68 [2018-11-23 05:48:51,787 WARN L180 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 54 [2018-11-23 05:48:52,746 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 40 [2018-11-23 05:48:53,232 WARN L180 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 38 [2018-11-23 05:48:53,508 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 50 [2018-11-23 05:48:55,272 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 40 [2018-11-23 05:48:55,614 WARN L180 SmtUtils]: Spent 209.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 40 [2018-11-23 05:48:55,996 WARN L180 SmtUtils]: Spent 136.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 41 [2018-11-23 05:48:56,346 WARN L180 SmtUtils]: Spent 212.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 44 [2018-11-23 05:48:56,734 WARN L180 SmtUtils]: Spent 192.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 44 [2018-11-23 05:48:56,997 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 35 [2018-11-23 05:48:57,333 WARN L180 SmtUtils]: Spent 199.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 41 [2018-11-23 05:48:57,617 WARN L180 SmtUtils]: Spent 175.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 41 [2018-11-23 05:48:58,043 WARN L180 SmtUtils]: Spent 149.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 50 [2018-11-23 05:48:58,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:48:58,571 INFO L93 Difference]: Finished difference Result 151 states and 184 transitions. [2018-11-23 05:48:58,573 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-11-23 05:48:58,573 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 78 [2018-11-23 05:48:58,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:48:58,574 INFO L225 Difference]: With dead ends: 151 [2018-11-23 05:48:58,574 INFO L226 Difference]: Without dead ends: 138 [2018-11-23 05:48:58,574 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 180 GetRequests, 128 SyntacticMatches, 3 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 317 ImplicationChecksByTransitivity, 8.1s TimeCoverageRelationStatistics Valid=446, Invalid=2104, Unknown=0, NotChecked=0, Total=2550 [2018-11-23 05:48:58,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-11-23 05:48:58,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 126. [2018-11-23 05:48:58,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-11-23 05:48:58,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 157 transitions. [2018-11-23 05:48:58,591 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 157 transitions. Word has length 78 [2018-11-23 05:48:58,591 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:48:58,591 INFO L480 AbstractCegarLoop]: Abstraction has 126 states and 157 transitions. [2018-11-23 05:48:58,591 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-23 05:48:58,591 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 157 transitions. [2018-11-23 05:48:58,591 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-11-23 05:48:58,591 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:48:58,592 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:48:58,592 INFO L423 AbstractCegarLoop]: === Iteration 49 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:48:58,592 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:48:58,592 INFO L82 PathProgramCache]: Analyzing trace with hash -1425060131, now seen corresponding path program 1 times [2018-11-23 05:48:58,592 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:48:58,592 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 54 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:48:58,616 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:48:58,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:48:58,640 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:48:58,718 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-23 05:48:58,718 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:48:58,891 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-23 05:48:58,892 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:48:58,892 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 15 [2018-11-23 05:48:58,893 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-23 05:48:58,893 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-23 05:48:58,893 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2018-11-23 05:48:58,893 INFO L87 Difference]: Start difference. First operand 126 states and 157 transitions. Second operand 15 states. [2018-11-23 05:48:59,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:48:59,329 INFO L93 Difference]: Finished difference Result 138 states and 169 transitions. [2018-11-23 05:48:59,329 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 05:48:59,330 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 79 [2018-11-23 05:48:59,330 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:48:59,330 INFO L225 Difference]: With dead ends: 138 [2018-11-23 05:48:59,330 INFO L226 Difference]: Without dead ends: 128 [2018-11-23 05:48:59,331 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 164 GetRequests, 142 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=102, Invalid=360, Unknown=0, NotChecked=0, Total=462 [2018-11-23 05:48:59,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-11-23 05:48:59,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 117. [2018-11-23 05:48:59,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-11-23 05:48:59,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 145 transitions. [2018-11-23 05:48:59,345 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 145 transitions. Word has length 79 [2018-11-23 05:48:59,346 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:48:59,346 INFO L480 AbstractCegarLoop]: Abstraction has 117 states and 145 transitions. [2018-11-23 05:48:59,346 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-23 05:48:59,346 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 145 transitions. [2018-11-23 05:48:59,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-11-23 05:48:59,346 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:48:59,346 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:48:59,347 INFO L423 AbstractCegarLoop]: === Iteration 50 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:48:59,347 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:48:59,347 INFO L82 PathProgramCache]: Analyzing trace with hash -1418902222, now seen corresponding path program 1 times [2018-11-23 05:48:59,347 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:48:59,347 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:48:59,366 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:48:59,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:48:59,671 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:49:01,319 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 10 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-23 05:49:01,319 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:49:01,881 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification that was a NOOP. DAG size: 56 [2018-11-23 05:49:02,968 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:49:02,968 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:49:02,975 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:49:03,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:49:03,745 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:49:03,774 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 10 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-23 05:49:03,774 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:49:04,049 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification that was a NOOP. DAG size: 56 [2018-11-23 05:49:04,154 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification that was a NOOP. DAG size: 56 [2018-11-23 05:49:04,470 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:49:04,470 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 20 [2018-11-23 05:49:04,471 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-23 05:49:04,471 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-23 05:49:04,471 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=593, Unknown=0, NotChecked=0, Total=650 [2018-11-23 05:49:04,471 INFO L87 Difference]: Start difference. First operand 117 states and 145 transitions. Second operand 20 states. [2018-11-23 05:49:08,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:49:08,898 INFO L93 Difference]: Finished difference Result 131 states and 160 transitions. [2018-11-23 05:49:08,900 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-23 05:49:08,900 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 83 [2018-11-23 05:49:08,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:49:08,901 INFO L225 Difference]: With dead ends: 131 [2018-11-23 05:49:08,901 INFO L226 Difference]: Without dead ends: 122 [2018-11-23 05:49:08,901 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 202 GetRequests, 163 SyntacticMatches, 1 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 161 ImplicationChecksByTransitivity, 5.2s TimeCoverageRelationStatistics Valid=129, Invalid=1431, Unknown=0, NotChecked=0, Total=1560 [2018-11-23 05:49:08,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states. [2018-11-23 05:49:08,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 117. [2018-11-23 05:49:08,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-11-23 05:49:08,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 144 transitions. [2018-11-23 05:49:08,917 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 144 transitions. Word has length 83 [2018-11-23 05:49:08,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:49:08,917 INFO L480 AbstractCegarLoop]: Abstraction has 117 states and 144 transitions. [2018-11-23 05:49:08,917 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-23 05:49:08,917 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 144 transitions. [2018-11-23 05:49:08,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-11-23 05:49:08,918 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:49:08,918 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:49:08,918 INFO L423 AbstractCegarLoop]: === Iteration 51 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:49:08,918 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:49:08,918 INFO L82 PathProgramCache]: Analyzing trace with hash -1504804959, now seen corresponding path program 2 times [2018-11-23 05:49:08,918 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:49:08,918 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:49:08,934 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 05:49:08,969 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:49:08,969 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:49:08,972 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:49:09,041 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-23 05:49:09,041 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:49:09,168 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-23 05:49:09,170 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:49:09,170 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 15 [2018-11-23 05:49:09,170 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-23 05:49:09,170 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-23 05:49:09,170 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2018-11-23 05:49:09,170 INFO L87 Difference]: Start difference. First operand 117 states and 144 transitions. Second operand 15 states. [2018-11-23 05:49:09,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:49:09,565 INFO L93 Difference]: Finished difference Result 127 states and 154 transitions. [2018-11-23 05:49:09,565 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-23 05:49:09,565 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 79 [2018-11-23 05:49:09,566 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:49:09,566 INFO L225 Difference]: With dead ends: 127 [2018-11-23 05:49:09,566 INFO L226 Difference]: Without dead ends: 117 [2018-11-23 05:49:09,566 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 164 GetRequests, 141 SyntacticMatches, 3 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=99, Invalid=363, Unknown=0, NotChecked=0, Total=462 [2018-11-23 05:49:09,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-11-23 05:49:09,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 106. [2018-11-23 05:49:09,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-11-23 05:49:09,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 130 transitions. [2018-11-23 05:49:09,578 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 130 transitions. Word has length 79 [2018-11-23 05:49:09,578 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:49:09,579 INFO L480 AbstractCegarLoop]: Abstraction has 106 states and 130 transitions. [2018-11-23 05:49:09,579 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-23 05:49:09,579 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 130 transitions. [2018-11-23 05:49:09,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-11-23 05:49:09,579 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:49:09,579 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:49:09,579 INFO L423 AbstractCegarLoop]: === Iteration 52 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:49:09,580 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:49:09,580 INFO L82 PathProgramCache]: Analyzing trace with hash -1912539214, now seen corresponding path program 2 times [2018-11-23 05:49:09,580 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:49:09,580 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 58 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:49:09,595 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 05:49:09,945 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:49:09,945 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:49:09,963 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:49:11,681 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 10 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-23 05:49:11,681 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:49:12,012 WARN L180 SmtUtils]: Spent 126.00 ms on a formula simplification that was a NOOP. DAG size: 62 [2018-11-23 05:49:12,196 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification that was a NOOP. DAG size: 58 [2018-11-23 05:49:12,317 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification that was a NOOP. DAG size: 58 [2018-11-23 05:49:13,505 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:49:13,505 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:49:13,512 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 05:49:14,360 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:49:14,360 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:49:14,364 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:49:14,733 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 17 proven. 10 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-23 05:49:14,734 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:49:15,064 WARN L180 SmtUtils]: Spent 314.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 69 [2018-11-23 05:49:15,258 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification that was a NOOP. DAG size: 58 [2018-11-23 05:49:15,363 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification that was a NOOP. DAG size: 58 [2018-11-23 05:49:16,111 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:49:16,112 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 22] total 22 [2018-11-23 05:49:16,112 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-23 05:49:16,112 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-23 05:49:16,112 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=746, Unknown=0, NotChecked=0, Total=812 [2018-11-23 05:49:16,112 INFO L87 Difference]: Start difference. First operand 106 states and 130 transitions. Second operand 22 states. [2018-11-23 05:49:21,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:49:21,007 INFO L93 Difference]: Finished difference Result 120 states and 145 transitions. [2018-11-23 05:49:21,008 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-23 05:49:21,008 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 83 [2018-11-23 05:49:21,008 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:49:21,009 INFO L225 Difference]: With dead ends: 120 [2018-11-23 05:49:21,009 INFO L226 Difference]: Without dead ends: 111 [2018-11-23 05:49:21,009 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 158 SyntacticMatches, 3 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 205 ImplicationChecksByTransitivity, 6.5s TimeCoverageRelationStatistics Valid=144, Invalid=1748, Unknown=0, NotChecked=0, Total=1892 [2018-11-23 05:49:21,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-11-23 05:49:21,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 106. [2018-11-23 05:49:21,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-11-23 05:49:21,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 129 transitions. [2018-11-23 05:49:21,031 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 129 transitions. Word has length 83 [2018-11-23 05:49:21,032 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:49:21,032 INFO L480 AbstractCegarLoop]: Abstraction has 106 states and 129 transitions. [2018-11-23 05:49:21,032 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-23 05:49:21,032 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 129 transitions. [2018-11-23 05:49:21,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-23 05:49:21,032 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:49:21,033 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:49:21,033 INFO L423 AbstractCegarLoop]: === Iteration 53 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:49:21,033 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:49:21,033 INFO L82 PathProgramCache]: Analyzing trace with hash -1984707855, now seen corresponding path program 1 times [2018-11-23 05:49:21,033 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:49:21,033 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 60 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:49:21,048 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:49:21,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:49:21,167 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:49:21,619 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 10 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-23 05:49:21,619 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:49:21,733 WARN L180 SmtUtils]: Spent 111.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 42 [2018-11-23 05:49:23,708 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 11 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-11-23 05:49:23,709 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:49:23,709 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14] total 24 [2018-11-23 05:49:23,709 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-23 05:49:23,709 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-23 05:49:23,710 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=470, Unknown=0, NotChecked=0, Total=552 [2018-11-23 05:49:23,710 INFO L87 Difference]: Start difference. First operand 106 states and 129 transitions. Second operand 24 states. [2018-11-23 05:49:24,533 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification that was a NOOP. DAG size: 45 [2018-11-23 05:49:27,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:49:27,736 INFO L93 Difference]: Finished difference Result 131 states and 157 transitions. [2018-11-23 05:49:27,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-23 05:49:27,738 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 84 [2018-11-23 05:49:27,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:49:27,738 INFO L225 Difference]: With dead ends: 131 [2018-11-23 05:49:27,738 INFO L226 Difference]: Without dead ends: 91 [2018-11-23 05:49:27,739 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 185 GetRequests, 145 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 188 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=308, Invalid=1414, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 05:49:27,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-11-23 05:49:27,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 86. [2018-11-23 05:49:27,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-11-23 05:49:27,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 102 transitions. [2018-11-23 05:49:27,748 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 102 transitions. Word has length 84 [2018-11-23 05:49:27,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:49:27,748 INFO L480 AbstractCegarLoop]: Abstraction has 86 states and 102 transitions. [2018-11-23 05:49:27,748 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-23 05:49:27,748 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 102 transitions. [2018-11-23 05:49:27,748 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-23 05:49:27,748 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:49:27,749 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:49:27,749 INFO L423 AbstractCegarLoop]: === Iteration 54 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:49:27,749 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:49:27,749 INFO L82 PathProgramCache]: Analyzing trace with hash -107585423, now seen corresponding path program 2 times [2018-11-23 05:49:27,749 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:49:27,749 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:49:27,764 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 05:49:27,876 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:49:27,876 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:49:27,894 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:49:28,433 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 10 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-23 05:49:28,433 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:49:28,596 WARN L180 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 48 [2018-11-23 05:49:30,601 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 11 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-11-23 05:49:30,602 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:49:30,603 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14] total 24 [2018-11-23 05:49:30,603 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-23 05:49:30,603 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-23 05:49:30,603 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=472, Unknown=0, NotChecked=0, Total=552 [2018-11-23 05:49:30,603 INFO L87 Difference]: Start difference. First operand 86 states and 102 transitions. Second operand 24 states. [2018-11-23 05:49:32,096 WARN L180 SmtUtils]: Spent 181.00 ms on a formula simplification that was a NOOP. DAG size: 63 [2018-11-23 05:49:35,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:49:35,399 INFO L93 Difference]: Finished difference Result 106 states and 123 transitions. [2018-11-23 05:49:35,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-11-23 05:49:35,400 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 84 [2018-11-23 05:49:35,401 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:49:35,401 INFO L225 Difference]: With dead ends: 106 [2018-11-23 05:49:35,401 INFO L226 Difference]: Without dead ends: 73 [2018-11-23 05:49:35,402 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 186 GetRequests, 145 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 195 ImplicationChecksByTransitivity, 4.8s TimeCoverageRelationStatistics Valid=318, Invalid=1488, Unknown=0, NotChecked=0, Total=1806 [2018-11-23 05:49:35,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-11-23 05:49:35,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 73. [2018-11-23 05:49:35,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2018-11-23 05:49:35,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 87 transitions. [2018-11-23 05:49:35,411 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 87 transitions. Word has length 84 [2018-11-23 05:49:35,411 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:49:35,411 INFO L480 AbstractCegarLoop]: Abstraction has 73 states and 87 transitions. [2018-11-23 05:49:35,411 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-23 05:49:35,411 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 87 transitions. [2018-11-23 05:49:35,412 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-11-23 05:49:35,412 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:49:35,412 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:49:35,412 INFO L423 AbstractCegarLoop]: === Iteration 55 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:49:35,412 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:49:35,412 INFO L82 PathProgramCache]: Analyzing trace with hash 593862840, now seen corresponding path program 1 times [2018-11-23 05:49:35,412 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:49:35,412 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 62 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:49:35,428 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:49:35,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:49:35,755 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:49:38,106 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 8 proven. 11 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-23 05:49:38,106 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:49:38,652 WARN L180 SmtUtils]: Spent 319.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 62 [2018-11-23 05:49:40,008 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:49:40,009 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:49:40,017 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:49:40,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:49:40,715 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:49:43,589 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 11 proven. 17 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-23 05:49:43,589 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:49:43,868 WARN L180 SmtUtils]: Spent 276.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 65 [2018-11-23 05:49:44,064 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification that was a NOOP. DAG size: 61 [2018-11-23 05:49:44,184 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification that was a NOOP. DAG size: 61 [2018-11-23 05:49:45,881 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:49:45,882 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 24] total 32 [2018-11-23 05:49:45,882 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-11-23 05:49:45,882 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-11-23 05:49:45,882 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=1612, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 05:49:45,882 INFO L87 Difference]: Start difference. First operand 73 states and 87 transitions. Second operand 32 states. [2018-11-23 05:49:51,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:49:51,965 INFO L93 Difference]: Finished difference Result 82 states and 96 transitions. [2018-11-23 05:49:51,967 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-23 05:49:51,967 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 85 [2018-11-23 05:49:51,967 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:49:51,967 INFO L225 Difference]: With dead ends: 82 [2018-11-23 05:49:51,967 INFO L226 Difference]: Without dead ends: 71 [2018-11-23 05:49:51,968 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 209 GetRequests, 151 SyntacticMatches, 1 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 516 ImplicationChecksByTransitivity, 11.8s TimeCoverageRelationStatistics Valid=210, Invalid=3212, Unknown=0, NotChecked=0, Total=3422 [2018-11-23 05:49:51,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-11-23 05:49:51,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 71. [2018-11-23 05:49:51,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2018-11-23 05:49:51,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 83 transitions. [2018-11-23 05:49:51,975 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 83 transitions. Word has length 85 [2018-11-23 05:49:51,975 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:49:51,975 INFO L480 AbstractCegarLoop]: Abstraction has 71 states and 83 transitions. [2018-11-23 05:49:51,975 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-11-23 05:49:51,975 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 83 transitions. [2018-11-23 05:49:51,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-11-23 05:49:51,975 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:49:51,975 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:49:51,975 INFO L423 AbstractCegarLoop]: === Iteration 56 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:49:51,975 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:49:51,975 INFO L82 PathProgramCache]: Analyzing trace with hash 516304508, now seen corresponding path program 2 times [2018-11-23 05:49:51,976 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:49:51,976 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/cvc4nyu Starting monitored process 64 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:49:51,988 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 05:49:52,267 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:49:52,267 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:49:52,286 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:49:54,641 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 8 proven. 11 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-23 05:49:54,641 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:49:55,095 WARN L180 SmtUtils]: Spent 265.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 68 [2018-11-23 05:49:55,288 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification that was a NOOP. DAG size: 61 [2018-11-23 05:49:55,411 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification that was a NOOP. DAG size: 61 [2018-11-23 05:49:56,620 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:49:56,621 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:49:56,628 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 05:49:57,334 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:49:57,334 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:49:57,338 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:50:01,104 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 11 proven. 17 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-23 05:50:01,105 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:50:01,377 WARN L180 SmtUtils]: Spent 269.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 68 [2018-11-23 05:50:01,596 WARN L180 SmtUtils]: Spent 126.00 ms on a formula simplification that was a NOOP. DAG size: 60 [2018-11-23 05:50:01,717 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification that was a NOOP. DAG size: 60 [2018-11-23 05:50:02,082 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:50:02,082 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 24] total 31 [2018-11-23 05:50:02,082 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-11-23 05:50:02,082 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-11-23 05:50:02,082 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=89, Invalid=1243, Unknown=0, NotChecked=0, Total=1332 [2018-11-23 05:50:02,082 INFO L87 Difference]: Start difference. First operand 71 states and 83 transitions. Second operand 31 states. [2018-11-23 05:50:07,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:50:07,882 INFO L93 Difference]: Finished difference Result 71 states and 83 transitions. [2018-11-23 05:50:07,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-23 05:50:07,884 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 85 [2018-11-23 05:50:07,884 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:50:07,884 INFO L225 Difference]: With dead ends: 71 [2018-11-23 05:50:07,884 INFO L226 Difference]: Without dead ends: 0 [2018-11-23 05:50:07,885 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 209 GetRequests, 155 SyntacticMatches, 2 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 376 ImplicationChecksByTransitivity, 11.3s TimeCoverageRelationStatistics Valid=181, Invalid=2681, Unknown=0, NotChecked=0, Total=2862 [2018-11-23 05:50:07,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 0 states. [2018-11-23 05:50:07,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 0 to 0. [2018-11-23 05:50:07,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 0 states. [2018-11-23 05:50:07,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 0 states to 0 states and 0 transitions. [2018-11-23 05:50:07,885 INFO L78 Accepts]: Start accepts. Automaton has 0 states and 0 transitions. Word has length 85 [2018-11-23 05:50:07,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:50:07,886 INFO L480 AbstractCegarLoop]: Abstraction has 0 states and 0 transitions. [2018-11-23 05:50:07,886 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-11-23 05:50:07,886 INFO L276 IsEmpty]: Start isEmpty. Operand 0 states and 0 transitions. [2018-11-23 05:50:07,886 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 05:50:07,890 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 0 states and 0 transitions. [2018-11-23 05:50:08,196 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-23 05:50:08,820 WARN L180 SmtUtils]: Spent 311.00 ms on a formula simplification. DAG size of input: 361 DAG size of output: 343 [2018-11-23 05:50:08,827 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-23 05:50:08,828 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-23 05:50:08,934 WARN L180 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 260 DAG size of output: 225 [2018-11-23 05:50:08,946 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-23 05:50:08,947 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-23 05:50:09,054 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 249 DAG size of output: 219 [2018-11-23 05:50:09,075 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-23 05:50:09,076 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-23 05:50:09,213 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 250 DAG size of output: 220 [2018-11-23 05:50:09,232 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-23 05:50:09,233 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-23 05:50:09,240 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-23 05:50:09,250 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-23 05:50:09,253 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-23 05:50:09,596 WARN L180 SmtUtils]: Spent 340.00 ms on a formula simplification. DAG size of input: 289 DAG size of output: 278 [2018-11-23 05:50:09,985 WARN L180 SmtUtils]: Spent 387.00 ms on a formula simplification. DAG size of input: 323 DAG size of output: 311 [2018-11-23 05:50:10,232 WARN L180 SmtUtils]: Spent 246.00 ms on a formula simplification. DAG size of input: 342 DAG size of output: 325 [2018-11-23 05:50:10,591 WARN L180 SmtUtils]: Spent 282.00 ms on a formula simplification. DAG size of input: 362 DAG size of output: 347 [2018-11-23 05:50:10,737 WARN L180 SmtUtils]: Spent 145.00 ms on a formula simplification. DAG size of input: 332 DAG size of output: 310 [2018-11-23 05:50:11,197 WARN L180 SmtUtils]: Spent 417.00 ms on a formula simplification. DAG size of input: 398 DAG size of output: 383 [2018-11-23 05:50:11,437 WARN L180 SmtUtils]: Spent 182.00 ms on a formula simplification. DAG size of input: 288 DAG size of output: 267 [2018-11-23 05:50:11,777 WARN L180 SmtUtils]: Spent 240.00 ms on a formula simplification. DAG size of input: 331 DAG size of output: 319 [2018-11-23 05:50:11,885 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-23 05:50:12,100 WARN L180 SmtUtils]: Spent 177.00 ms on a formula simplification. DAG size of input: 290 DAG size of output: 275 [2018-11-23 05:50:12,169 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-23 05:50:12,355 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-23 05:50:12,619 WARN L180 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 291 DAG size of output: 276 [2018-11-23 05:52:36,298 WARN L180 SmtUtils]: Spent 2.39 m on a formula simplification. DAG size of input: 342 DAG size of output: 57 [2018-11-23 05:57:21,808 WARN L180 SmtUtils]: Spent 4.76 m on a formula simplification. DAG size of input: 867 DAG size of output: 180 [2018-11-23 05:57:23,858 WARN L180 SmtUtils]: Spent 2.05 s on a formula simplification. DAG size of input: 137 DAG size of output: 81 [2018-11-23 05:59:08,478 WARN L180 SmtUtils]: Spent 1.74 m on a formula simplification. DAG size of input: 404 DAG size of output: 125 [2018-11-23 05:59:08,481 INFO L451 ceAbstractionStarter]: At program point ULTIMATE.initFINAL(line -1) the Hoare annotation is: true [2018-11-23 05:59:08,481 INFO L448 ceAbstractionStarter]: For program point ULTIMATE.initEXIT(line -1) no Hoare annotation was computed. [2018-11-23 05:59:08,481 INFO L448 ceAbstractionStarter]: For program point L19(lines 19 24) no Hoare annotation was computed. [2018-11-23 05:59:08,481 INFO L448 ceAbstractionStarter]: For program point L48(lines 47 62) no Hoare annotation was computed. [2018-11-23 05:59:08,481 INFO L451 ceAbstractionStarter]: At program point L69(lines 18 71) the Hoare annotation is: true [2018-11-23 05:59:08,481 INFO L448 ceAbstractionStarter]: For program point L28(lines 27 42) no Hoare annotation was computed. [2018-11-23 05:59:08,481 INFO L448 ceAbstractionStarter]: For program point L49(lines 47 62) no Hoare annotation was computed. [2018-11-23 05:59:08,481 INFO L448 ceAbstractionStarter]: For program point L37(lines 37 41) no Hoare annotation was computed. [2018-11-23 05:59:08,481 INFO L451 ceAbstractionStarter]: At program point L37-1(lines 27 42) the Hoare annotation is: true [2018-11-23 05:59:08,481 INFO L448 ceAbstractionStarter]: For program point L25(lines 25 65) no Hoare annotation was computed. [2018-11-23 05:59:08,481 INFO L451 ceAbstractionStarter]: At program point base2fltENTRY(lines 14 72) the Hoare annotation is: true [2018-11-23 05:59:08,481 INFO L448 ceAbstractionStarter]: For program point base2fltFINAL(lines 14 72) no Hoare annotation was computed. [2018-11-23 05:59:08,481 INFO L451 ceAbstractionStarter]: At program point L63(lines 25 65) the Hoare annotation is: true [2018-11-23 05:59:08,481 INFO L448 ceAbstractionStarter]: For program point base2fltEXIT(lines 14 72) no Hoare annotation was computed. [2018-11-23 05:59:08,481 INFO L451 ceAbstractionStarter]: At program point L47-2(lines 47 62) the Hoare annotation is: true [2018-11-23 05:59:08,481 INFO L448 ceAbstractionStarter]: For program point ULTIMATE.startEXIT(line -1) no Hoare annotation was computed. [2018-11-23 05:59:08,481 INFO L451 ceAbstractionStarter]: At program point L-1(line -1) the Hoare annotation is: true [2018-11-23 05:59:08,481 INFO L451 ceAbstractionStarter]: At program point ULTIMATE.startENTRY(line -1) the Hoare annotation is: true [2018-11-23 05:59:08,481 INFO L448 ceAbstractionStarter]: For program point ULTIMATE.startFINAL(line -1) no Hoare annotation was computed. [2018-11-23 05:59:08,482 INFO L448 ceAbstractionStarter]: For program point mainEXIT(lines 214 252) no Hoare annotation was computed. [2018-11-23 05:59:08,482 INFO L448 ceAbstractionStarter]: For program point mainFINAL(lines 214 252) no Hoare annotation was computed. [2018-11-23 05:59:08,482 INFO L448 ceAbstractionStarter]: For program point L236(lines 236 245) no Hoare annotation was computed. [2018-11-23 05:59:08,482 INFO L444 ceAbstractionStarter]: At program point L234(line 234) the Hoare annotation is: (let ((.cse20 (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) main_~a~0))) (.cse15 (bvlshr main_~b~0 (_ bv24 32))) (.cse8 (bvlshr main_~a~0 (_ bv24 32)))) (let ((.cse19 (bvlshr .cse20 (bvadd .cse15 (bvneg (bvadd .cse8 (_ bv4294967168 32))) (_ bv4294967168 32)))) (.cse21 (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) main_~b~0)))) (let ((.cse14 (bvadd .cse19 .cse21)) (.cse7 (bvadd .cse20 (bvlshr .cse21 (bvadd (bvneg (bvadd .cse15 (_ bv4294967168 32))) .cse8 (_ bv4294967168 32)))))) (let ((.cse5 (= (bvand (_ bv33554432 32) .cse7) (_ bv0 32))) (.cse12 (= (_ bv0 32) (bvand (_ bv33554432 32) .cse14))) (.cse3 (= main_~a~0 (_ bv0 32))) (.cse17 (bvult main_~a~0 main_~b~0)) (.cse18 (= main_~b~0 (_ bv0 32)))) (let ((.cse6 (not .cse18)) (.cse9 (not .cse17)) (.cse1 (= (bvadd .cse15 (_ bv4294967041 32)) (_ bv0 32))) (.cse13 (not .cse3)) (.cse0 (not .cse12)) (.cse10 (not .cse5)) (.cse11 (= (bvadd .cse8 (_ bv4294967041 32)) (_ bv0 32))) (.cse2 (= (_ bv4294967295 32) main_~r_add1~0)) (.cse16 (= .cse19 (_ bv0 32))) (.cse4 (= main_~b~0 main_~r_add1~0))) (or (and .cse0 .cse1 .cse2) (and .cse3 .cse4) (and .cse5 .cse6 (= (bvor (bvand (_ bv16777215 32) .cse7) (bvshl .cse8 (_ bv24 32))) main_~r_add1~0) .cse9) (and .cse6 (= main_~r_add1~0 (bvor (bvand (_ bv16777215 32) (bvlshr .cse7 (_ bv1 32))) (bvshl (bvadd .cse8 (_ bv1 32)) (_ bv24 32)))) .cse10 (not .cse11) .cse9) (and .cse12 .cse13 (= main_~r_add1~0 (bvor (bvand (_ bv16777215 32) .cse14) (bvshl .cse15 (_ bv24 32)))) (not .cse16)) (and (not .cse1) .cse13 .cse17 .cse0 (= main_~r_add1~0 (bvor (bvand (_ bv16777215 32) (bvlshr .cse14 (_ bv1 32))) (bvshl (bvadd .cse15 (_ bv1 32)) (_ bv24 32))))) (and .cse10 .cse11 .cse2) (and .cse18 (= main_~a~0 main_~r_add1~0)) (and .cse16 .cse17 .cse4))))))) [2018-11-23 05:59:08,482 INFO L444 ceAbstractionStarter]: At program point L236-2(lines 236 245) the Hoare annotation is: (and (= main_~tmp___0~0 (_ bv0 32)) (= main_~tmp~2 (_ bv0 32))) [2018-11-23 05:59:08,482 INFO L448 ceAbstractionStarter]: For program point L234-1(line 234) no Hoare annotation was computed. [2018-11-23 05:59:08,482 INFO L451 ceAbstractionStarter]: At program point L232(line 232) the Hoare annotation is: true [2018-11-23 05:59:08,482 INFO L448 ceAbstractionStarter]: For program point L232-1(line 232) no Hoare annotation was computed. [2018-11-23 05:59:08,482 INFO L451 ceAbstractionStarter]: At program point L230(line 230) the Hoare annotation is: true [2018-11-23 05:59:08,482 INFO L448 ceAbstractionStarter]: For program point L230-1(line 230) no Hoare annotation was computed. [2018-11-23 05:59:08,482 INFO L451 ceAbstractionStarter]: At program point mainENTRY(lines 214 252) the Hoare annotation is: true [2018-11-23 05:59:08,482 INFO L448 ceAbstractionStarter]: For program point L247(line 247) no Hoare annotation was computed. [2018-11-23 05:59:08,482 INFO L448 ceAbstractionStarter]: For program point L239(lines 239 243) no Hoare annotation was computed. [2018-11-23 05:59:08,482 INFO L448 ceAbstractionStarter]: For program point L239-2(lines 239 243) no Hoare annotation was computed. [2018-11-23 05:59:08,482 INFO L451 ceAbstractionStarter]: At program point L233(line 233) the Hoare annotation is: true [2018-11-23 05:59:08,482 INFO L448 ceAbstractionStarter]: For program point L233-1(line 233) no Hoare annotation was computed. [2018-11-23 05:59:08,483 INFO L451 ceAbstractionStarter]: At program point L231(line 231) the Hoare annotation is: true [2018-11-23 05:59:08,483 INFO L448 ceAbstractionStarter]: For program point L231-1(line 231) no Hoare annotation was computed. [2018-11-23 05:59:08,483 INFO L448 ceAbstractionStarter]: For program point L128(line 128) no Hoare annotation was computed. [2018-11-23 05:59:08,483 INFO L451 ceAbstractionStarter]: At program point addfltENTRY(lines 73 136) the Hoare annotation is: true [2018-11-23 05:59:08,483 INFO L448 ceAbstractionStarter]: For program point addfltFINAL(lines 73 136) no Hoare annotation was computed. [2018-11-23 05:59:08,483 INFO L448 ceAbstractionStarter]: For program point L116(lines 116 121) no Hoare annotation was computed. [2018-11-23 05:59:08,483 INFO L448 ceAbstractionStarter]: For program point L108(lines 108 113) no Hoare annotation was computed. [2018-11-23 05:59:08,483 INFO L444 ceAbstractionStarter]: At program point L104(line 104) the Hoare annotation is: (let ((.cse0 (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) |addflt_#in~b|))) (.cse1 (= addflt_~a |addflt_#in~a|))) (and (or (= .cse0 addflt_~ma~0) .cse1) (let ((.cse2 (and (not (= (_ bv0 32) |addflt_#in~b|)) (exists ((addflt_~b (_ BitVec 32)) (addflt_~a (_ BitVec 32))) (and (= (bvadd addflt_~eb~0 (_ bv128 32)) (bvlshr addflt_~b (_ bv24 32))) (not (bvult addflt_~a addflt_~b)) (= (bvadd (bvlshr addflt_~a (_ bv24 32)) (_ bv4294967168 32)) addflt_~ea~0))) (not (bvult addflt_~a addflt_~b))))) (or (and .cse2 (= addflt_~b |addflt_#in~a|) (= addflt_~a |addflt_#in~b|)) (and .cse2 (= addflt_~b |addflt_#in~b|)))) (let ((.cse3 (bvadd (bvlshr |addflt_#in~b| (_ bv24 32)) (_ bv4294967168 32))) (.cse4 (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) |addflt_#in~a|)))) (or (and (= .cse0 addflt_~mb~0) .cse1 (= .cse3 addflt_~eb~0) (= .cse4 addflt_~ma~0) (= (bvadd (bvlshr addflt_~a (_ bv24 32)) (_ bv4294967168 32)) addflt_~ea~0)) (and (= .cse3 addflt_~ea~0) (= .cse4 addflt_~mb~0) (= (bvadd (bvlshr |addflt_#in~a| (_ bv24 32)) (_ bv4294967168 32)) addflt_~eb~0) (bvult addflt_~b |addflt_#in~b|)))) (not (= (_ bv0 32) |addflt_#in~a|)))) [2018-11-23 05:59:08,483 INFO L448 ceAbstractionStarter]: For program point L104-1(line 104) no Hoare annotation was computed. [2018-11-23 05:59:08,484 INFO L444 ceAbstractionStarter]: At program point L133(lines 83 135) the Hoare annotation is: (let ((.cse4 (bvlshr |addflt_#in~b| (_ bv24 32)))) (let ((.cse39 (bvadd .cse4 (_ bv4294967168 32))) (.cse17 (bvlshr |addflt_#in~a| (_ bv24 32)))) (let ((.cse31 (bvadd .cse17 (_ bv4294967168 32))) (.cse10 (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) |addflt_#in~b|))) (.cse44 (bvneg .cse39))) (let ((.cse45 (bvlshr .cse10 (bvadd .cse17 .cse44 (_ bv4294967168 32)))) (.cse11 (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) |addflt_#in~a|))) (.cse12 (bvneg .cse31))) (let ((.cse47 (bvlshr .cse11 (bvadd .cse4 .cse12 (_ bv4294967168 32)))) (.cse16 (bvadd .cse45 .cse11))) (let ((.cse27 (= (bvand (_ bv33554432 32) .cse16) (_ bv0 32))) (.cse3 (bvadd .cse47 .cse10)) (.cse42 (= addflt_~a |addflt_#in~b|)) (.cse28 (= addflt_~b |addflt_#in~b|)) (.cse43 (= (_ bv0 32) |addflt_#in~b|))) (let ((.cse41 (let ((.cse48 (and (not .cse43) (not (bvult addflt_~a addflt_~b))))) (or (and .cse48 .cse42) (and .cse48 .cse28)))) (.cse1 (= (bvand (_ bv33554432 32) .cse3) (_ bv0 32))) (.cse0 (= (_ bv0 32) (bvand (_ bv33554432 32) addflt_~ma~0))) (.cse24 (not .cse27)) (.cse19 (= (bvadd .cse17 (_ bv4294967041 32)) (_ bv0 32)))) (let ((.cse32 (= addflt_~__retres10~0 |addflt_#in~a|)) (.cse38 (= (_ bv0 32) |addflt_#in~a|)) (.cse36 (bvult addflt_~b |addflt_#in~b|)) (.cse14 (or (not (= (_ bv127 32) addflt_~ea~0)) .cse0 (and .cse24 .cse19))) (.cse9 (not .cse1)) (.cse21 (= addflt_~a |addflt_#in~a|)) (.cse46 (= .cse47 (_ bv0 32))) (.cse8 (= .cse39 addflt_~ea~0)) (.cse37 (and (bvult |addflt_#in~a| |addflt_#in~b|) (and .cse41 (= addflt_~__retres10~0 |addflt_#in~b|) .cse42))) (.cse34 (= .cse47 addflt_~mb~0))) (let ((.cse5 (and .cse46 .cse8 .cse37 .cse34)) (.cse22 (and .cse24 .cse14 (or .cse0 .cse9) (= (bvor (bvand (_ bv16777215 32) (bvlshr .cse16 (_ bv1 32))) (bvshl (bvadd .cse17 (_ bv1 32)) (_ bv24 32))) addflt_~__retres10~0) .cse21)) (.cse2 (or (and (not (= (_ bv255 32) .cse17)) (not .cse46) .cse34 .cse36) (and .cse8 (not (= (_ bv0 32) (bvlshr addflt_~mb~0 (bvadd addflt_~ea~0 (bvneg addflt_~eb~0))))) .cse34 .cse36))) (.cse23 (and .cse38 .cse37)) (.cse6 (= (bvadd addflt_~__retres10~0 (_ bv1 32)) (_ bv0 32))) (.cse26 (not (= .cse45 (_ bv0 32)))) (.cse25 (= (_ bv0 32) (bvlshr .cse10 (bvadd (bvlshr addflt_~__retres10~0 (_ bv24 32)) .cse44 (_ bv4294967168 32))))) (.cse15 (= (bvlshr .cse10 (bvadd (bvlshr addflt_~a (_ bv24 32)) .cse44 (_ bv4294967168 32))) addflt_~mb~0)) (.cse20 (bvlshr .cse10 (bvadd .cse44 addflt_~ea~0))) (.cse18 (and .cse21 .cse43 .cse28 .cse32)) (.cse33 (= addflt_~b |addflt_#in~a|))) (and (let ((.cse7 (= (bvadd .cse4 (_ bv4294967041 32)) (_ bv0 32))) (.cse13 (or .cse24 .cse0))) (or (and .cse0 .cse1 .cse2 (= addflt_~__retres10~0 (bvor (bvand (_ bv16777215 32) .cse3) (bvshl .cse4 (_ bv24 32))))) .cse5 (and .cse6 .cse7 .cse8 .cse9 (= (bvadd .cse10 (bvlshr .cse11 (bvadd .cse12 addflt_~ea~0))) addflt_~ma~0)) (and (= addflt_~__retres10~0 (bvor (bvand (_ bv16777215 32) (bvlshr .cse3 (_ bv1 32))) (bvshl (bvadd .cse4 (_ bv1 32)) (_ bv24 32)))) .cse9 (not .cse7) .cse13 .cse14) (and .cse15 .cse13 (= (bvor (bvand (_ bv16777215 32) .cse16) (bvshl .cse17 (_ bv24 32))) addflt_~__retres10~0)) .cse18 (and .cse19 (not (= (_ bv0 32) (bvand (_ bv33554432 32) (bvadd .cse20 .cse11)))) .cse21) .cse22 .cse23)) (or .cse18 (and (exists ((addflt_~delta~0 (_ BitVec 32)) (addflt_~b (_ BitVec 32)) (addflt_~a (_ BitVec 32))) (= (bvlshr (bvadd (bvneg (bvneg (bvlshr (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) addflt_~b)) addflt_~delta~0))) (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) addflt_~a))) (_ bv1 32)) addflt_~ma~0)) .cse25) .cse5 (and .cse6 .cse21) .cse22 .cse2 (and .cse26 .cse27) .cse23) (let ((.cse29 (= addflt_~mb~0 .cse20)) (.cse30 (= .cse39 addflt_~eb~0)) (.cse35 (not .cse38))) (or .cse18 (and (= .cse16 addflt_~ma~0) .cse28 .cse6 .cse15 .cse26 .cse29 .cse30) (and .cse15 .cse26 .cse27 .cse29 .cse30) (and (= .cse31 addflt_~ea~0) .cse25 .cse32 .cse21 .cse30 (= .cse11 addflt_~ma~0)) (and .cse24 .cse28 .cse15 (not .cse19)) (and (and .cse33 .cse34 .cse35 .cse36) .cse9) (and .cse8 .cse33 .cse34 .cse35 .cse36) .cse37)) (let ((.cse40 (and (or (and .cse41 .cse42) (and .cse41 .cse21)) (not (bvult addflt_~a |addflt_#in~a|))))) (or (and .cse21 .cse40) .cse18 (and .cse40 .cse33))))))))))))) [2018-11-23 05:59:08,484 INFO L448 ceAbstractionStarter]: For program point addfltEXIT(lines 73 136) no Hoare annotation was computed. [2018-11-23 05:59:08,484 INFO L448 ceAbstractionStarter]: For program point L84(lines 84 90) no Hoare annotation was computed. [2018-11-23 05:59:08,484 INFO L448 ceAbstractionStarter]: For program point L115(lines 115 126) no Hoare annotation was computed. [2018-11-23 05:59:08,484 INFO L448 ceAbstractionStarter]: For program point L84-2(lines 83 135) no Hoare annotation was computed. [2018-11-23 05:59:08,485 INFO L444 ceAbstractionStarter]: At program point L115-2(lines 115 126) the Hoare annotation is: (let ((.cse1 (bvlshr |addflt_#in~b| (_ bv24 32))) (.cse16 (bvlshr |addflt_#in~a| (_ bv24 32)))) (let ((.cse9 (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) |addflt_#in~a|))) (.cse14 (bvneg (bvadd .cse16 (_ bv4294967168 32)))) (.cse12 (bvadd .cse1 (_ bv4294967168 32)))) (let ((.cse6 (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) |addflt_#in~b|))) (.cse13 (bvneg .cse12)) (.cse5 (bvlshr .cse9 (bvadd .cse1 .cse14 (_ bv4294967168 32)))) (.cse18 (= addflt_~a |addflt_#in~a|)) (.cse17 (= addflt_~b |addflt_#in~b|)) (.cse21 (and (not (= (_ bv0 32) addflt_~b)) (and (not (= (_ bv0 32) |addflt_#in~b|)) (not (bvult addflt_~a addflt_~b))))) (.cse20 (= addflt_~a |addflt_#in~b|)) (.cse22 (not (bvult addflt_~a |addflt_#in~a|)))) (let ((.cse0 (= addflt_~b |addflt_#in~a|)) (.cse7 (and (let ((.cse23 (let ((.cse24 (= (_ bv0 32) (bvand (_ bv33554432 32) addflt_~ma~0))) (.cse25 (exists ((addflt_~delta~0 (_ BitVec 32)) (addflt_~b (_ BitVec 32)) (addflt_~a (_ BitVec 32))) (= (bvadd (bvneg (bvlshr (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) addflt_~b)) addflt_~delta~0)) addflt_~ma~0) (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) addflt_~a)))))) (or (and .cse24 .cse21 .cse25 .cse17) (and .cse24 .cse21 .cse25 .cse20))))) (or (and .cse18 .cse23) (and .cse23 .cse20))) .cse22)) (.cse3 (= .cse5 addflt_~mb~0)) (.cse10 (= (bvlshr .cse6 (bvadd (bvlshr addflt_~a (_ bv24 32)) .cse13 (_ bv4294967168 32))) addflt_~mb~0)) (.cse4 (and (let ((.cse19 (or (and .cse21 .cse17) (and .cse21 .cse20)))) (or (and .cse19 .cse20) (and .cse18 .cse19))) .cse22)) (.cse11 (bvlshr .cse6 (bvadd .cse16 .cse13 (_ bv4294967168 32))))) (or (let ((.cse2 (bvadd .cse5 .cse6))) (and .cse0 (= (bvadd .cse1 (_ bv4294967169 32)) addflt_~ea~0) (= (bvlshr .cse2 (_ bv1 32)) addflt_~ma~0) (not (= (bvadd .cse1 (_ bv4294967041 32)) (_ bv0 32))) .cse3 .cse4 (not (= (bvand (_ bv33554432 32) .cse2) (_ bv0 32))))) (let ((.cse8 (bvlshr .cse6 (bvadd .cse13 addflt_~ea~0)))) (and .cse7 (= (bvadd .cse8 .cse9) addflt_~ma~0) .cse10 (not (= .cse11 (_ bv0 32))) (= addflt_~mb~0 .cse8) (= .cse12 addflt_~eb~0))) (and .cse0 .cse7 (= .cse12 addflt_~ea~0) .cse3 (not (= (_ bv0 32) (bvadd (bvneg .cse6) addflt_~ma~0))) (= (bvadd .cse6 (bvlshr .cse9 (bvadd .cse14 addflt_~ea~0))) addflt_~ma~0)) (let ((.cse15 (bvadd .cse11 .cse9))) (and (exists ((addflt_~delta~0 (_ BitVec 32)) (addflt_~b (_ BitVec 32)) (addflt_~a (_ BitVec 32))) (= (bvlshr (bvadd (bvneg (bvneg (bvlshr (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) addflt_~b)) addflt_~delta~0))) (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) addflt_~a))) (_ bv1 32)) addflt_~ma~0)) (= (bvlshr .cse15 (_ bv1 32)) addflt_~ma~0) (= (bvadd .cse16 (_ bv4294967169 32)) addflt_~ea~0) .cse17 (not (= (bvand (_ bv33554432 32) .cse15) (_ bv0 32))) .cse10 (not (= (bvadd .cse16 (_ bv4294967041 32)) (_ bv0 32))) .cse18 .cse4))))))) [2018-11-23 05:59:08,485 INFO L451 ceAbstractionStarter]: At program point __VERIFIER_assertENTRY(lines 5 10) the Hoare annotation is: true [2018-11-23 05:59:08,485 INFO L448 ceAbstractionStarter]: For program point __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION(line 7) no Hoare annotation was computed. [2018-11-23 05:59:08,485 INFO L448 ceAbstractionStarter]: For program point __VERIFIER_assertEXIT(lines 5 10) no Hoare annotation was computed. [2018-11-23 05:59:08,485 INFO L448 ceAbstractionStarter]: For program point L7(line 7) no Hoare annotation was computed. [2018-11-23 05:59:08,485 INFO L448 ceAbstractionStarter]: For program point L6(lines 6 8) no Hoare annotation was computed. [2018-11-23 05:59:08,485 INFO L448 ceAbstractionStarter]: For program point L6-2(lines 5 10) no Hoare annotation was computed. [2018-11-23 05:59:08,495 WARN L416 cessorBacktranslator]: Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~b,QUANTIFIED] [2018-11-23 05:59:08,496 WARN L416 cessorBacktranslator]: Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~delta~0,QUANTIFIED] [2018-11-23 05:59:08,496 WARN L416 cessorBacktranslator]: Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~a,QUANTIFIED] [2018-11-23 05:59:08,514 WARN L416 cessorBacktranslator]: Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~b,QUANTIFIED] [2018-11-23 05:59:08,514 WARN L416 cessorBacktranslator]: Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~delta~0,QUANTIFIED] [2018-11-23 05:59:08,515 WARN L416 cessorBacktranslator]: Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~a,QUANTIFIED] [2018-11-23 05:59:08,523 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 05:59:08 BoogieIcfgContainer [2018-11-23 05:59:08,523 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 05:59:08,523 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 05:59:08,523 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 05:59:08,523 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 05:59:08,524 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:46:19" (3/4) ... [2018-11-23 05:59:08,526 INFO L144 WitnessPrinter]: Generating witness for correct program [2018-11-23 05:59:08,532 INFO L354 RCFGBacktranslator]: Ignoring RootEdge to procedure ULTIMATE.init [2018-11-23 05:59:08,532 INFO L354 RCFGBacktranslator]: Ignoring RootEdge to procedure base2flt [2018-11-23 05:59:08,532 INFO L354 RCFGBacktranslator]: Ignoring RootEdge to procedure main [2018-11-23 05:59:08,532 INFO L354 RCFGBacktranslator]: Ignoring RootEdge to procedure addflt [2018-11-23 05:59:08,533 INFO L354 RCFGBacktranslator]: Ignoring RootEdge to procedure __VERIFIER_assert [2018-11-23 05:59:08,537 INFO L879 BoogieBacktranslator]: Reduced CFG by removing 11 nodes and edges [2018-11-23 05:59:08,537 INFO L879 BoogieBacktranslator]: Reduced CFG by removing 4 nodes and edges [2018-11-23 05:59:08,538 INFO L879 BoogieBacktranslator]: Reduced CFG by removing 1 nodes and edges [2018-11-23 05:59:08,561 WARN L221 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((((((0bv32 == ~bvand64(33554432bv32, ma) && ~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32) && ((((!(255bv32 == ~bvlshr64(\old(a), 24bv32)) && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && ~bvult64(b, \old(b))) || (((~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea && !(0bv32 == ~bvlshr64(mb, ~bvadd64(ea, ~bvneg32(eb))))) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && ~bvult64(b, \old(b))))) && __retres10 == ~bvor32(~bvand64(16777215bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))), ~bvshl32(~bvlshr64(\old(b), 24bv32), 24bv32))) || (((~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32 && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea) && ~bvult64(\old(a), \old(b)) && ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && __retres10 == \old(b)) && a == \old(b)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb)) || ((((~bvadd64(__retres10, 1bv32) == 0bv32 && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967041bv32) == 0bv32) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea) && !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32)) && ~bvadd64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), ea))) == ma)) || ((((__retres10 == ~bvor32(~bvand64(16777215bv32, ~bvlshr64(~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b)))), 1bv32)), ~bvshl32(~bvadd64(~bvlshr64(\old(b), 24bv32), 1bv32), 24bv32)) && !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32)) && !(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967041bv32) == 0bv32)) && (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) || 0bv32 == ~bvand64(33554432bv32, ma))) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32)))) || ((~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(a, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb && (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) || 0bv32 == ~bvand64(33554432bv32, ma))) && ~bvor32(~bvand64(16777215bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))), ~bvshl32(~bvlshr64(\old(a), 24bv32), 24bv32)) == __retres10)) || (((a == \old(a) && 0bv32 == \old(b)) && b == \old(b)) && __retres10 == \old(a))) || ((~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32 && !(0bv32 == ~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), ea)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))))) && a == \old(a))) || ((((!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) && (0bv32 == ~bvand64(33554432bv32, ma) || !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32))) && ~bvor32(~bvand64(16777215bv32, ~bvlshr64(~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a)))), 1bv32)), ~bvshl32(~bvadd64(~bvlshr64(\old(a), 24bv32), 1bv32), 24bv32)) == __retres10) && a == \old(a))) || (0bv32 == \old(a) && ~bvult64(\old(a), \old(b)) && ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && __retres10 == \old(b)) && a == \old(b))) && ((((((((((a == \old(a) && 0bv32 == \old(b)) && b == \old(b)) && __retres10 == \old(a)) || ((\exists addflt_~delta~0 : bv32, addflt_~b : bv32, addflt_~a : bv32 :: ~bvlshr64(~bvadd64(~bvneg32(~bvneg32(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, addflt_~b)), addflt_~delta~0))), ~bvor32(16777216bv32, ~bvand64(16777215bv32, addflt_~a))), 1bv32) == ma) && 0bv32 == ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(__retres10, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)))) || (((~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32 && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea) && ~bvult64(\old(a), \old(b)) && ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && __retres10 == \old(b)) && a == \old(b)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb)) || (~bvadd64(__retres10, 1bv32) == 0bv32 && a == \old(a))) || ((((!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) && (0bv32 == ~bvand64(33554432bv32, ma) || !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32))) && ~bvor32(~bvand64(16777215bv32, ~bvlshr64(~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a)))), 1bv32)), ~bvshl32(~bvadd64(~bvlshr64(\old(a), 24bv32), 1bv32), 24bv32)) == __retres10) && a == \old(a))) || (((!(255bv32 == ~bvlshr64(\old(a), 24bv32)) && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && ~bvult64(b, \old(b))) || (((~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea && !(0bv32 == ~bvlshr64(mb, ~bvadd64(ea, ~bvneg32(eb))))) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && ~bvult64(b, \old(b)))) || (!(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32) && ~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32)) || (0bv32 == \old(a) && ~bvult64(\old(a), \old(b)) && ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && __retres10 == \old(b)) && a == \old(b)))) && ((((((((((a == \old(a) && 0bv32 == \old(b)) && b == \old(b)) && __retres10 == \old(a)) || ((((((~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a)))) == ma && b == \old(b)) && ~bvadd64(__retres10, 1bv32) == 0bv32) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(a, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && mb == ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), ea))) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == eb)) || ((((~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(a, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && ~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && mb == ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), ea))) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == eb)) || (((((~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32) == ea && 0bv32 == ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(__retres10, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32))) && __retres10 == \old(a)) && a == \old(a)) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == eb) && ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))) == ma)) || (((!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && b == \old(b)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(a, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) || ((((b == \old(a) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(0bv32 == \old(a))) && ~bvult64(b, \old(b))) && !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32))) || ((((~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea && b == \old(a)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(0bv32 == \old(a))) && ~bvult64(b, \old(b)))) || (~bvult64(\old(a), \old(b)) && ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && __retres10 == \old(b)) && a == \old(b)))) && (((a == \old(a) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && a == \old(a))) && !~bvult64(a, \old(a))) || (((a == \old(a) && 0bv32 == \old(b)) && b == \old(b)) && __retres10 == \old(a))) || (((((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && a == \old(a))) && !~bvult64(a, \old(a))) && b == \old(a))) [2018-11-23 05:59:08,578 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_952fe706-50f9-4485-a6a0-3d8cd50f7797/bin-2019/uautomizer/witness.graphml [2018-11-23 05:59:08,578 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 05:59:08,579 INFO L168 Benchmark]: Toolchain (without parser) took 769660.90 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 179.3 MB). Free memory was 949.7 MB in the beginning and 941.3 MB in the end (delta: 8.5 MB). Peak memory consumption was 187.8 MB. Max. memory is 11.5 GB. [2018-11-23 05:59:08,580 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 05:59:08,580 INFO L168 Benchmark]: CACSL2BoogieTranslator took 235.56 ms. Allocated memory is still 1.0 GB. Free memory was 949.7 MB in the beginning and 933.6 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-23 05:59:08,580 INFO L168 Benchmark]: Boogie Procedure Inliner took 22.71 ms. Allocated memory is still 1.0 GB. Free memory is still 933.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 05:59:08,580 INFO L168 Benchmark]: Boogie Preprocessor took 24.05 ms. Allocated memory is still 1.0 GB. Free memory was 933.6 MB in the beginning and 928.3 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-11-23 05:59:08,581 INFO L168 Benchmark]: RCFGBuilder took 273.22 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 159.4 MB). Free memory was 928.3 MB in the beginning and 1.1 GB in the end (delta: -203.1 MB). Peak memory consumption was 15.2 MB. Max. memory is 11.5 GB. [2018-11-23 05:59:08,581 INFO L168 Benchmark]: TraceAbstraction took 769046.13 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 19.9 MB). Free memory was 1.1 GB in the beginning and 941.3 MB in the end (delta: 190.1 MB). Peak memory consumption was 335.8 MB. Max. memory is 11.5 GB. [2018-11-23 05:59:08,581 INFO L168 Benchmark]: Witness Printer took 54.77 ms. Allocated memory is still 1.2 GB. Free memory was 941.3 MB in the beginning and 941.3 MB in the end (delta: 2.4 kB). Peak memory consumption was 2.4 kB. Max. memory is 11.5 GB. [2018-11-23 05:59:08,583 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 235.56 ms. Allocated memory is still 1.0 GB. Free memory was 949.7 MB in the beginning and 933.6 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 22.71 ms. Allocated memory is still 1.0 GB. Free memory is still 933.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 24.05 ms. Allocated memory is still 1.0 GB. Free memory was 933.6 MB in the beginning and 928.3 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 273.22 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 159.4 MB). Free memory was 928.3 MB in the beginning and 1.1 GB in the end (delta: -203.1 MB). Peak memory consumption was 15.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 769046.13 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 19.9 MB). Free memory was 1.1 GB in the beginning and 941.3 MB in the end (delta: 190.1 MB). Peak memory consumption was 335.8 MB. Max. memory is 11.5 GB. * Witness Printer took 54.77 ms. Allocated memory is still 1.2 GB. Free memory was 941.3 MB in the beginning and 941.3 MB in the end (delta: 2.4 kB). Peak memory consumption was 2.4 kB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~b,QUANTIFIED] - GenericResult: Unfinished Backtranslation Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~delta~0,QUANTIFIED] - GenericResult: Unfinished Backtranslation Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~a,QUANTIFIED] - GenericResult: Unfinished Backtranslation Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~b,QUANTIFIED] - GenericResult: Unfinished Backtranslation Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~delta~0,QUANTIFIED] - GenericResult: Unfinished Backtranslation Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~a,QUANTIFIED] * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - PositiveResult [Line: 7]: call of __VERIFIER_error() unreachable For all program executions holds that call of __VERIFIER_error() unreachable at this location - AllSpecificationsHoldResult: All specifications hold 1 specifications checked. All of them hold - InvariantResult [Line: 25]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 18]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 83]: Loop Invariant [2018-11-23 05:59:08,586 WARN L416 cessorBacktranslator]: Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~b,QUANTIFIED] [2018-11-23 05:59:08,586 WARN L416 cessorBacktranslator]: Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~delta~0,QUANTIFIED] [2018-11-23 05:59:08,586 WARN L416 cessorBacktranslator]: Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~a,QUANTIFIED] [2018-11-23 05:59:08,590 WARN L416 cessorBacktranslator]: Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~b,QUANTIFIED] [2018-11-23 05:59:08,590 WARN L416 cessorBacktranslator]: Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~delta~0,QUANTIFIED] [2018-11-23 05:59:08,590 WARN L416 cessorBacktranslator]: Identifier is quantified, using identity as back-translation of IdentifierExpression[addflt_~a,QUANTIFIED] Derived loop invariant: (((((((((((((0bv32 == ~bvand64(33554432bv32, ma) && ~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32) && ((((!(255bv32 == ~bvlshr64(\old(a), 24bv32)) && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && ~bvult64(b, \old(b))) || (((~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea && !(0bv32 == ~bvlshr64(mb, ~bvadd64(ea, ~bvneg32(eb))))) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && ~bvult64(b, \old(b))))) && __retres10 == ~bvor32(~bvand64(16777215bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))), ~bvshl32(~bvlshr64(\old(b), 24bv32), 24bv32))) || (((~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32 && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea) && ~bvult64(\old(a), \old(b)) && ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && __retres10 == \old(b)) && a == \old(b)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb)) || ((((~bvadd64(__retres10, 1bv32) == 0bv32 && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967041bv32) == 0bv32) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea) && !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32)) && ~bvadd64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), ea))) == ma)) || ((((__retres10 == ~bvor32(~bvand64(16777215bv32, ~bvlshr64(~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b)))), 1bv32)), ~bvshl32(~bvadd64(~bvlshr64(\old(b), 24bv32), 1bv32), 24bv32)) && !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32)) && !(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967041bv32) == 0bv32)) && (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) || 0bv32 == ~bvand64(33554432bv32, ma))) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32)))) || ((~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(a, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb && (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) || 0bv32 == ~bvand64(33554432bv32, ma))) && ~bvor32(~bvand64(16777215bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))), ~bvshl32(~bvlshr64(\old(a), 24bv32), 24bv32)) == __retres10)) || (((a == \old(a) && 0bv32 == \old(b)) && b == \old(b)) && __retres10 == \old(a))) || ((~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32 && !(0bv32 == ~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), ea)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))))) && a == \old(a))) || ((((!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) && (0bv32 == ~bvand64(33554432bv32, ma) || !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32))) && ~bvor32(~bvand64(16777215bv32, ~bvlshr64(~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a)))), 1bv32)), ~bvshl32(~bvadd64(~bvlshr64(\old(a), 24bv32), 1bv32), 24bv32)) == __retres10) && a == \old(a))) || (0bv32 == \old(a) && ~bvult64(\old(a), \old(b)) && ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && __retres10 == \old(b)) && a == \old(b))) && ((((((((((a == \old(a) && 0bv32 == \old(b)) && b == \old(b)) && __retres10 == \old(a)) || ((\exists addflt_~delta~0 : bv32, addflt_~b : bv32, addflt_~a : bv32 :: ~bvlshr64(~bvadd64(~bvneg32(~bvneg32(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, addflt_~b)), addflt_~delta~0))), ~bvor32(16777216bv32, ~bvand64(16777215bv32, addflt_~a))), 1bv32) == ma) && 0bv32 == ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(__retres10, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)))) || (((~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32 && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea) && ~bvult64(\old(a), \old(b)) && ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && __retres10 == \old(b)) && a == \old(b)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb)) || (~bvadd64(__retres10, 1bv32) == 0bv32 && a == \old(a))) || ((((!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) && (0bv32 == ~bvand64(33554432bv32, ma) || !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32))) && ~bvor32(~bvand64(16777215bv32, ~bvlshr64(~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a)))), 1bv32)), ~bvshl32(~bvadd64(~bvlshr64(\old(a), 24bv32), 1bv32), 24bv32)) == __retres10) && a == \old(a))) || (((!(255bv32 == ~bvlshr64(\old(a), 24bv32)) && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && ~bvult64(b, \old(b))) || (((~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea && !(0bv32 == ~bvlshr64(mb, ~bvadd64(ea, ~bvneg32(eb))))) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && ~bvult64(b, \old(b)))) || (!(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32) && ~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32)) || (0bv32 == \old(a) && ~bvult64(\old(a), \old(b)) && ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && __retres10 == \old(b)) && a == \old(b)))) && ((((((((((a == \old(a) && 0bv32 == \old(b)) && b == \old(b)) && __retres10 == \old(a)) || ((((((~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a)))) == ma && b == \old(b)) && ~bvadd64(__retres10, 1bv32) == 0bv32) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(a, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && mb == ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), ea))) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == eb)) || ((((~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(a, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && ~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && mb == ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), ea))) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == eb)) || (((((~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32) == ea && 0bv32 == ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(__retres10, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32))) && __retres10 == \old(a)) && a == \old(a)) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == eb) && ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))) == ma)) || (((!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && b == \old(b)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(a, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) || ((((b == \old(a) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(0bv32 == \old(a))) && ~bvult64(b, \old(b))) && !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32))) || ((((~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea && b == \old(a)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(0bv32 == \old(a))) && ~bvult64(b, \old(b)))) || (~bvult64(\old(a), \old(b)) && ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && __retres10 == \old(b)) && a == \old(b)))) && (((a == \old(a) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && a == \old(a))) && !~bvult64(a, \old(a))) || (((a == \old(a) && 0bv32 == \old(b)) && b == \old(b)) && __retres10 == \old(a))) || (((((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || ((!(0bv32 == \old(b)) && !~bvult64(a, b)) && b == \old(b))) && a == \old(a))) && !~bvult64(a, \old(a))) && b == \old(a))) - InvariantResult [Line: 47]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 27]: Loop Invariant Derived loop invariant: 1 - StatisticsResult: Ultimate Automizer benchmark data CFG has 6 procedures, 56 locations, 1 error locations. SAFE Result, 768.9s OverallTime, 56 OverallIterations, 5 TraceHistogramMax, 137.1s AutomataDifference, 0.0s DeadEndRemovalTime, 540.5s HoareAnnotationTime, HoareTripleCheckerStatistics: 4124 SDtfs, 4133 SDslu, 36824 SDs, 0 SdLazy, 16072 SolverSat, 1651 SolverUnsat, 11 SolverUnknown, 0 SolverNotchecked, 65.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 6999 GetRequests, 5642 SyntacticMatches, 66 SemanticMatches, 1291 ConstructedPredicates, 0 IntricatePredicates, 1 DeprecatedPredicates, 4473 ImplicationChecksByTransitivity, 134.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=243occurred in iteration=21, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 1.2s AutomataMinimizationTime, 56 MinimizatonAttempts, 959 StatesRemovedByMinimization, 51 NontrivialMinimizations, HoareAnnotationStatistics: 0.0s HoareAnnotationTime, 20 LocationsWithAnnotation, 343 PreInvPairs, 1398 NumberOfFragments, 3353 HoareAnnotationTreeSize, 343 FomulaSimplifications, 112128650744 FormulaSimplificationTreeSizeReduction, 4.9s HoareSimplificationTime, 20 FomulaSimplificationsInter, 4212074100 FormulaSimplificationTreeSizeReductionInter, 535.6s HoareSimplificationTimeInter, RefinementEngineStatistics: TraceCheckStatistics: 0.3s SsaConstructionTime, 6.0s SatisfiabilityAnalysisTime, 82.0s InterpolantComputationTime, 4132 NumberOfCodeBlocks, 4114 NumberOfCodeBlocksAsserted, 80 NumberOfCheckSat, 6324 ConstructedInterpolants, 79 QuantifiedInterpolants, 3145278 SizeOfPredicates, 645 NumberOfNonLiveVariables, 7388 ConjunctsInSsa, 1179 ConjunctsInUnsatCore, 98 InterpolantComputations, 15 PerfectInterpolantSequences, 2884/3477 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be correct! Received shutdown request...