./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/thin000_power.opt_false-unreach-call.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_68853c4d-c738-42b3-b062-41fa6f6ad7ab/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_68853c4d-c738-42b3-b062-41fa6f6ad7ab/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_68853c4d-c738-42b3-b062-41fa6f6ad7ab/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_68853c4d-c738-42b3-b062-41fa6f6ad7ab/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/thin000_power.opt_false-unreach-call.i -s /tmp/vcloud-vcloud-master/worker/working_dir_68853c4d-c738-42b3-b062-41fa6f6ad7ab/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_68853c4d-c738-42b3-b062-41fa6f6ad7ab/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6b9587c6020262ab57ddfec61db9cd4fba3d13a7 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 03:30:35,290 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 03:30:35,292 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 03:30:35,300 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 03:30:35,301 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 03:30:35,301 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 03:30:35,302 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 03:30:35,304 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 03:30:35,305 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 03:30:35,305 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 03:30:35,306 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 03:30:35,307 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 03:30:35,307 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 03:30:35,308 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 03:30:35,309 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 03:30:35,309 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 03:30:35,310 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 03:30:35,312 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 03:30:35,313 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 03:30:35,314 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 03:30:35,315 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 03:30:35,316 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 03:30:35,317 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 03:30:35,318 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 03:30:35,318 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 03:30:35,319 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 03:30:35,320 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 03:30:35,320 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 03:30:35,321 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 03:30:35,321 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 03:30:35,322 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 03:30:35,323 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 03:30:35,323 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 03:30:35,323 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 03:30:35,324 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 03:30:35,324 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 03:30:35,324 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_68853c4d-c738-42b3-b062-41fa6f6ad7ab/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-23 03:30:35,335 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 03:30:35,335 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 03:30:35,336 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 03:30:35,336 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 03:30:35,337 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 03:30:35,337 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 03:30:35,337 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 03:30:35,337 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 03:30:35,337 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 03:30:35,337 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 03:30:35,337 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 03:30:35,338 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 03:30:35,338 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 03:30:35,338 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 03:30:35,338 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 03:30:35,338 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 03:30:35,338 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 03:30:35,338 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 03:30:35,338 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 03:30:35,339 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 03:30:35,339 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 03:30:35,339 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 03:30:35,339 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 03:30:35,339 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 03:30:35,339 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 03:30:35,339 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 03:30:35,339 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 03:30:35,340 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 03:30:35,340 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 03:30:35,340 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 03:30:35,340 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_68853c4d-c738-42b3-b062-41fa6f6ad7ab/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6b9587c6020262ab57ddfec61db9cd4fba3d13a7 [2018-11-23 03:30:35,363 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 03:30:35,373 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 03:30:35,375 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 03:30:35,377 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 03:30:35,377 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 03:30:35,378 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_68853c4d-c738-42b3-b062-41fa6f6ad7ab/bin-2019/uautomizer/../../sv-benchmarks/c/pthread-wmm/thin000_power.opt_false-unreach-call.i [2018-11-23 03:30:35,414 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_68853c4d-c738-42b3-b062-41fa6f6ad7ab/bin-2019/uautomizer/data/63e7493f3/e8c83d3e011e41a29bc6090baa7b71a8/FLAG6931c6fec [2018-11-23 03:30:35,801 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 03:30:35,802 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_68853c4d-c738-42b3-b062-41fa6f6ad7ab/sv-benchmarks/c/pthread-wmm/thin000_power.opt_false-unreach-call.i [2018-11-23 03:30:35,815 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_68853c4d-c738-42b3-b062-41fa6f6ad7ab/bin-2019/uautomizer/data/63e7493f3/e8c83d3e011e41a29bc6090baa7b71a8/FLAG6931c6fec [2018-11-23 03:30:35,826 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_68853c4d-c738-42b3-b062-41fa6f6ad7ab/bin-2019/uautomizer/data/63e7493f3/e8c83d3e011e41a29bc6090baa7b71a8 [2018-11-23 03:30:35,829 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 03:30:35,830 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 03:30:35,830 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 03:30:35,830 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 03:30:35,833 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 03:30:35,834 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 03:30:35" (1/1) ... [2018-11-23 03:30:35,836 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7befe0c1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:30:35, skipping insertion in model container [2018-11-23 03:30:35,836 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 03:30:35" (1/1) ... [2018-11-23 03:30:35,843 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 03:30:35,877 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 03:30:36,119 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 03:30:36,131 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 03:30:36,221 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 03:30:36,264 INFO L195 MainTranslator]: Completed translation [2018-11-23 03:30:36,265 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:30:36 WrapperNode [2018-11-23 03:30:36,265 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 03:30:36,266 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 03:30:36,266 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 03:30:36,266 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 03:30:36,273 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:30:36" (1/1) ... [2018-11-23 03:30:36,284 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:30:36" (1/1) ... [2018-11-23 03:30:36,300 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 03:30:36,300 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 03:30:36,300 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 03:30:36,300 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 03:30:36,307 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:30:36" (1/1) ... [2018-11-23 03:30:36,307 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:30:36" (1/1) ... [2018-11-23 03:30:36,309 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:30:36" (1/1) ... [2018-11-23 03:30:36,310 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:30:36" (1/1) ... [2018-11-23 03:30:36,316 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:30:36" (1/1) ... [2018-11-23 03:30:36,318 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:30:36" (1/1) ... [2018-11-23 03:30:36,320 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:30:36" (1/1) ... [2018-11-23 03:30:36,323 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 03:30:36,323 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 03:30:36,323 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 03:30:36,323 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 03:30:36,324 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:30:36" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_68853c4d-c738-42b3-b062-41fa6f6ad7ab/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 03:30:36,368 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 03:30:36,368 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-23 03:30:36,369 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-23 03:30:36,369 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2018-11-23 03:30:36,369 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 03:30:36,369 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2018-11-23 03:30:36,369 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2018-11-23 03:30:36,370 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2018-11-23 03:30:36,370 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2018-11-23 03:30:36,370 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-11-23 03:30:36,370 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2018-11-23 03:30:36,370 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 03:30:36,370 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 03:30:36,372 WARN L198 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2018-11-23 03:30:36,910 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 03:30:36,910 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-11-23 03:30:36,910 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 03:30:36 BoogieIcfgContainer [2018-11-23 03:30:36,911 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 03:30:36,911 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 03:30:36,911 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 03:30:36,913 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 03:30:36,913 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 03:30:35" (1/3) ... [2018-11-23 03:30:36,914 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2fd3af23 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 03:30:36, skipping insertion in model container [2018-11-23 03:30:36,914 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:30:36" (2/3) ... [2018-11-23 03:30:36,914 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2fd3af23 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 03:30:36, skipping insertion in model container [2018-11-23 03:30:36,914 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 03:30:36" (3/3) ... [2018-11-23 03:30:36,917 INFO L112 eAbstractionObserver]: Analyzing ICFG thin000_power.opt_false-unreach-call.i [2018-11-23 03:30:36,944 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,944 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,944 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,945 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,945 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,945 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,945 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,945 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,945 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,946 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,946 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,946 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~mem3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,946 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,946 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,946 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,946 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~mem3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,946 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,947 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,947 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,947 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,947 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,947 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,947 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,948 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,948 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,948 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,948 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,948 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,948 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,948 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,949 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,949 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,949 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,949 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,949 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet10.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,949 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet10.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,949 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,950 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,950 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet10.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,950 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet10.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,951 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet12.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,951 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet11.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,951 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet11.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,951 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,951 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,952 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet14.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,952 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet12.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,952 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet14.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,952 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet12.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,952 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet11.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,952 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet14.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,952 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,952 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet12.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,952 WARN L317 ript$VariableManager]: TermVariabe Thread0_P1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,952 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet11.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,952 WARN L317 ript$VariableManager]: TermVariabe Thread0_P1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,953 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet14.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,953 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,953 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,953 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,953 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,953 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,953 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,953 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,953 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,953 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,953 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,954 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,954 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,954 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,954 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,954 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,954 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,954 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,954 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,955 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,955 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,955 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,955 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,955 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,955 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,955 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,955 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,955 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,956 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,956 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,956 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,956 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,956 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,956 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,956 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,957 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,957 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,957 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,957 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,957 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,957 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,957 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,957 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,957 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,957 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,958 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,958 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,958 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,964 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,965 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,965 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,965 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,965 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,965 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,965 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,966 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,966 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,966 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,966 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,966 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,966 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,966 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,966 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,967 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,967 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,967 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,967 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,967 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,967 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,967 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,968 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,968 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,968 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,968 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,968 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,968 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,968 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,968 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,968 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,969 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,969 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,969 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,969 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,969 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,969 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,969 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,969 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,969 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,970 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,970 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,970 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,970 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,970 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,970 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,970 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,970 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,971 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,971 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,971 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,971 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,971 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,971 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,972 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,972 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,972 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,972 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,972 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,972 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,972 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,973 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,973 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,973 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,973 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,973 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,973 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,973 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,973 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,974 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,974 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,974 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,974 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,974 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,974 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,974 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,975 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,975 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,975 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,975 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,975 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,975 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,975 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,975 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,976 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,976 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,976 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,976 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,976 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,976 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,976 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,976 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,976 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,977 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,977 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,977 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,977 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,977 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,977 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,977 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,977 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,978 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,978 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,978 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,978 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,978 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,978 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,978 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,978 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,979 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,979 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,979 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,979 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,979 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,979 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,979 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,980 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,980 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,980 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,980 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,980 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,980 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,980 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,980 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,981 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,981 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,981 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,981 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,981 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,981 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,981 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,981 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,982 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,982 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,982 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,982 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,982 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,982 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,982 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,982 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,983 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,983 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,983 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,983 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,983 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,983 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,983 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,983 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,983 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet67.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,984 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet67.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,984 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,984 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,984 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet67.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:36,984 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet67.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:30:37,000 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2018-11-23 03:30:37,001 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 03:30:37,006 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2018-11-23 03:30:37,015 INFO L257 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2018-11-23 03:30:37,032 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 03:30:37,033 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 03:30:37,033 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 03:30:37,033 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 03:30:37,033 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 03:30:37,033 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 03:30:37,033 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 03:30:37,033 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 03:30:37,033 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 03:30:37,042 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 200places, 259 transitions [2018-11-23 03:30:40,848 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 65314 states. [2018-11-23 03:30:40,850 INFO L276 IsEmpty]: Start isEmpty. Operand 65314 states. [2018-11-23 03:30:40,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-23 03:30:40,856 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:30:40,857 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:30:40,858 INFO L423 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:30:40,862 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:30:40,862 INFO L82 PathProgramCache]: Analyzing trace with hash -1016272846, now seen corresponding path program 1 times [2018-11-23 03:30:40,864 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:30:40,864 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:30:40,899 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:30:40,899 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:30:40,899 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:30:40,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:30:41,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:30:41,016 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:30:41,017 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:30:41,019 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:30:41,026 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:30:41,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:30:41,028 INFO L87 Difference]: Start difference. First operand 65314 states. Second operand 4 states. [2018-11-23 03:30:41,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:30:41,888 INFO L93 Difference]: Finished difference Result 113402 states and 445073 transitions. [2018-11-23 03:30:41,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 03:30:41,890 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 49 [2018-11-23 03:30:41,890 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:30:42,202 INFO L225 Difference]: With dead ends: 113402 [2018-11-23 03:30:42,202 INFO L226 Difference]: Without dead ends: 86242 [2018-11-23 03:30:42,203 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:30:42,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86242 states. [2018-11-23 03:30:43,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86242 to 53058. [2018-11-23 03:30:43,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53058 states. [2018-11-23 03:30:43,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53058 states to 53058 states and 208767 transitions. [2018-11-23 03:30:43,872 INFO L78 Accepts]: Start accepts. Automaton has 53058 states and 208767 transitions. Word has length 49 [2018-11-23 03:30:43,872 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:30:43,873 INFO L480 AbstractCegarLoop]: Abstraction has 53058 states and 208767 transitions. [2018-11-23 03:30:43,873 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:30:43,873 INFO L276 IsEmpty]: Start isEmpty. Operand 53058 states and 208767 transitions. [2018-11-23 03:30:43,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-11-23 03:30:43,880 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:30:43,880 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:30:43,881 INFO L423 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:30:43,881 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:30:43,881 INFO L82 PathProgramCache]: Analyzing trace with hash -267205330, now seen corresponding path program 1 times [2018-11-23 03:30:43,881 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:30:43,881 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:30:43,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:30:43,884 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:30:43,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:30:43,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:30:43,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:30:43,936 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:30:43,936 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 03:30:43,937 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 03:30:43,937 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 03:30:43,937 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 03:30:43,938 INFO L87 Difference]: Start difference. First operand 53058 states and 208767 transitions. Second operand 3 states. [2018-11-23 03:30:44,716 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:30:44,716 INFO L93 Difference]: Finished difference Result 53058 states and 208358 transitions. [2018-11-23 03:30:44,717 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 03:30:44,717 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2018-11-23 03:30:44,717 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:30:44,861 INFO L225 Difference]: With dead ends: 53058 [2018-11-23 03:30:44,861 INFO L226 Difference]: Without dead ends: 53058 [2018-11-23 03:30:44,862 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 03:30:45,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53058 states. [2018-11-23 03:30:45,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53058 to 53058. [2018-11-23 03:30:45,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53058 states. [2018-11-23 03:30:45,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53058 states to 53058 states and 208358 transitions. [2018-11-23 03:30:45,758 INFO L78 Accepts]: Start accepts. Automaton has 53058 states and 208358 transitions. Word has length 61 [2018-11-23 03:30:45,759 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:30:45,759 INFO L480 AbstractCegarLoop]: Abstraction has 53058 states and 208358 transitions. [2018-11-23 03:30:45,759 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 03:30:45,759 INFO L276 IsEmpty]: Start isEmpty. Operand 53058 states and 208358 transitions. [2018-11-23 03:30:45,763 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-11-23 03:30:45,763 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:30:45,764 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:30:45,764 INFO L423 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:30:45,764 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:30:45,764 INFO L82 PathProgramCache]: Analyzing trace with hash 1475605005, now seen corresponding path program 1 times [2018-11-23 03:30:45,764 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:30:45,764 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:30:45,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:30:45,767 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:30:45,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:30:45,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:30:45,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:30:45,829 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:30:45,829 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:30:45,829 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:30:45,829 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:30:45,830 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:30:45,830 INFO L87 Difference]: Start difference. First operand 53058 states and 208358 transitions. Second operand 5 states. [2018-11-23 03:30:46,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:30:46,850 INFO L93 Difference]: Finished difference Result 120766 states and 451890 transitions. [2018-11-23 03:30:46,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 03:30:46,850 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 61 [2018-11-23 03:30:46,851 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:30:47,153 INFO L225 Difference]: With dead ends: 120766 [2018-11-23 03:30:47,153 INFO L226 Difference]: Without dead ends: 119910 [2018-11-23 03:30:47,153 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:30:47,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119910 states. [2018-11-23 03:30:48,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119910 to 81756. [2018-11-23 03:30:48,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81756 states. [2018-11-23 03:30:49,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81756 states to 81756 states and 306102 transitions. [2018-11-23 03:30:49,021 INFO L78 Accepts]: Start accepts. Automaton has 81756 states and 306102 transitions. Word has length 61 [2018-11-23 03:30:49,022 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:30:49,022 INFO L480 AbstractCegarLoop]: Abstraction has 81756 states and 306102 transitions. [2018-11-23 03:30:49,023 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:30:49,023 INFO L276 IsEmpty]: Start isEmpty. Operand 81756 states and 306102 transitions. [2018-11-23 03:30:49,028 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-11-23 03:30:49,028 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:30:49,029 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:30:49,029 INFO L423 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:30:49,029 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:30:49,029 INFO L82 PathProgramCache]: Analyzing trace with hash 1874201971, now seen corresponding path program 1 times [2018-11-23 03:30:49,029 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:30:49,029 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:30:49,031 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:30:49,032 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:30:49,032 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:30:49,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:30:49,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:30:49,109 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:30:49,109 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:30:49,109 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:30:49,109 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:30:49,110 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:30:49,110 INFO L87 Difference]: Start difference. First operand 81756 states and 306102 transitions. Second operand 6 states. [2018-11-23 03:30:50,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:30:50,108 INFO L93 Difference]: Finished difference Result 194640 states and 716858 transitions. [2018-11-23 03:30:50,108 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 03:30:50,109 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 62 [2018-11-23 03:30:50,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:30:53,148 INFO L225 Difference]: With dead ends: 194640 [2018-11-23 03:30:53,148 INFO L226 Difference]: Without dead ends: 193624 [2018-11-23 03:30:53,149 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=42, Invalid=90, Unknown=0, NotChecked=0, Total=132 [2018-11-23 03:30:53,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193624 states. [2018-11-23 03:30:55,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193624 to 91024. [2018-11-23 03:30:55,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91024 states. [2018-11-23 03:30:55,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91024 states to 91024 states and 338411 transitions. [2018-11-23 03:30:55,380 INFO L78 Accepts]: Start accepts. Automaton has 91024 states and 338411 transitions. Word has length 62 [2018-11-23 03:30:55,380 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:30:55,380 INFO L480 AbstractCegarLoop]: Abstraction has 91024 states and 338411 transitions. [2018-11-23 03:30:55,380 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:30:55,380 INFO L276 IsEmpty]: Start isEmpty. Operand 91024 states and 338411 transitions. [2018-11-23 03:30:55,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-23 03:30:55,389 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:30:55,390 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:30:55,390 INFO L423 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:30:55,391 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:30:55,391 INFO L82 PathProgramCache]: Analyzing trace with hash -1781281892, now seen corresponding path program 1 times [2018-11-23 03:30:55,391 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:30:55,391 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:30:55,393 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:30:55,393 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:30:55,393 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:30:55,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:30:55,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:30:55,432 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:30:55,432 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 03:30:55,432 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 03:30:55,432 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 03:30:55,432 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 03:30:55,432 INFO L87 Difference]: Start difference. First operand 91024 states and 338411 transitions. Second operand 3 states. [2018-11-23 03:30:55,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:30:55,893 INFO L93 Difference]: Finished difference Result 120751 states and 443372 transitions. [2018-11-23 03:30:55,893 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 03:30:55,894 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 64 [2018-11-23 03:30:55,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:30:56,125 INFO L225 Difference]: With dead ends: 120751 [2018-11-23 03:30:56,126 INFO L226 Difference]: Without dead ends: 120751 [2018-11-23 03:30:56,126 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 03:30:56,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120751 states. [2018-11-23 03:30:58,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120751 to 101531. [2018-11-23 03:30:58,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101531 states. [2018-11-23 03:30:58,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101531 states to 101531 states and 373619 transitions. [2018-11-23 03:30:58,430 INFO L78 Accepts]: Start accepts. Automaton has 101531 states and 373619 transitions. Word has length 64 [2018-11-23 03:30:58,431 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:30:58,431 INFO L480 AbstractCegarLoop]: Abstraction has 101531 states and 373619 transitions. [2018-11-23 03:30:58,431 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 03:30:58,431 INFO L276 IsEmpty]: Start isEmpty. Operand 101531 states and 373619 transitions. [2018-11-23 03:30:58,445 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-23 03:30:58,445 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:30:58,445 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:30:58,445 INFO L423 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:30:58,446 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:30:58,446 INFO L82 PathProgramCache]: Analyzing trace with hash -571649263, now seen corresponding path program 1 times [2018-11-23 03:30:58,446 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:30:58,446 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:30:58,448 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:30:58,448 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:30:58,448 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:30:58,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:30:58,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:30:58,566 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:30:58,566 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-23 03:30:58,567 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-23 03:30:58,567 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-23 03:30:58,567 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2018-11-23 03:30:58,567 INFO L87 Difference]: Start difference. First operand 101531 states and 373619 transitions. Second operand 10 states. [2018-11-23 03:31:00,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:00,189 INFO L93 Difference]: Finished difference Result 162636 states and 583282 transitions. [2018-11-23 03:31:00,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-11-23 03:31:00,189 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 68 [2018-11-23 03:31:00,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:00,512 INFO L225 Difference]: With dead ends: 162636 [2018-11-23 03:31:00,513 INFO L226 Difference]: Without dead ends: 161372 [2018-11-23 03:31:00,513 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 364 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=343, Invalid=1063, Unknown=0, NotChecked=0, Total=1406 [2018-11-23 03:31:01,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161372 states. [2018-11-23 03:31:02,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161372 to 108947. [2018-11-23 03:31:02,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108947 states. [2018-11-23 03:31:03,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108947 states to 108947 states and 398508 transitions. [2018-11-23 03:31:03,138 INFO L78 Accepts]: Start accepts. Automaton has 108947 states and 398508 transitions. Word has length 68 [2018-11-23 03:31:03,139 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:03,139 INFO L480 AbstractCegarLoop]: Abstraction has 108947 states and 398508 transitions. [2018-11-23 03:31:03,139 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-23 03:31:03,139 INFO L276 IsEmpty]: Start isEmpty. Operand 108947 states and 398508 transitions. [2018-11-23 03:31:03,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-23 03:31:03,161 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:03,161 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:03,161 INFO L423 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:03,161 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:03,161 INFO L82 PathProgramCache]: Analyzing trace with hash 540269240, now seen corresponding path program 1 times [2018-11-23 03:31:03,161 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:03,162 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:03,164 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:03,164 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:03,164 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:03,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:03,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:03,249 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:03,249 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:31:03,249 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:31:03,249 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:31:03,249 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:31:03,249 INFO L87 Difference]: Start difference. First operand 108947 states and 398508 transitions. Second operand 6 states. [2018-11-23 03:31:04,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:04,140 INFO L93 Difference]: Finished difference Result 136498 states and 489586 transitions. [2018-11-23 03:31:04,141 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 03:31:04,141 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 70 [2018-11-23 03:31:04,141 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:04,398 INFO L225 Difference]: With dead ends: 136498 [2018-11-23 03:31:04,398 INFO L226 Difference]: Without dead ends: 135590 [2018-11-23 03:31:04,398 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:31:04,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135590 states. [2018-11-23 03:31:06,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135590 to 131562. [2018-11-23 03:31:06,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131562 states. [2018-11-23 03:31:06,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131562 states to 131562 states and 473807 transitions. [2018-11-23 03:31:06,997 INFO L78 Accepts]: Start accepts. Automaton has 131562 states and 473807 transitions. Word has length 70 [2018-11-23 03:31:06,997 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:06,997 INFO L480 AbstractCegarLoop]: Abstraction has 131562 states and 473807 transitions. [2018-11-23 03:31:06,997 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:31:06,997 INFO L276 IsEmpty]: Start isEmpty. Operand 131562 states and 473807 transitions. [2018-11-23 03:31:07,023 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-23 03:31:07,023 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:07,023 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:07,023 INFO L423 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:07,023 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:07,023 INFO L82 PathProgramCache]: Analyzing trace with hash 246866233, now seen corresponding path program 1 times [2018-11-23 03:31:07,023 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:07,023 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:07,025 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:07,025 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:07,025 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:07,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:07,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:07,108 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:07,109 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 03:31:07,109 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 03:31:07,109 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 03:31:07,109 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:31:07,109 INFO L87 Difference]: Start difference. First operand 131562 states and 473807 transitions. Second operand 7 states. [2018-11-23 03:31:08,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:08,404 INFO L93 Difference]: Finished difference Result 190988 states and 665826 transitions. [2018-11-23 03:31:08,404 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 03:31:08,404 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 70 [2018-11-23 03:31:08,405 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:08,794 INFO L225 Difference]: With dead ends: 190988 [2018-11-23 03:31:08,794 INFO L226 Difference]: Without dead ends: 190988 [2018-11-23 03:31:08,794 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=74, Unknown=0, NotChecked=0, Total=110 [2018-11-23 03:31:09,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 190988 states. [2018-11-23 03:31:11,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 190988 to 162964. [2018-11-23 03:31:11,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162964 states. [2018-11-23 03:31:12,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162964 states to 162964 states and 575510 transitions. [2018-11-23 03:31:12,210 INFO L78 Accepts]: Start accepts. Automaton has 162964 states and 575510 transitions. Word has length 70 [2018-11-23 03:31:12,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:12,210 INFO L480 AbstractCegarLoop]: Abstraction has 162964 states and 575510 transitions. [2018-11-23 03:31:12,210 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 03:31:12,210 INFO L276 IsEmpty]: Start isEmpty. Operand 162964 states and 575510 transitions. [2018-11-23 03:31:12,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-23 03:31:12,239 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:12,239 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:12,239 INFO L423 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:12,239 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:12,239 INFO L82 PathProgramCache]: Analyzing trace with hash -1560588230, now seen corresponding path program 1 times [2018-11-23 03:31:12,240 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:12,240 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:12,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:12,241 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:12,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:12,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:12,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:12,306 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:12,306 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:31:12,306 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:31:12,306 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:31:12,307 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:31:12,307 INFO L87 Difference]: Start difference. First operand 162964 states and 575510 transitions. Second operand 4 states. [2018-11-23 03:31:12,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:12,414 INFO L93 Difference]: Finished difference Result 31092 states and 99229 transitions. [2018-11-23 03:31:12,414 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 03:31:12,415 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 70 [2018-11-23 03:31:12,415 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:12,459 INFO L225 Difference]: With dead ends: 31092 [2018-11-23 03:31:12,459 INFO L226 Difference]: Without dead ends: 27988 [2018-11-23 03:31:12,459 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:31:12,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27988 states. [2018-11-23 03:31:12,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27988 to 27932. [2018-11-23 03:31:12,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27932 states. [2018-11-23 03:31:12,789 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27932 states to 27932 states and 89022 transitions. [2018-11-23 03:31:12,789 INFO L78 Accepts]: Start accepts. Automaton has 27932 states and 89022 transitions. Word has length 70 [2018-11-23 03:31:12,789 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:12,789 INFO L480 AbstractCegarLoop]: Abstraction has 27932 states and 89022 transitions. [2018-11-23 03:31:12,790 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:31:12,790 INFO L276 IsEmpty]: Start isEmpty. Operand 27932 states and 89022 transitions. [2018-11-23 03:31:12,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-11-23 03:31:12,795 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:12,795 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:12,795 INFO L423 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:12,795 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:12,795 INFO L82 PathProgramCache]: Analyzing trace with hash 1407972401, now seen corresponding path program 1 times [2018-11-23 03:31:12,796 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:12,796 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:12,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:12,797 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:12,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:12,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:12,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:12,852 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:12,852 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:31:12,853 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:31:12,853 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:31:12,853 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:31:12,853 INFO L87 Difference]: Start difference. First operand 27932 states and 89022 transitions. Second operand 4 states. [2018-11-23 03:31:13,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:13,066 INFO L93 Difference]: Finished difference Result 30580 states and 97292 transitions. [2018-11-23 03:31:13,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 03:31:13,067 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 76 [2018-11-23 03:31:13,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:13,111 INFO L225 Difference]: With dead ends: 30580 [2018-11-23 03:31:13,111 INFO L226 Difference]: Without dead ends: 30580 [2018-11-23 03:31:13,111 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:31:13,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30580 states. [2018-11-23 03:31:13,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30580 to 29760. [2018-11-23 03:31:13,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29760 states. [2018-11-23 03:31:13,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29760 states to 29760 states and 94685 transitions. [2018-11-23 03:31:13,478 INFO L78 Accepts]: Start accepts. Automaton has 29760 states and 94685 transitions. Word has length 76 [2018-11-23 03:31:13,478 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:13,478 INFO L480 AbstractCegarLoop]: Abstraction has 29760 states and 94685 transitions. [2018-11-23 03:31:13,478 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:31:13,478 INFO L276 IsEmpty]: Start isEmpty. Operand 29760 states and 94685 transitions. [2018-11-23 03:31:13,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-11-23 03:31:13,483 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:13,483 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:13,483 INFO L423 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:13,483 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:13,483 INFO L82 PathProgramCache]: Analyzing trace with hash -1144184560, now seen corresponding path program 1 times [2018-11-23 03:31:13,483 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:13,483 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:13,484 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:13,485 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:13,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:13,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:13,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:13,594 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:13,594 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 03:31:13,595 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 03:31:13,595 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 03:31:13,595 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:31:13,595 INFO L87 Difference]: Start difference. First operand 29760 states and 94685 transitions. Second operand 7 states. [2018-11-23 03:31:14,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:14,087 INFO L93 Difference]: Finished difference Result 51085 states and 161924 transitions. [2018-11-23 03:31:14,088 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-23 03:31:14,088 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 76 [2018-11-23 03:31:14,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:14,165 INFO L225 Difference]: With dead ends: 51085 [2018-11-23 03:31:14,165 INFO L226 Difference]: Without dead ends: 51014 [2018-11-23 03:31:14,165 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2018-11-23 03:31:14,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51014 states. [2018-11-23 03:31:14,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51014 to 32286. [2018-11-23 03:31:14,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32286 states. [2018-11-23 03:31:14,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32286 states to 32286 states and 102215 transitions. [2018-11-23 03:31:14,692 INFO L78 Accepts]: Start accepts. Automaton has 32286 states and 102215 transitions. Word has length 76 [2018-11-23 03:31:14,692 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:14,692 INFO L480 AbstractCegarLoop]: Abstraction has 32286 states and 102215 transitions. [2018-11-23 03:31:14,692 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 03:31:14,693 INFO L276 IsEmpty]: Start isEmpty. Operand 32286 states and 102215 transitions. [2018-11-23 03:31:14,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-11-23 03:31:14,701 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:14,701 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:14,701 INFO L423 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:14,701 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:14,701 INFO L82 PathProgramCache]: Analyzing trace with hash 2040421375, now seen corresponding path program 1 times [2018-11-23 03:31:14,702 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:14,702 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:14,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:14,703 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:14,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:14,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:14,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:14,732 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:14,732 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 03:31:14,732 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 03:31:14,733 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 03:31:14,733 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 03:31:14,733 INFO L87 Difference]: Start difference. First operand 32286 states and 102215 transitions. Second operand 3 states. [2018-11-23 03:31:14,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:14,963 INFO L93 Difference]: Finished difference Result 33202 states and 104622 transitions. [2018-11-23 03:31:14,964 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 03:31:14,964 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 82 [2018-11-23 03:31:14,964 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:15,015 INFO L225 Difference]: With dead ends: 33202 [2018-11-23 03:31:15,016 INFO L226 Difference]: Without dead ends: 33202 [2018-11-23 03:31:15,016 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 03:31:15,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33202 states. [2018-11-23 03:31:15,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33202 to 32869. [2018-11-23 03:31:15,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32869 states. [2018-11-23 03:31:15,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32869 states to 32869 states and 103706 transitions. [2018-11-23 03:31:15,388 INFO L78 Accepts]: Start accepts. Automaton has 32869 states and 103706 transitions. Word has length 82 [2018-11-23 03:31:15,388 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:15,388 INFO L480 AbstractCegarLoop]: Abstraction has 32869 states and 103706 transitions. [2018-11-23 03:31:15,388 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 03:31:15,389 INFO L276 IsEmpty]: Start isEmpty. Operand 32869 states and 103706 transitions. [2018-11-23 03:31:15,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-11-23 03:31:15,397 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:15,397 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:15,397 INFO L423 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:15,397 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:15,397 INFO L82 PathProgramCache]: Analyzing trace with hash 691673262, now seen corresponding path program 1 times [2018-11-23 03:31:15,397 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:15,397 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:15,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:15,399 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:15,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:15,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:15,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:15,448 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:15,448 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:31:15,448 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:31:15,448 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:31:15,448 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:31:15,449 INFO L87 Difference]: Start difference. First operand 32869 states and 103706 transitions. Second operand 4 states. [2018-11-23 03:31:15,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:15,737 INFO L93 Difference]: Finished difference Result 40300 states and 125281 transitions. [2018-11-23 03:31:15,737 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 03:31:15,738 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 82 [2018-11-23 03:31:15,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:15,782 INFO L225 Difference]: With dead ends: 40300 [2018-11-23 03:31:15,783 INFO L226 Difference]: Without dead ends: 40300 [2018-11-23 03:31:15,783 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:31:15,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40300 states. [2018-11-23 03:31:16,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40300 to 36355. [2018-11-23 03:31:16,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36355 states. [2018-11-23 03:31:16,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36355 states to 36355 states and 113635 transitions. [2018-11-23 03:31:16,175 INFO L78 Accepts]: Start accepts. Automaton has 36355 states and 113635 transitions. Word has length 82 [2018-11-23 03:31:16,176 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:16,176 INFO L480 AbstractCegarLoop]: Abstraction has 36355 states and 113635 transitions. [2018-11-23 03:31:16,176 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:31:16,176 INFO L276 IsEmpty]: Start isEmpty. Operand 36355 states and 113635 transitions. [2018-11-23 03:31:16,187 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-23 03:31:16,187 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:16,187 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:16,187 INFO L423 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:16,187 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:16,188 INFO L82 PathProgramCache]: Analyzing trace with hash 1307367553, now seen corresponding path program 1 times [2018-11-23 03:31:16,188 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:16,188 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:16,188 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:16,189 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:16,189 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:16,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:16,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:16,250 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:16,250 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:31:16,250 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:31:16,251 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:31:16,251 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:31:16,251 INFO L87 Difference]: Start difference. First operand 36355 states and 113635 transitions. Second operand 6 states. [2018-11-23 03:31:17,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:17,022 INFO L93 Difference]: Finished difference Result 45905 states and 141213 transitions. [2018-11-23 03:31:17,023 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:31:17,023 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 84 [2018-11-23 03:31:17,023 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:17,074 INFO L225 Difference]: With dead ends: 45905 [2018-11-23 03:31:17,074 INFO L226 Difference]: Without dead ends: 45874 [2018-11-23 03:31:17,074 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:31:17,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45874 states. [2018-11-23 03:31:17,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45874 to 39677. [2018-11-23 03:31:17,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39677 states. [2018-11-23 03:31:17,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39677 states to 39677 states and 123151 transitions. [2018-11-23 03:31:17,502 INFO L78 Accepts]: Start accepts. Automaton has 39677 states and 123151 transitions. Word has length 84 [2018-11-23 03:31:17,502 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:17,502 INFO L480 AbstractCegarLoop]: Abstraction has 39677 states and 123151 transitions. [2018-11-23 03:31:17,502 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:31:17,502 INFO L276 IsEmpty]: Start isEmpty. Operand 39677 states and 123151 transitions. [2018-11-23 03:31:17,515 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-23 03:31:17,515 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:17,515 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:17,515 INFO L423 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:17,515 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:17,515 INFO L82 PathProgramCache]: Analyzing trace with hash -2025985726, now seen corresponding path program 1 times [2018-11-23 03:31:17,516 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:17,516 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:17,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:17,517 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:17,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:17,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:17,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:17,604 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:17,604 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:31:17,604 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:31:17,604 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:31:17,604 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:31:17,605 INFO L87 Difference]: Start difference. First operand 39677 states and 123151 transitions. Second operand 6 states. [2018-11-23 03:31:17,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:17,979 INFO L93 Difference]: Finished difference Result 43621 states and 132259 transitions. [2018-11-23 03:31:17,979 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 03:31:17,979 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 84 [2018-11-23 03:31:17,979 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:18,121 INFO L225 Difference]: With dead ends: 43621 [2018-11-23 03:31:18,121 INFO L226 Difference]: Without dead ends: 43621 [2018-11-23 03:31:18,121 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-11-23 03:31:18,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43621 states. [2018-11-23 03:31:18,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43621 to 40234. [2018-11-23 03:31:18,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40234 states. [2018-11-23 03:31:18,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40234 states to 40234 states and 123358 transitions. [2018-11-23 03:31:18,516 INFO L78 Accepts]: Start accepts. Automaton has 40234 states and 123358 transitions. Word has length 84 [2018-11-23 03:31:18,516 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:18,516 INFO L480 AbstractCegarLoop]: Abstraction has 40234 states and 123358 transitions. [2018-11-23 03:31:18,516 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:31:18,516 INFO L276 IsEmpty]: Start isEmpty. Operand 40234 states and 123358 transitions. [2018-11-23 03:31:18,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-23 03:31:18,528 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:18,528 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:18,528 INFO L423 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:18,528 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:18,528 INFO L82 PathProgramCache]: Analyzing trace with hash -781221245, now seen corresponding path program 1 times [2018-11-23 03:31:18,528 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:18,529 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:18,530 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:18,530 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:18,530 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:18,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:18,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:18,592 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:18,592 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:31:18,592 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:31:18,592 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:31:18,592 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:31:18,592 INFO L87 Difference]: Start difference. First operand 40234 states and 123358 transitions. Second operand 5 states. [2018-11-23 03:31:18,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:18,920 INFO L93 Difference]: Finished difference Result 48057 states and 145245 transitions. [2018-11-23 03:31:18,920 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:31:18,920 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 84 [2018-11-23 03:31:18,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:18,972 INFO L225 Difference]: With dead ends: 48057 [2018-11-23 03:31:18,972 INFO L226 Difference]: Without dead ends: 48057 [2018-11-23 03:31:18,973 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:31:19,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48057 states. [2018-11-23 03:31:19,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48057 to 43901. [2018-11-23 03:31:19,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43901 states. [2018-11-23 03:31:19,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43901 states to 43901 states and 132803 transitions. [2018-11-23 03:31:19,431 INFO L78 Accepts]: Start accepts. Automaton has 43901 states and 132803 transitions. Word has length 84 [2018-11-23 03:31:19,432 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:19,432 INFO L480 AbstractCegarLoop]: Abstraction has 43901 states and 132803 transitions. [2018-11-23 03:31:19,432 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:31:19,432 INFO L276 IsEmpty]: Start isEmpty. Operand 43901 states and 132803 transitions. [2018-11-23 03:31:19,443 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-23 03:31:19,443 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:19,443 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:19,443 INFO L423 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:19,443 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:19,443 INFO L82 PathProgramCache]: Analyzing trace with hash -1778293598, now seen corresponding path program 1 times [2018-11-23 03:31:19,443 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:19,444 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:19,444 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:19,444 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:19,444 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:19,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:19,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:19,502 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:19,502 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:31:19,502 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:31:19,502 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:31:19,502 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:31:19,503 INFO L87 Difference]: Start difference. First operand 43901 states and 132803 transitions. Second operand 5 states. [2018-11-23 03:31:19,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:19,971 INFO L93 Difference]: Finished difference Result 60790 states and 183246 transitions. [2018-11-23 03:31:19,971 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 03:31:19,971 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 84 [2018-11-23 03:31:19,971 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:20,042 INFO L225 Difference]: With dead ends: 60790 [2018-11-23 03:31:20,042 INFO L226 Difference]: Without dead ends: 60790 [2018-11-23 03:31:20,042 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:31:20,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60790 states. [2018-11-23 03:31:20,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60790 to 47649. [2018-11-23 03:31:20,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47649 states. [2018-11-23 03:31:20,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47649 states to 47649 states and 143369 transitions. [2018-11-23 03:31:20,589 INFO L78 Accepts]: Start accepts. Automaton has 47649 states and 143369 transitions. Word has length 84 [2018-11-23 03:31:20,589 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:20,589 INFO L480 AbstractCegarLoop]: Abstraction has 47649 states and 143369 transitions. [2018-11-23 03:31:20,589 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:31:20,589 INFO L276 IsEmpty]: Start isEmpty. Operand 47649 states and 143369 transitions. [2018-11-23 03:31:20,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-23 03:31:20,601 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:20,601 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:20,601 INFO L423 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:20,601 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:20,601 INFO L82 PathProgramCache]: Analyzing trace with hash 719722339, now seen corresponding path program 1 times [2018-11-23 03:31:20,601 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:20,601 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:20,602 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:20,603 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:20,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:20,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:20,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:20,659 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:20,659 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:31:20,659 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:31:20,659 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:31:20,659 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:31:20,660 INFO L87 Difference]: Start difference. First operand 47649 states and 143369 transitions. Second operand 4 states. [2018-11-23 03:31:21,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:21,240 INFO L93 Difference]: Finished difference Result 60253 states and 181234 transitions. [2018-11-23 03:31:21,241 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 03:31:21,241 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 84 [2018-11-23 03:31:21,241 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:21,316 INFO L225 Difference]: With dead ends: 60253 [2018-11-23 03:31:21,316 INFO L226 Difference]: Without dead ends: 59825 [2018-11-23 03:31:21,317 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:31:21,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59825 states. [2018-11-23 03:31:21,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59825 to 56001. [2018-11-23 03:31:21,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56001 states. [2018-11-23 03:31:22,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56001 states to 56001 states and 168841 transitions. [2018-11-23 03:31:22,024 INFO L78 Accepts]: Start accepts. Automaton has 56001 states and 168841 transitions. Word has length 84 [2018-11-23 03:31:22,024 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:22,024 INFO L480 AbstractCegarLoop]: Abstraction has 56001 states and 168841 transitions. [2018-11-23 03:31:22,024 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:31:22,024 INFO L276 IsEmpty]: Start isEmpty. Operand 56001 states and 168841 transitions. [2018-11-23 03:31:22,040 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-23 03:31:22,040 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:22,040 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:22,040 INFO L423 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:22,040 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:22,041 INFO L82 PathProgramCache]: Analyzing trace with hash 426319332, now seen corresponding path program 1 times [2018-11-23 03:31:22,041 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:22,041 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:22,042 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:22,042 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:22,042 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:22,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:22,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:22,097 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:22,097 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:31:22,097 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:31:22,097 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:31:22,097 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:31:22,098 INFO L87 Difference]: Start difference. First operand 56001 states and 168841 transitions. Second operand 5 states. [2018-11-23 03:31:22,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:22,160 INFO L93 Difference]: Finished difference Result 12621 states and 29962 transitions. [2018-11-23 03:31:22,160 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 03:31:22,160 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 84 [2018-11-23 03:31:22,160 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:22,168 INFO L225 Difference]: With dead ends: 12621 [2018-11-23 03:31:22,169 INFO L226 Difference]: Without dead ends: 10165 [2018-11-23 03:31:22,169 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:31:22,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10165 states. [2018-11-23 03:31:22,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10165 to 8860. [2018-11-23 03:31:22,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8860 states. [2018-11-23 03:31:22,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8860 states to 8860 states and 20404 transitions. [2018-11-23 03:31:22,266 INFO L78 Accepts]: Start accepts. Automaton has 8860 states and 20404 transitions. Word has length 84 [2018-11-23 03:31:22,266 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:22,266 INFO L480 AbstractCegarLoop]: Abstraction has 8860 states and 20404 transitions. [2018-11-23 03:31:22,266 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:31:22,266 INFO L276 IsEmpty]: Start isEmpty. Operand 8860 states and 20404 transitions. [2018-11-23 03:31:22,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-11-23 03:31:22,271 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:22,271 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:22,272 INFO L423 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:22,272 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:22,272 INFO L82 PathProgramCache]: Analyzing trace with hash -371203702, now seen corresponding path program 1 times [2018-11-23 03:31:22,272 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:22,272 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:22,273 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:22,273 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:22,273 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:22,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:22,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:22,328 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:22,328 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:31:22,328 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:31:22,328 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:31:22,328 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:31:22,328 INFO L87 Difference]: Start difference. First operand 8860 states and 20404 transitions. Second operand 5 states. [2018-11-23 03:31:22,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:22,431 INFO L93 Difference]: Finished difference Result 10299 states and 23671 transitions. [2018-11-23 03:31:22,432 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 03:31:22,432 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 88 [2018-11-23 03:31:22,432 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:22,440 INFO L225 Difference]: With dead ends: 10299 [2018-11-23 03:31:22,440 INFO L226 Difference]: Without dead ends: 10299 [2018-11-23 03:31:22,440 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-23 03:31:22,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10299 states. [2018-11-23 03:31:22,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10299 to 9297. [2018-11-23 03:31:22,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9297 states. [2018-11-23 03:31:22,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9297 states to 9297 states and 21406 transitions. [2018-11-23 03:31:22,523 INFO L78 Accepts]: Start accepts. Automaton has 9297 states and 21406 transitions. Word has length 88 [2018-11-23 03:31:22,523 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:22,524 INFO L480 AbstractCegarLoop]: Abstraction has 9297 states and 21406 transitions. [2018-11-23 03:31:22,524 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:31:22,524 INFO L276 IsEmpty]: Start isEmpty. Operand 9297 states and 21406 transitions. [2018-11-23 03:31:22,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-11-23 03:31:22,529 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:22,530 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:22,530 INFO L423 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:22,530 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:22,530 INFO L82 PathProgramCache]: Analyzing trace with hash 1371606633, now seen corresponding path program 1 times [2018-11-23 03:31:22,530 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:22,530 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:22,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:22,532 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:22,532 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:22,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:22,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:22,609 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:22,609 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:31:22,609 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:31:22,609 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:31:22,610 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:31:22,610 INFO L87 Difference]: Start difference. First operand 9297 states and 21406 transitions. Second operand 6 states. [2018-11-23 03:31:22,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:22,905 INFO L93 Difference]: Finished difference Result 12636 states and 28984 transitions. [2018-11-23 03:31:22,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 03:31:22,906 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 88 [2018-11-23 03:31:22,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:22,914 INFO L225 Difference]: With dead ends: 12636 [2018-11-23 03:31:22,914 INFO L226 Difference]: Without dead ends: 12517 [2018-11-23 03:31:22,914 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2018-11-23 03:31:22,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12517 states. [2018-11-23 03:31:22,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12517 to 9995. [2018-11-23 03:31:22,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9995 states. [2018-11-23 03:31:23,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9995 states to 9995 states and 23011 transitions. [2018-11-23 03:31:23,000 INFO L78 Accepts]: Start accepts. Automaton has 9995 states and 23011 transitions. Word has length 88 [2018-11-23 03:31:23,000 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:23,000 INFO L480 AbstractCegarLoop]: Abstraction has 9995 states and 23011 transitions. [2018-11-23 03:31:23,000 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:31:23,000 INFO L276 IsEmpty]: Start isEmpty. Operand 9995 states and 23011 transitions. [2018-11-23 03:31:23,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-11-23 03:31:23,007 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:23,007 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:23,007 INFO L423 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:23,007 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:23,007 INFO L82 PathProgramCache]: Analyzing trace with hash -2047011829, now seen corresponding path program 1 times [2018-11-23 03:31:23,007 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:23,007 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:23,008 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:23,008 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:23,008 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:23,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:23,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:23,060 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:23,060 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:31:23,060 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:31:23,060 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:31:23,061 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:31:23,061 INFO L87 Difference]: Start difference. First operand 9995 states and 23011 transitions. Second operand 4 states. [2018-11-23 03:31:23,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:23,260 INFO L93 Difference]: Finished difference Result 14091 states and 32163 transitions. [2018-11-23 03:31:23,260 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 03:31:23,260 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 109 [2018-11-23 03:31:23,260 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:23,271 INFO L225 Difference]: With dead ends: 14091 [2018-11-23 03:31:23,271 INFO L226 Difference]: Without dead ends: 14091 [2018-11-23 03:31:23,272 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:31:23,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14091 states. [2018-11-23 03:31:23,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14091 to 10917. [2018-11-23 03:31:23,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10917 states. [2018-11-23 03:31:23,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10917 states to 10917 states and 24843 transitions. [2018-11-23 03:31:23,383 INFO L78 Accepts]: Start accepts. Automaton has 10917 states and 24843 transitions. Word has length 109 [2018-11-23 03:31:23,384 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:23,384 INFO L480 AbstractCegarLoop]: Abstraction has 10917 states and 24843 transitions. [2018-11-23 03:31:23,384 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:31:23,384 INFO L276 IsEmpty]: Start isEmpty. Operand 10917 states and 24843 transitions. [2018-11-23 03:31:23,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-11-23 03:31:23,392 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:23,392 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:23,392 INFO L423 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:23,392 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:23,392 INFO L82 PathProgramCache]: Analyzing trace with hash -1997462001, now seen corresponding path program 2 times [2018-11-23 03:31:23,393 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:23,393 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:23,394 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:23,394 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:23,394 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:23,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:23,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:23,452 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:23,452 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:31:23,453 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:31:23,453 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:31:23,453 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:31:23,453 INFO L87 Difference]: Start difference. First operand 10917 states and 24843 transitions. Second operand 4 states. [2018-11-23 03:31:23,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:23,644 INFO L93 Difference]: Finished difference Result 11029 states and 24959 transitions. [2018-11-23 03:31:23,645 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 03:31:23,645 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 109 [2018-11-23 03:31:23,645 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:23,653 INFO L225 Difference]: With dead ends: 11029 [2018-11-23 03:31:23,653 INFO L226 Difference]: Without dead ends: 11029 [2018-11-23 03:31:23,654 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:31:23,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11029 states. [2018-11-23 03:31:23,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11029 to 10494. [2018-11-23 03:31:23,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10494 states. [2018-11-23 03:31:23,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10494 states to 10494 states and 23767 transitions. [2018-11-23 03:31:23,749 INFO L78 Accepts]: Start accepts. Automaton has 10494 states and 23767 transitions. Word has length 109 [2018-11-23 03:31:23,750 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:23,750 INFO L480 AbstractCegarLoop]: Abstraction has 10494 states and 23767 transitions. [2018-11-23 03:31:23,750 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:31:23,750 INFO L276 IsEmpty]: Start isEmpty. Operand 10494 states and 23767 transitions. [2018-11-23 03:31:23,758 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-11-23 03:31:23,758 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:23,759 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:23,759 INFO L423 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:23,759 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:23,759 INFO L82 PathProgramCache]: Analyzing trace with hash 554746858, now seen corresponding path program 1 times [2018-11-23 03:31:23,759 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:23,759 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:23,761 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:23,761 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 03:31:23,761 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:23,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:23,805 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:23,805 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:23,805 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:31:23,805 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:31:23,805 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:31:23,805 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:31:23,805 INFO L87 Difference]: Start difference. First operand 10494 states and 23767 transitions. Second operand 4 states. [2018-11-23 03:31:23,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:23,891 INFO L93 Difference]: Finished difference Result 11286 states and 25384 transitions. [2018-11-23 03:31:23,892 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 03:31:23,892 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 109 [2018-11-23 03:31:23,892 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:23,900 INFO L225 Difference]: With dead ends: 11286 [2018-11-23 03:31:23,900 INFO L226 Difference]: Without dead ends: 11286 [2018-11-23 03:31:23,900 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:31:23,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11286 states. [2018-11-23 03:31:23,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11286 to 10632. [2018-11-23 03:31:23,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10632 states. [2018-11-23 03:31:23,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10632 states to 10632 states and 23991 transitions. [2018-11-23 03:31:23,996 INFO L78 Accepts]: Start accepts. Automaton has 10632 states and 23991 transitions. Word has length 109 [2018-11-23 03:31:23,997 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:23,997 INFO L480 AbstractCegarLoop]: Abstraction has 10632 states and 23991 transitions. [2018-11-23 03:31:23,997 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:31:23,997 INFO L276 IsEmpty]: Start isEmpty. Operand 10632 states and 23991 transitions. [2018-11-23 03:31:24,004 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-23 03:31:24,004 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:24,004 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:24,004 INFO L423 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:24,004 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:24,005 INFO L82 PathProgramCache]: Analyzing trace with hash -1563716653, now seen corresponding path program 1 times [2018-11-23 03:31:24,005 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:24,005 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:24,005 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:24,006 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:24,006 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:24,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:24,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:24,056 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:24,056 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:31:24,056 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:31:24,057 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:31:24,057 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:31:24,057 INFO L87 Difference]: Start difference. First operand 10632 states and 23991 transitions. Second operand 5 states. [2018-11-23 03:31:24,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:24,223 INFO L93 Difference]: Finished difference Result 14125 states and 31666 transitions. [2018-11-23 03:31:24,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 03:31:24,224 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 111 [2018-11-23 03:31:24,225 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:24,236 INFO L225 Difference]: With dead ends: 14125 [2018-11-23 03:31:24,236 INFO L226 Difference]: Without dead ends: 14125 [2018-11-23 03:31:24,237 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:31:24,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14125 states. [2018-11-23 03:31:24,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14125 to 11534. [2018-11-23 03:31:24,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11534 states. [2018-11-23 03:31:24,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11534 states to 11534 states and 25913 transitions. [2018-11-23 03:31:24,361 INFO L78 Accepts]: Start accepts. Automaton has 11534 states and 25913 transitions. Word has length 111 [2018-11-23 03:31:24,361 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:24,361 INFO L480 AbstractCegarLoop]: Abstraction has 11534 states and 25913 transitions. [2018-11-23 03:31:24,361 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:31:24,361 INFO L276 IsEmpty]: Start isEmpty. Operand 11534 states and 25913 transitions. [2018-11-23 03:31:24,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-23 03:31:24,371 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:24,371 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:24,371 INFO L423 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:24,371 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:24,372 INFO L82 PathProgramCache]: Analyzing trace with hash -1552400526, now seen corresponding path program 1 times [2018-11-23 03:31:24,372 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:24,372 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:24,373 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:24,373 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:24,373 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:24,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:24,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:24,424 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:24,424 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:31:24,424 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:31:24,424 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:31:24,424 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:31:24,424 INFO L87 Difference]: Start difference. First operand 11534 states and 25913 transitions. Second operand 5 states. [2018-11-23 03:31:24,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:24,783 INFO L93 Difference]: Finished difference Result 18523 states and 41989 transitions. [2018-11-23 03:31:24,784 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:31:24,784 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 111 [2018-11-23 03:31:24,784 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:24,797 INFO L225 Difference]: With dead ends: 18523 [2018-11-23 03:31:24,797 INFO L226 Difference]: Without dead ends: 18523 [2018-11-23 03:31:24,798 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:31:24,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18523 states. [2018-11-23 03:31:24,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18523 to 12483. [2018-11-23 03:31:24,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12483 states. [2018-11-23 03:31:24,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12483 states to 12483 states and 28014 transitions. [2018-11-23 03:31:24,949 INFO L78 Accepts]: Start accepts. Automaton has 12483 states and 28014 transitions. Word has length 111 [2018-11-23 03:31:24,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:24,950 INFO L480 AbstractCegarLoop]: Abstraction has 12483 states and 28014 transitions. [2018-11-23 03:31:24,950 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:31:24,950 INFO L276 IsEmpty]: Start isEmpty. Operand 12483 states and 28014 transitions. [2018-11-23 03:31:24,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-23 03:31:24,959 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:24,959 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:24,960 INFO L423 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:24,960 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:24,960 INFO L82 PathProgramCache]: Analyzing trace with hash 665357427, now seen corresponding path program 1 times [2018-11-23 03:31:24,960 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:24,960 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:24,961 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:24,961 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:24,961 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:24,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:25,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:25,076 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:25,077 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 03:31:25,077 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 03:31:25,077 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 03:31:25,077 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:31:25,077 INFO L87 Difference]: Start difference. First operand 12483 states and 28014 transitions. Second operand 8 states. [2018-11-23 03:31:25,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:25,539 INFO L93 Difference]: Finished difference Result 15724 states and 35222 transitions. [2018-11-23 03:31:25,539 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-23 03:31:25,539 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 111 [2018-11-23 03:31:25,539 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:25,551 INFO L225 Difference]: With dead ends: 15724 [2018-11-23 03:31:25,551 INFO L226 Difference]: Without dead ends: 15692 [2018-11-23 03:31:25,551 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=163, Unknown=0, NotChecked=0, Total=210 [2018-11-23 03:31:25,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15692 states. [2018-11-23 03:31:25,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15692 to 14135. [2018-11-23 03:31:25,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14135 states. [2018-11-23 03:31:25,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14135 states to 14135 states and 31639 transitions. [2018-11-23 03:31:25,696 INFO L78 Accepts]: Start accepts. Automaton has 14135 states and 31639 transitions. Word has length 111 [2018-11-23 03:31:25,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:25,696 INFO L480 AbstractCegarLoop]: Abstraction has 14135 states and 31639 transitions. [2018-11-23 03:31:25,696 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 03:31:25,696 INFO L276 IsEmpty]: Start isEmpty. Operand 14135 states and 31639 transitions. [2018-11-23 03:31:25,707 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-23 03:31:25,707 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:25,707 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:25,708 INFO L423 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:25,708 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:25,708 INFO L82 PathProgramCache]: Analyzing trace with hash 371954420, now seen corresponding path program 1 times [2018-11-23 03:31:25,708 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:25,708 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:25,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:25,709 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:25,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:25,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:25,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:25,831 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:25,831 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 03:31:25,833 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 03:31:25,833 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 03:31:25,833 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:31:25,833 INFO L87 Difference]: Start difference. First operand 14135 states and 31639 transitions. Second operand 8 states. [2018-11-23 03:31:26,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:26,352 INFO L93 Difference]: Finished difference Result 22043 states and 50243 transitions. [2018-11-23 03:31:26,352 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-23 03:31:26,352 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 111 [2018-11-23 03:31:26,353 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:26,369 INFO L225 Difference]: With dead ends: 22043 [2018-11-23 03:31:26,369 INFO L226 Difference]: Without dead ends: 22043 [2018-11-23 03:31:26,369 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2018-11-23 03:31:26,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22043 states. [2018-11-23 03:31:26,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22043 to 15684. [2018-11-23 03:31:26,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15684 states. [2018-11-23 03:31:26,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15684 states to 15684 states and 35336 transitions. [2018-11-23 03:31:26,552 INFO L78 Accepts]: Start accepts. Automaton has 15684 states and 35336 transitions. Word has length 111 [2018-11-23 03:31:26,553 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:26,553 INFO L480 AbstractCegarLoop]: Abstraction has 15684 states and 35336 transitions. [2018-11-23 03:31:26,553 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 03:31:26,553 INFO L276 IsEmpty]: Start isEmpty. Operand 15684 states and 35336 transitions. [2018-11-23 03:31:26,566 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-23 03:31:26,566 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:26,566 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:26,566 INFO L423 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:26,567 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:26,567 INFO L82 PathProgramCache]: Analyzing trace with hash -1435500043, now seen corresponding path program 1 times [2018-11-23 03:31:26,567 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:26,567 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:26,568 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:26,568 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:26,568 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:26,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:26,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:26,666 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:26,666 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 03:31:26,666 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 03:31:26,666 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 03:31:26,666 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:31:26,666 INFO L87 Difference]: Start difference. First operand 15684 states and 35336 transitions. Second operand 7 states. [2018-11-23 03:31:26,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:26,814 INFO L93 Difference]: Finished difference Result 19298 states and 43961 transitions. [2018-11-23 03:31:26,814 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:31:26,814 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 111 [2018-11-23 03:31:26,815 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:26,830 INFO L225 Difference]: With dead ends: 19298 [2018-11-23 03:31:26,830 INFO L226 Difference]: Without dead ends: 19298 [2018-11-23 03:31:26,830 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2018-11-23 03:31:26,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19298 states. [2018-11-23 03:31:26,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19298 to 15237. [2018-11-23 03:31:26,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15237 states. [2018-11-23 03:31:26,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15237 states to 15237 states and 34087 transitions. [2018-11-23 03:31:26,994 INFO L78 Accepts]: Start accepts. Automaton has 15237 states and 34087 transitions. Word has length 111 [2018-11-23 03:31:26,994 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:26,994 INFO L480 AbstractCegarLoop]: Abstraction has 15237 states and 34087 transitions. [2018-11-23 03:31:26,994 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 03:31:26,995 INFO L276 IsEmpty]: Start isEmpty. Operand 15237 states and 34087 transitions. [2018-11-23 03:31:27,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-23 03:31:27,007 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:27,007 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:27,008 INFO L423 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:27,008 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:27,008 INFO L82 PathProgramCache]: Analyzing trace with hash 583305333, now seen corresponding path program 1 times [2018-11-23 03:31:27,008 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:27,008 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:27,009 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:27,009 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:27,009 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:27,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:27,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:27,111 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:27,111 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:31:27,111 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:31:27,111 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:31:27,112 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:31:27,112 INFO L87 Difference]: Start difference. First operand 15237 states and 34087 transitions. Second operand 6 states. [2018-11-23 03:31:27,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:27,233 INFO L93 Difference]: Finished difference Result 15633 states and 34370 transitions. [2018-11-23 03:31:27,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:31:27,233 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 111 [2018-11-23 03:31:27,233 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:27,245 INFO L225 Difference]: With dead ends: 15633 [2018-11-23 03:31:27,245 INFO L226 Difference]: Without dead ends: 15633 [2018-11-23 03:31:27,245 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:31:27,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15633 states. [2018-11-23 03:31:27,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15633 to 10089. [2018-11-23 03:31:27,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10089 states. [2018-11-23 03:31:27,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10089 states to 10089 states and 22346 transitions. [2018-11-23 03:31:27,369 INFO L78 Accepts]: Start accepts. Automaton has 10089 states and 22346 transitions. Word has length 111 [2018-11-23 03:31:27,370 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:27,370 INFO L480 AbstractCegarLoop]: Abstraction has 10089 states and 22346 transitions. [2018-11-23 03:31:27,370 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:31:27,370 INFO L276 IsEmpty]: Start isEmpty. Operand 10089 states and 22346 transitions. [2018-11-23 03:31:27,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-23 03:31:27,377 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:27,377 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:27,377 INFO L423 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:27,377 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:27,377 INFO L82 PathProgramCache]: Analyzing trace with hash 217281873, now seen corresponding path program 1 times [2018-11-23 03:31:27,377 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:27,377 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:27,378 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:27,378 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:27,378 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:27,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:27,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:27,451 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:27,451 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:31:27,451 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:31:27,451 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:31:27,451 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:31:27,451 INFO L87 Difference]: Start difference. First operand 10089 states and 22346 transitions. Second operand 5 states. [2018-11-23 03:31:27,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:27,483 INFO L93 Difference]: Finished difference Result 10089 states and 22330 transitions. [2018-11-23 03:31:27,483 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 03:31:27,483 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 113 [2018-11-23 03:31:27,483 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:27,490 INFO L225 Difference]: With dead ends: 10089 [2018-11-23 03:31:27,490 INFO L226 Difference]: Without dead ends: 10089 [2018-11-23 03:31:27,491 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:31:27,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10089 states. [2018-11-23 03:31:27,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10089 to 10089. [2018-11-23 03:31:27,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10089 states. [2018-11-23 03:31:27,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10089 states to 10089 states and 22330 transitions. [2018-11-23 03:31:27,576 INFO L78 Accepts]: Start accepts. Automaton has 10089 states and 22330 transitions. Word has length 113 [2018-11-23 03:31:27,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:27,576 INFO L480 AbstractCegarLoop]: Abstraction has 10089 states and 22330 transitions. [2018-11-23 03:31:27,576 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:31:27,576 INFO L276 IsEmpty]: Start isEmpty. Operand 10089 states and 22330 transitions. [2018-11-23 03:31:27,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-23 03:31:27,584 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:27,584 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:27,584 INFO L423 AbstractCegarLoop]: === Iteration 32 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:27,585 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:27,585 INFO L82 PathProgramCache]: Analyzing trace with hash -1590172590, now seen corresponding path program 1 times [2018-11-23 03:31:27,585 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:27,585 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:27,586 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:27,586 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:27,586 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:27,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:27,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:27,626 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:27,626 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 03:31:27,626 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 03:31:27,626 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 03:31:27,626 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 03:31:27,627 INFO L87 Difference]: Start difference. First operand 10089 states and 22330 transitions. Second operand 3 states. [2018-11-23 03:31:27,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:27,649 INFO L93 Difference]: Finished difference Result 10089 states and 22314 transitions. [2018-11-23 03:31:27,649 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 03:31:27,649 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2018-11-23 03:31:27,649 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:27,656 INFO L225 Difference]: With dead ends: 10089 [2018-11-23 03:31:27,656 INFO L226 Difference]: Without dead ends: 10089 [2018-11-23 03:31:27,657 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 03:31:27,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10089 states. [2018-11-23 03:31:27,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10089 to 10089. [2018-11-23 03:31:27,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10089 states. [2018-11-23 03:31:27,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10089 states to 10089 states and 22314 transitions. [2018-11-23 03:31:27,741 INFO L78 Accepts]: Start accepts. Automaton has 10089 states and 22314 transitions. Word has length 113 [2018-11-23 03:31:27,741 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:27,742 INFO L480 AbstractCegarLoop]: Abstraction has 10089 states and 22314 transitions. [2018-11-23 03:31:27,742 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 03:31:27,742 INFO L276 IsEmpty]: Start isEmpty. Operand 10089 states and 22314 transitions. [2018-11-23 03:31:27,748 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-11-23 03:31:27,748 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:27,749 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:27,749 INFO L423 AbstractCegarLoop]: === Iteration 33 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:27,749 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:27,749 INFO L82 PathProgramCache]: Analyzing trace with hash 1851971030, now seen corresponding path program 1 times [2018-11-23 03:31:27,749 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:27,749 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:27,750 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:27,750 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:27,750 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:27,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:27,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:27,849 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:27,849 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-23 03:31:27,850 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 03:31:27,850 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 03:31:27,850 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2018-11-23 03:31:27,850 INFO L87 Difference]: Start difference. First operand 10089 states and 22314 transitions. Second operand 9 states. [2018-11-23 03:31:28,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:28,142 INFO L93 Difference]: Finished difference Result 12161 states and 26975 transitions. [2018-11-23 03:31:28,143 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 03:31:28,143 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 115 [2018-11-23 03:31:28,143 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:28,144 INFO L225 Difference]: With dead ends: 12161 [2018-11-23 03:31:28,144 INFO L226 Difference]: Without dead ends: 2071 [2018-11-23 03:31:28,145 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=55, Invalid=155, Unknown=0, NotChecked=0, Total=210 [2018-11-23 03:31:28,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2071 states. [2018-11-23 03:31:28,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2071 to 2071. [2018-11-23 03:31:28,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2071 states. [2018-11-23 03:31:28,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2071 states to 2071 states and 4621 transitions. [2018-11-23 03:31:28,159 INFO L78 Accepts]: Start accepts. Automaton has 2071 states and 4621 transitions. Word has length 115 [2018-11-23 03:31:28,160 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:28,160 INFO L480 AbstractCegarLoop]: Abstraction has 2071 states and 4621 transitions. [2018-11-23 03:31:28,160 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 03:31:28,160 INFO L276 IsEmpty]: Start isEmpty. Operand 2071 states and 4621 transitions. [2018-11-23 03:31:28,161 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-11-23 03:31:28,161 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:28,161 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:28,162 INFO L423 AbstractCegarLoop]: === Iteration 34 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:28,162 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:28,162 INFO L82 PathProgramCache]: Analyzing trace with hash 777976698, now seen corresponding path program 1 times [2018-11-23 03:31:28,162 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:28,162 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:28,163 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:28,163 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:28,163 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:28,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:28,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:28,224 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:28,224 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:31:28,224 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:31:28,224 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:31:28,224 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:31:28,224 INFO L87 Difference]: Start difference. First operand 2071 states and 4621 transitions. Second operand 6 states. [2018-11-23 03:31:28,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:28,324 INFO L93 Difference]: Finished difference Result 2101 states and 4594 transitions. [2018-11-23 03:31:28,325 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 03:31:28,325 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 115 [2018-11-23 03:31:28,325 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:28,327 INFO L225 Difference]: With dead ends: 2101 [2018-11-23 03:31:28,327 INFO L226 Difference]: Without dead ends: 2101 [2018-11-23 03:31:28,327 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:31:28,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2101 states. [2018-11-23 03:31:28,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2101 to 1707. [2018-11-23 03:31:28,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1707 states. [2018-11-23 03:31:28,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1707 states to 1707 states and 3722 transitions. [2018-11-23 03:31:28,347 INFO L78 Accepts]: Start accepts. Automaton has 1707 states and 3722 transitions. Word has length 115 [2018-11-23 03:31:28,347 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:28,348 INFO L480 AbstractCegarLoop]: Abstraction has 1707 states and 3722 transitions. [2018-11-23 03:31:28,348 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:31:28,348 INFO L276 IsEmpty]: Start isEmpty. Operand 1707 states and 3722 transitions. [2018-11-23 03:31:28,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-11-23 03:31:28,350 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:28,350 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:28,350 INFO L423 AbstractCegarLoop]: === Iteration 35 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:28,350 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:28,350 INFO L82 PathProgramCache]: Analyzing trace with hash 1865893307, now seen corresponding path program 1 times [2018-11-23 03:31:28,350 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:28,350 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:28,352 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:28,352 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:28,352 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:28,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:28,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:28,434 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:28,434 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:31:28,434 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:31:28,434 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:31:28,434 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:31:28,434 INFO L87 Difference]: Start difference. First operand 1707 states and 3722 transitions. Second operand 6 states. [2018-11-23 03:31:28,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:28,517 INFO L93 Difference]: Finished difference Result 1914 states and 4138 transitions. [2018-11-23 03:31:28,517 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:31:28,517 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 115 [2018-11-23 03:31:28,517 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:28,519 INFO L225 Difference]: With dead ends: 1914 [2018-11-23 03:31:28,519 INFO L226 Difference]: Without dead ends: 1883 [2018-11-23 03:31:28,520 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:31:28,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1883 states. [2018-11-23 03:31:28,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1883 to 1615. [2018-11-23 03:31:28,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1615 states. [2018-11-23 03:31:28,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1615 states to 1615 states and 3523 transitions. [2018-11-23 03:31:28,539 INFO L78 Accepts]: Start accepts. Automaton has 1615 states and 3523 transitions. Word has length 115 [2018-11-23 03:31:28,539 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:28,539 INFO L480 AbstractCegarLoop]: Abstraction has 1615 states and 3523 transitions. [2018-11-23 03:31:28,540 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:31:28,540 INFO L276 IsEmpty]: Start isEmpty. Operand 1615 states and 3523 transitions. [2018-11-23 03:31:28,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-11-23 03:31:28,541 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:28,542 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:28,542 INFO L423 AbstractCegarLoop]: === Iteration 36 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:28,542 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:28,542 INFO L82 PathProgramCache]: Analyzing trace with hash -1735972292, now seen corresponding path program 2 times [2018-11-23 03:31:28,542 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:28,542 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:28,543 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:28,544 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:28,544 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:28,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:28,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:28,846 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:28,846 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2018-11-23 03:31:28,847 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-23 03:31:28,847 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-23 03:31:28,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=232, Unknown=0, NotChecked=0, Total=272 [2018-11-23 03:31:28,847 INFO L87 Difference]: Start difference. First operand 1615 states and 3523 transitions. Second operand 17 states. [2018-11-23 03:31:29,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:29,263 INFO L93 Difference]: Finished difference Result 1771 states and 3861 transitions. [2018-11-23 03:31:29,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-23 03:31:29,263 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 115 [2018-11-23 03:31:29,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:29,265 INFO L225 Difference]: With dead ends: 1771 [2018-11-23 03:31:29,265 INFO L226 Difference]: Without dead ends: 1675 [2018-11-23 03:31:29,266 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=144, Invalid=612, Unknown=0, NotChecked=0, Total=756 [2018-11-23 03:31:29,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1675 states. [2018-11-23 03:31:29,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1675 to 1615. [2018-11-23 03:31:29,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1615 states. [2018-11-23 03:31:29,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1615 states to 1615 states and 3507 transitions. [2018-11-23 03:31:29,279 INFO L78 Accepts]: Start accepts. Automaton has 1615 states and 3507 transitions. Word has length 115 [2018-11-23 03:31:29,279 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:29,280 INFO L480 AbstractCegarLoop]: Abstraction has 1615 states and 3507 transitions. [2018-11-23 03:31:29,280 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-23 03:31:29,280 INFO L276 IsEmpty]: Start isEmpty. Operand 1615 states and 3507 transitions. [2018-11-23 03:31:29,281 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-11-23 03:31:29,282 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:29,282 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:29,282 INFO L423 AbstractCegarLoop]: === Iteration 37 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:29,282 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:29,282 INFO L82 PathProgramCache]: Analyzing trace with hash 816184669, now seen corresponding path program 1 times [2018-11-23 03:31:29,282 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:29,282 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:29,284 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:29,284 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 03:31:29,284 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:29,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:31:29,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:31:29,726 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:31:29,727 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [25] imperfect sequences [] total 25 [2018-11-23 03:31:29,727 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-11-23 03:31:29,727 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-11-23 03:31:29,727 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=539, Unknown=0, NotChecked=0, Total=600 [2018-11-23 03:31:29,728 INFO L87 Difference]: Start difference. First operand 1615 states and 3507 transitions. Second operand 25 states. [2018-11-23 03:31:30,677 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:31:30,677 INFO L93 Difference]: Finished difference Result 2904 states and 6388 transitions. [2018-11-23 03:31:30,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-23 03:31:30,677 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 115 [2018-11-23 03:31:30,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:31:30,679 INFO L225 Difference]: With dead ends: 2904 [2018-11-23 03:31:30,679 INFO L226 Difference]: Without dead ends: 1996 [2018-11-23 03:31:30,680 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 358 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=351, Invalid=1811, Unknown=0, NotChecked=0, Total=2162 [2018-11-23 03:31:30,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1996 states. [2018-11-23 03:31:30,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1996 to 1670. [2018-11-23 03:31:30,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1670 states. [2018-11-23 03:31:30,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1670 states to 1670 states and 3619 transitions. [2018-11-23 03:31:30,695 INFO L78 Accepts]: Start accepts. Automaton has 1670 states and 3619 transitions. Word has length 115 [2018-11-23 03:31:30,695 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:31:30,695 INFO L480 AbstractCegarLoop]: Abstraction has 1670 states and 3619 transitions. [2018-11-23 03:31:30,695 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-11-23 03:31:30,695 INFO L276 IsEmpty]: Start isEmpty. Operand 1670 states and 3619 transitions. [2018-11-23 03:31:30,696 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-11-23 03:31:30,696 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:31:30,696 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:31:30,696 INFO L423 AbstractCegarLoop]: === Iteration 38 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:31:30,697 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:31:30,697 INFO L82 PathProgramCache]: Analyzing trace with hash 1119572719, now seen corresponding path program 2 times [2018-11-23 03:31:30,697 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:31:30,697 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:31:30,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:30,698 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:31:30,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:31:30,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 03:31:30,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 03:31:30,764 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [596] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [520] L-1-->L671: Formula: (= |v_#valid_1| (store |v_#valid_2| 0 0)) InVars {#valid=|v_#valid_2|} OutVars{#valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [632] L671-->L673: Formula: (= v_~__unbuffered_cnt~0_5 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [680] L673-->L675: Formula: (= v_~__unbuffered_p0_EAX~0_2 0) InVars {} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_2} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 [570] L675-->L676: Formula: (= v_~__unbuffered_p1_EAX~0_2 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [513] L676-->L677: Formula: (= v_~__unbuffered_p1_EAX$flush_delayed~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$flush_delayed~0=v_~__unbuffered_p1_EAX$flush_delayed~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [603] L677-->L678: Formula: (= v_~__unbuffered_p1_EAX$mem_tmp~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$mem_tmp~0=v_~__unbuffered_p1_EAX$mem_tmp~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [709] L678-->L679: Formula: (= v_~__unbuffered_p1_EAX$r_buff0_thd0~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$r_buff0_thd0~0=v_~__unbuffered_p1_EAX$r_buff0_thd0~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [767] L679-->L680: Formula: (= v_~__unbuffered_p1_EAX$r_buff0_thd1~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$r_buff0_thd1~0=v_~__unbuffered_p1_EAX$r_buff0_thd1~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [727] L680-->L681: Formula: (= v_~__unbuffered_p1_EAX$r_buff0_thd2~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$r_buff0_thd2~0=v_~__unbuffered_p1_EAX$r_buff0_thd2~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [536] L681-->L682: Formula: (= v_~__unbuffered_p1_EAX$r_buff1_thd0~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$r_buff1_thd0~0=v_~__unbuffered_p1_EAX$r_buff1_thd0~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [629] L682-->L683: Formula: (= v_~__unbuffered_p1_EAX$r_buff1_thd1~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$r_buff1_thd1~0=v_~__unbuffered_p1_EAX$r_buff1_thd1~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [576] L683-->L684: Formula: (= v_~__unbuffered_p1_EAX$r_buff1_thd2~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$r_buff1_thd2~0=v_~__unbuffered_p1_EAX$r_buff1_thd2~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [679] L684-->L685: Formula: (= v_~__unbuffered_p1_EAX$read_delayed~0_2 0) InVars {} OutVars{~__unbuffered_p1_EAX$read_delayed~0=v_~__unbuffered_p1_EAX$read_delayed~0_2} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [744] L685-->L686: Formula: (and (= v_~__unbuffered_p1_EAX$read_delayed_var~0.base_2 0) (= v_~__unbuffered_p1_EAX$read_delayed_var~0.offset_2 0)) InVars {} OutVars{~__unbuffered_p1_EAX$read_delayed_var~0.base=v_~__unbuffered_p1_EAX$read_delayed_var~0.base_2, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=v_~__unbuffered_p1_EAX$read_delayed_var~0.offset_2} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [569] L686-->L687: Formula: (= v_~__unbuffered_p1_EAX$w_buff0~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$w_buff0~0=v_~__unbuffered_p1_EAX$w_buff0~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [533] L687-->L688: Formula: (= v_~__unbuffered_p1_EAX$w_buff0_used~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$w_buff0_used~0=v_~__unbuffered_p1_EAX$w_buff0_used~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [602] L688-->L689: Formula: (= v_~__unbuffered_p1_EAX$w_buff1~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$w_buff1~0=v_~__unbuffered_p1_EAX$w_buff1~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [707] L689-->L690: Formula: (= v_~__unbuffered_p1_EAX$w_buff1_used~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$w_buff1_used~0=v_~__unbuffered_p1_EAX$w_buff1_used~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [766] L690-->L691: Formula: (= v_~main$tmp_guard0~0_1 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [?] -1 [725] L691-->L693: Formula: (= v_~main$tmp_guard1~0_1 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_1} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [627] L693-->L693-1: Formula: (and (= |v_#length_1| (store |v_#length_2| |v_~#x~0.base_13| 4)) (= |v_~#x~0.offset_13| 0) (not (= 0 |v_~#x~0.base_13|)) (= (store |v_#valid_4| |v_~#x~0.base_13| 1) |v_#valid_3|) (= 0 (select |v_#valid_4| |v_~#x~0.base_13|))) InVars {#length=|v_#length_2|, #valid=|v_#valid_4|} OutVars{~#x~0.base=|v_~#x~0.base_13|, #length=|v_#length_1|, ~#x~0.offset=|v_~#x~0.offset_13|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[~#x~0.offset, #valid, ~#x~0.base, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [611] L693-1-->L693-2: Formula: (= (select (select |v_#memory_int_17| |v_~#x~0.base_14|) |v_~#x~0.offset_14|) 0) InVars {~#x~0.base=|v_~#x~0.base_14|, #memory_int=|v_#memory_int_17|, ~#x~0.offset=|v_~#x~0.offset_14|} OutVars{~#x~0.base=|v_~#x~0.base_14|, #memory_int=|v_#memory_int_17|, ~#x~0.offset=|v_~#x~0.offset_14|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [614] L693-2-->L695: Formula: (= v_~x$flush_delayed~0_5 0) InVars {} OutVars{~x$flush_delayed~0=v_~x$flush_delayed~0_5} AuxVars[] AssignedVars[~x$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [?] -1 [678] L695-->L696: Formula: (= v_~x$mem_tmp~0_3 0) InVars {} OutVars{~x$mem_tmp~0=v_~x$mem_tmp~0_3} AuxVars[] AssignedVars[~x$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [?] -1 [743] L696-->L697: Formula: (= v_~x$r_buff0_thd0~0_2 0) InVars {} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_2} AuxVars[] AssignedVars[~x$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [?] -1 [566] L697-->L698: Formula: (= v_~x$r_buff0_thd1~0_14 0) InVars {} OutVars{~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_14} AuxVars[] AssignedVars[~x$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [?] -1 [532] L698-->L699: Formula: (= v_~x$r_buff0_thd2~0_58 0) InVars {} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_58} AuxVars[] AssignedVars[~x$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [?] -1 [601] L699-->L700: Formula: (= v_~x$r_buff1_thd0~0_2 0) InVars {} OutVars{~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_2} AuxVars[] AssignedVars[~x$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [?] -1 [706] L700-->L701: Formula: (= v_~x$r_buff1_thd1~0_9 0) InVars {} OutVars{~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_9} AuxVars[] AssignedVars[~x$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [?] -1 [765] L701-->L702: Formula: (= v_~x$r_buff1_thd2~0_41 0) InVars {} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_41} AuxVars[] AssignedVars[~x$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [?] -1 [724] L702-->L703: Formula: (= v_~x$read_delayed~0_1 0) InVars {} OutVars{~x$read_delayed~0=v_~x$read_delayed~0_1} AuxVars[] AssignedVars[~x$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [?] -1 [560] L703-->L704: Formula: (and (= v_~x$read_delayed_var~0.offset_1 0) (= v_~x$read_delayed_var~0.base_1 0)) InVars {} OutVars{~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_1, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~x$read_delayed_var~0.offset, ~x$read_delayed_var~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0] [?] -1 [624] L704-->L705: Formula: (= v_~x$w_buff0~0_16 0) InVars {} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_16} AuxVars[] AssignedVars[~x$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [?] -1 [575] L705-->L706: Formula: (= v_~x$w_buff0_used~0_83 0) InVars {} OutVars{~x$w_buff0_used~0=v_~x$w_buff0_used~0_83} AuxVars[] AssignedVars[~x$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [?] -1 [676] L706-->L707: Formula: (= v_~x$w_buff1~0_13 0) InVars {} OutVars{~x$w_buff1~0=v_~x$w_buff1~0_13} AuxVars[] AssignedVars[~x$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [?] -1 [742] L707-->L709: Formula: (= v_~x$w_buff1_used~0_47 0) InVars {} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_47} AuxVars[] AssignedVars[~x$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [?] -1 [531] L709-->L710: Formula: (= v_~y~0_3 0) InVars {} OutVars{~y~0=v_~y~0_3} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [600] L710-->L711: Formula: (= v_~weak$$choice0~0_14 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_14} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [705] L711-->L712: Formula: (= v_~weak$$choice1~0_5 0) InVars {} OutVars{~weak$$choice1~0=v_~weak$$choice1~0_5} AuxVars[] AssignedVars[~weak$$choice1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [764] L712-->L-1-1: Formula: (= v_~weak$$choice2~0_14 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_14} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [628] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [623] L-1-2-->L788: Formula: true InVars {} OutVars{ULTIMATE.start_main_~#t2669~0.offset=|v_ULTIMATE.start_main_~#t2669~0.offset_1|, ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_1|, ULTIMATE.start_main_#t~nondet69=|v_ULTIMATE.start_main_#t~nondet69_1|, ULTIMATE.start_main_#t~nondet68=|v_ULTIMATE.start_main_#t~nondet68_1|, ULTIMATE.start_main_~#t2669~0.base=|v_ULTIMATE.start_main_~#t2669~0.base_1|, ULTIMATE.start_main_#t~mem70=|v_ULTIMATE.start_main_#t~mem70_1|, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_1|, ULTIMATE.start_main_~#t2670~0.offset=|v_ULTIMATE.start_main_~#t2670~0.offset_1|, ULTIMATE.start_main_~#t2670~0.base=|v_ULTIMATE.start_main_~#t2670~0.base_1|, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_1|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_1|, ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_1|, ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_1|, ULTIMATE.start_main_#t~ite71=|v_ULTIMATE.start_main_#t~ite71_1|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_1|, ULTIMATE.start_main_#t~nondet77.offset=|v_ULTIMATE.start_main_#t~nondet77.offset_1|, ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_1|, ULTIMATE.start_main_#t~nondet77.base=|v_ULTIMATE.start_main_#t~nondet77.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2669~0.offset, ULTIMATE.start_main_#t~mem78, ULTIMATE.start_main_#t~nondet69, ULTIMATE.start_main_#t~nondet68, ULTIMATE.start_main_~#t2669~0.base, ULTIMATE.start_main_#t~mem70, ULTIMATE.start_main_#t~ite79, ULTIMATE.start_main_~#t2670~0.offset, ULTIMATE.start_main_~#t2670~0.base, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~ite76, ULTIMATE.start_main_#t~ite73, ULTIMATE.start_main_#t~ite74, ULTIMATE.start_main_#t~ite71, ULTIMATE.start_main_#t~ite72, ULTIMATE.start_main_#t~nondet77.offset, ULTIMATE.start_main_#t~ite80, ULTIMATE.start_main_#t~nondet77.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [701] L788-->L788-1: Formula: (and (= 0 (select |v_#valid_6| |v_ULTIMATE.start_main_~#t2669~0.base_2|)) (not (= |v_ULTIMATE.start_main_~#t2669~0.base_2| 0)) (= (store |v_#length_4| |v_ULTIMATE.start_main_~#t2669~0.base_2| 4) |v_#length_3|) (= 0 |v_ULTIMATE.start_main_~#t2669~0.offset_2|) (= (store |v_#valid_6| |v_ULTIMATE.start_main_~#t2669~0.base_2| 1) |v_#valid_5|)) InVars {#length=|v_#length_4|, #valid=|v_#valid_6|} OutVars{ULTIMATE.start_main_~#t2669~0.offset=|v_ULTIMATE.start_main_~#t2669~0.offset_2|, #length=|v_#length_3|, ULTIMATE.start_main_~#t2669~0.base=|v_ULTIMATE.start_main_~#t2669~0.base_2|, #valid=|v_#valid_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2669~0.offset, ULTIMATE.start_main_~#t2669~0.base, #valid, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [702] L788-1-->L789: Formula: (= (store |v_#memory_int_19| |v_ULTIMATE.start_main_~#t2669~0.base_3| (store (select |v_#memory_int_19| |v_ULTIMATE.start_main_~#t2669~0.base_3|) |v_ULTIMATE.start_main_~#t2669~0.offset_3| 0)) |v_#memory_int_18|) InVars {ULTIMATE.start_main_~#t2669~0.offset=|v_ULTIMATE.start_main_~#t2669~0.offset_3|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_~#t2669~0.base=|v_ULTIMATE.start_main_~#t2669~0.base_3|} OutVars{ULTIMATE.start_main_~#t2669~0.offset=|v_ULTIMATE.start_main_~#t2669~0.offset_3|, #memory_int=|v_#memory_int_18|, ULTIMATE.start_main_~#t2669~0.base=|v_ULTIMATE.start_main_~#t2669~0.base_3|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] FORK -1 [942] L789-->P0ENTRY: Formula: (and (= 0 |v_Thread1_P0_#in~arg.base_3|) (= 0 v_Thread1_P0_thidvar0_2) (= 0 |v_Thread1_P0_#in~arg.offset_3|)) InVars {} OutVars{Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_3|, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_3|, Thread1_P0_thidvar0=v_Thread1_P0_thidvar0_2} AuxVars[] AssignedVars[Thread1_P0_#in~arg.base, Thread1_P0_#in~arg.offset, Thread1_P0_thidvar0] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [760] L789-1-->L790: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet68=|v_ULTIMATE.start_main_#t~nondet68_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet68] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [738] L790-->L790-1: Formula: (and (= |v_ULTIMATE.start_main_~#t2670~0.offset_2| 0) (= |v_#length_5| (store |v_#length_6| |v_ULTIMATE.start_main_~#t2670~0.base_2| 4)) (= (select |v_#valid_8| |v_ULTIMATE.start_main_~#t2670~0.base_2|) 0) (not (= |v_ULTIMATE.start_main_~#t2670~0.base_2| 0)) (= |v_#valid_7| (store |v_#valid_8| |v_ULTIMATE.start_main_~#t2670~0.base_2| 1))) InVars {#length=|v_#length_6|, #valid=|v_#valid_8|} OutVars{ULTIMATE.start_main_~#t2670~0.offset=|v_ULTIMATE.start_main_~#t2670~0.offset_2|, #length=|v_#length_5|, ULTIMATE.start_main_~#t2670~0.base=|v_ULTIMATE.start_main_~#t2670~0.base_2|, #valid=|v_#valid_7|} AuxVars[] AssignedVars[#valid, ULTIMATE.start_main_~#t2670~0.offset, #length, ULTIMATE.start_main_~#t2670~0.base] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [739] L790-1-->L791: Formula: (= (store |v_#memory_int_21| |v_ULTIMATE.start_main_~#t2670~0.base_3| (store (select |v_#memory_int_21| |v_ULTIMATE.start_main_~#t2670~0.base_3|) |v_ULTIMATE.start_main_~#t2670~0.offset_3| 1)) |v_#memory_int_20|) InVars {#memory_int=|v_#memory_int_21|, ULTIMATE.start_main_~#t2670~0.offset=|v_ULTIMATE.start_main_~#t2670~0.offset_3|, ULTIMATE.start_main_~#t2670~0.base=|v_ULTIMATE.start_main_~#t2670~0.base_3|} OutVars{#memory_int=|v_#memory_int_20|, ULTIMATE.start_main_~#t2670~0.offset=|v_ULTIMATE.start_main_~#t2670~0.offset_3|, ULTIMATE.start_main_~#t2670~0.base=|v_ULTIMATE.start_main_~#t2670~0.base_3|} AuxVars[] AssignedVars[#memory_int] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] FORK -1 [941] L791-->P1ENTRY: Formula: (and (= 0 |v_Thread0_P1_#in~arg.offset_3|) (= 1 v_Thread0_P1_thidvar0_2) (= 0 |v_Thread0_P1_#in~arg.base_3|)) InVars {} OutVars{Thread0_P1_thidvar0=v_Thread0_P1_thidvar0_2, Thread0_P1_#in~arg.base=|v_Thread0_P1_#in~arg.base_3|, Thread0_P1_#in~arg.offset=|v_Thread0_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P1_thidvar0, Thread0_P1_#in~arg.base, Thread0_P1_#in~arg.offset] VAL [Thread0_P1_thidvar0=1, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [799] P1ENTRY-->L749: Formula: (and (= v_Thread0_P1_~arg.offset_1 |v_Thread0_P1_#in~arg.offset_1|) (= v_~weak$$choice0~0_3 (ite (= (+ |v_Thread0_P1_#t~nondet11.offset_1| |v_Thread0_P1_#t~nondet11.base_1|) 0) 0 1)) (= v_~x$flush_delayed~0_1 v_~weak$$choice2~0_5) (= v_~weak$$choice2~0_5 (ite (= (+ |v_Thread0_P1_#t~nondet12.offset_1| |v_Thread0_P1_#t~nondet12.base_1|) 0) 0 1)) (= v_~x$mem_tmp~0_1 (select (select |v_#memory_int_4| |v_~#x~0.base_3|) |v_~#x~0.offset_3|)) (= v_Thread0_P1_~arg.base_1 |v_Thread0_P1_#in~arg.base_1|) (= v_~weak$$choice1~0_1 (ite (= (+ |v_Thread0_P1_#t~nondet14.offset_1| |v_Thread0_P1_#t~nondet14.base_1|) 0) 0 1))) InVars {Thread0_P1_#in~arg.base=|v_Thread0_P1_#in~arg.base_1|, Thread0_P1_#t~nondet12.offset=|v_Thread0_P1_#t~nondet12.offset_1|, Thread0_P1_#t~nondet11.base=|v_Thread0_P1_#t~nondet11.base_1|, ~#x~0.offset=|v_~#x~0.offset_3|, Thread0_P1_#t~nondet14.base=|v_Thread0_P1_#t~nondet14.base_1|, Thread0_P1_#t~nondet14.offset=|v_Thread0_P1_#t~nondet14.offset_1|, ~#x~0.base=|v_~#x~0.base_3|, #memory_int=|v_#memory_int_4|, Thread0_P1_#t~nondet12.base=|v_Thread0_P1_#t~nondet12.base_1|, Thread0_P1_#t~nondet11.offset=|v_Thread0_P1_#t~nondet11.offset_1|, Thread0_P1_#in~arg.offset=|v_Thread0_P1_#in~arg.offset_1|} OutVars{Thread0_P1_#in~arg.base=|v_Thread0_P1_#in~arg.base_1|, Thread0_P1_~arg.offset=v_Thread0_P1_~arg.offset_1, Thread0_P1_#t~nondet12.offset=|v_Thread0_P1_#t~nondet12.offset_2|, Thread0_P1_#t~nondet11.base=|v_Thread0_P1_#t~nondet11.base_2|, ~#x~0.offset=|v_~#x~0.offset_3|, ~x$flush_delayed~0=v_~x$flush_delayed~0_1, Thread0_P1_#t~nondet14.offset=|v_Thread0_P1_#t~nondet14.offset_2|, ~x$mem_tmp~0=v_~x$mem_tmp~0_1, Thread0_P1_#in~arg.offset=|v_Thread0_P1_#in~arg.offset_1|, ~weak$$choice0~0=v_~weak$$choice0~0_3, ~weak$$choice1~0=v_~weak$$choice1~0_1, Thread0_P1_#t~nondet14.base=|v_Thread0_P1_#t~nondet14.base_2|, Thread0_P1_~arg.base=v_Thread0_P1_~arg.base_1, Thread0_P1_#t~mem13=|v_Thread0_P1_#t~mem13_1|, ~#x~0.base=|v_~#x~0.base_3|, #memory_int=|v_#memory_int_4|, Thread0_P1_#t~nondet12.base=|v_Thread0_P1_#t~nondet12.base_2|, Thread0_P1_#t~nondet11.offset=|v_Thread0_P1_#t~nondet11.offset_2|, ~weak$$choice2~0=v_~weak$$choice2~0_5} AuxVars[] AssignedVars[Thread0_P1_~arg.offset, Thread0_P1_#t~nondet12.offset, Thread0_P1_#t~nondet11.base, ~x$flush_delayed~0, Thread0_P1_#t~nondet14.offset, ~x$mem_tmp~0, ~weak$$choice0~0, ~weak$$choice1~0, Thread0_P1_#t~nondet14.base, Thread0_P1_~arg.base, Thread0_P1_#t~mem13, Thread0_P1_#t~nondet12.base, Thread0_P1_#t~nondet11.offset, ~weak$$choice2~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [800] L749-->L749-23: Formula: (and (= 0 (mod v_~x$w_buff0_used~0_28 256)) (= |v_Thread0_P1_#t~ite25_1| |v_Thread0_P1_#t~mem15_1|) (= |v_Thread0_P1_#t~mem15_1| (select (select |v_#memory_int_5| |v_~#x~0.base_4|) |v_~#x~0.offset_4|))) InVars {~#x~0.base=|v_~#x~0.base_4|, #memory_int=|v_#memory_int_5|, ~#x~0.offset=|v_~#x~0.offset_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_28} OutVars{~#x~0.offset=|v_~#x~0.offset_4|, ~#x~0.base=|v_~#x~0.base_4|, #memory_int=|v_#memory_int_5|, Thread0_P1_#t~mem15=|v_Thread0_P1_#t~mem15_1|, Thread0_P1_#t~ite25=|v_Thread0_P1_#t~ite25_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_28} AuxVars[] AssignedVars[Thread0_P1_#t~mem15, Thread0_P1_#t~ite25] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite25|=0, |Thread0_P1_#t~mem15|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [802] L749-23-->L750: Formula: (= (store |v_#memory_int_16| |v_~#x~0.base_12| (store (select |v_#memory_int_16| |v_~#x~0.base_12|) |v_~#x~0.offset_12| |v_Thread0_P1_#t~ite25_2|)) |v_#memory_int_15|) InVars {#memory_int=|v_#memory_int_16|, ~#x~0.base=|v_~#x~0.base_12|, ~#x~0.offset=|v_~#x~0.offset_12|, Thread0_P1_#t~ite25=|v_Thread0_P1_#t~ite25_2|} OutVars{~#x~0.offset=|v_~#x~0.offset_12|, Thread0_P1_#t~mem16=|v_Thread0_P1_#t~mem16_1|, Thread0_P1_#t~mem15=|v_Thread0_P1_#t~mem15_2|, Thread0_P1_#t~mem20=|v_Thread0_P1_#t~mem20_1|, Thread0_P1_#t~ite18=|v_Thread0_P1_#t~ite18_1|, Thread0_P1_#t~ite19=|v_Thread0_P1_#t~ite19_1|, Thread0_P1_#t~ite22=|v_Thread0_P1_#t~ite22_1|, #memory_int=|v_#memory_int_15|, ~#x~0.base=|v_~#x~0.base_12|, Thread0_P1_#t~ite21=|v_Thread0_P1_#t~ite21_1|, Thread0_P1_#t~ite24=|v_Thread0_P1_#t~ite24_1|, Thread0_P1_#t~ite23=|v_Thread0_P1_#t~ite23_1|, Thread0_P1_#t~ite25=|v_Thread0_P1_#t~ite25_3|, Thread0_P1_#t~ite17=|v_Thread0_P1_#t~ite17_1|} AuxVars[] AssignedVars[Thread0_P1_#t~mem20, Thread0_P1_#t~ite18, Thread0_P1_#t~ite19, Thread0_P1_#t~mem16, Thread0_P1_#t~ite22, #memory_int, Thread0_P1_#t~mem15, Thread0_P1_#t~ite21, Thread0_P1_#t~ite24, Thread0_P1_#t~ite23, Thread0_P1_#t~ite25, Thread0_P1_#t~ite17] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [805] L750-->L750-14: Formula: (and (= |v_Thread0_P1_#t~ite30_1| v_~x$w_buff0~0_9) (not (= (mod v_~weak$$choice2~0_6 256) 0))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_9, ~weak$$choice2~0=v_~weak$$choice2~0_6} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_9, ~weak$$choice2~0=v_~weak$$choice2~0_6, Thread0_P1_#t~ite30=|v_Thread0_P1_#t~ite30_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite30] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite30|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [810] L750-14-->L751: Formula: (= v_~x$w_buff0~0_15 |v_Thread0_P1_#t~ite30_2|) InVars {Thread0_P1_#t~ite30=|v_Thread0_P1_#t~ite30_2|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_15, Thread0_P1_#t~ite29=|v_Thread0_P1_#t~ite29_1|, Thread0_P1_#t~ite30=|v_Thread0_P1_#t~ite30_3|, Thread0_P1_#t~ite26=|v_Thread0_P1_#t~ite26_1|, Thread0_P1_#t~ite28=|v_Thread0_P1_#t~ite28_1|, Thread0_P1_#t~ite27=|v_Thread0_P1_#t~ite27_1|} AuxVars[] AssignedVars[~x$w_buff0~0, Thread0_P1_#t~ite29, Thread0_P1_#t~ite30, Thread0_P1_#t~ite26, Thread0_P1_#t~ite28, Thread0_P1_#t~ite27] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [817] L751-->L751-14: Formula: (and (not (= (mod v_~weak$$choice2~0_8 256) 0)) (= |v_Thread0_P1_#t~ite35_1| v_~x$w_buff1~0_6)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_8, ~x$w_buff1~0=v_~x$w_buff1~0_6} OutVars{Thread0_P1_#t~ite35=|v_Thread0_P1_#t~ite35_1|, ~weak$$choice2~0=v_~weak$$choice2~0_8, ~x$w_buff1~0=v_~x$w_buff1~0_6} AuxVars[] AssignedVars[Thread0_P1_#t~ite35] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite35|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [829] L751-14-->L752: Formula: (= v_~x$w_buff1~0_12 |v_Thread0_P1_#t~ite35_2|) InVars {Thread0_P1_#t~ite35=|v_Thread0_P1_#t~ite35_2|} OutVars{Thread0_P1_#t~ite31=|v_Thread0_P1_#t~ite31_1|, ~x$w_buff1~0=v_~x$w_buff1~0_12, Thread0_P1_#t~ite33=|v_Thread0_P1_#t~ite33_1|, Thread0_P1_#t~ite32=|v_Thread0_P1_#t~ite32_1|, Thread0_P1_#t~ite35=|v_Thread0_P1_#t~ite35_3|, Thread0_P1_#t~ite34=|v_Thread0_P1_#t~ite34_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite31, ~x$w_buff1~0, Thread0_P1_#t~ite33, Thread0_P1_#t~ite32, Thread0_P1_#t~ite35, Thread0_P1_#t~ite34] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [839] L752-->L752-14: Formula: (and (not (= (mod v_~weak$$choice2~0_10 256) 0)) (= |v_Thread0_P1_#t~ite40_1| (mod v_~x$w_buff0_used~0_65 256))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_65} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_10, Thread0_P1_#t~ite40=|v_Thread0_P1_#t~ite40_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_65} AuxVars[] AssignedVars[Thread0_P1_#t~ite40] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite40|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [848] L752-14-->L753: Formula: (= v_~x$w_buff0_used~0_74 (ite (= |v_Thread0_P1_#t~ite40_2| 0) 0 1)) InVars {Thread0_P1_#t~ite40=|v_Thread0_P1_#t~ite40_2|} OutVars{Thread0_P1_#t~ite40=|v_Thread0_P1_#t~ite40_3|, Thread0_P1_#t~ite37=|v_Thread0_P1_#t~ite37_1|, Thread0_P1_#t~ite36=|v_Thread0_P1_#t~ite36_1|, Thread0_P1_#t~ite39=|v_Thread0_P1_#t~ite39_1|, Thread0_P1_#t~ite38=|v_Thread0_P1_#t~ite38_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_74} AuxVars[] AssignedVars[Thread0_P1_#t~ite40, Thread0_P1_#t~ite37, Thread0_P1_#t~ite36, Thread0_P1_#t~ite39, Thread0_P1_#t~ite38, ~x$w_buff0_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [855] L753-->L753-14: Formula: (and (not (= (mod v_~weak$$choice2~0_12 256) 0)) (= |v_Thread0_P1_#t~ite45_1| v_~x$w_buff1_used~0_40)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_12, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_40} OutVars{Thread0_P1_#t~ite45=|v_Thread0_P1_#t~ite45_1|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_40, ~weak$$choice2~0=v_~weak$$choice2~0_12} AuxVars[] AssignedVars[Thread0_P1_#t~ite45] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite45|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [863] L753-14-->L754: Formula: (= v_~x$w_buff1_used~0_46 |v_Thread0_P1_#t~ite45_2|) InVars {Thread0_P1_#t~ite45=|v_Thread0_P1_#t~ite45_2|} OutVars{Thread0_P1_#t~ite41=|v_Thread0_P1_#t~ite41_1|, Thread0_P1_#t~ite42=|v_Thread0_P1_#t~ite42_1|, Thread0_P1_#t~ite45=|v_Thread0_P1_#t~ite45_3|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_46, Thread0_P1_#t~ite43=|v_Thread0_P1_#t~ite43_1|, Thread0_P1_#t~ite44=|v_Thread0_P1_#t~ite44_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite41, Thread0_P1_#t~ite42, Thread0_P1_#t~ite45, ~x$w_buff1_used~0, Thread0_P1_#t~ite43, Thread0_P1_#t~ite44] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [870] L754-->L754-14: Formula: (and (= |v_Thread0_P1_#t~ite50_1| v_~x$r_buff0_thd2~0_2) (not (= (mod v_~weak$$choice2~0_1 256) 0))) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_2, ~weak$$choice2~0=v_~weak$$choice2~0_1} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_2, ~weak$$choice2~0=v_~weak$$choice2~0_1, Thread0_P1_#t~ite50=|v_Thread0_P1_#t~ite50_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite50] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite50|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [878] L754-14-->L755: Formula: (= v_~x$r_buff0_thd2~0_10 |v_Thread0_P1_#t~ite50_2|) InVars {Thread0_P1_#t~ite50=|v_Thread0_P1_#t~ite50_2|} OutVars{Thread0_P1_#t~ite50=|v_Thread0_P1_#t~ite50_3|, Thread0_P1_#t~ite46=|v_Thread0_P1_#t~ite46_1|, Thread0_P1_#t~ite49=|v_Thread0_P1_#t~ite49_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_10, Thread0_P1_#t~ite47=|v_Thread0_P1_#t~ite47_1|, Thread0_P1_#t~ite48=|v_Thread0_P1_#t~ite48_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite50, Thread0_P1_#t~ite46, Thread0_P1_#t~ite49, ~x$r_buff0_thd2~0, Thread0_P1_#t~ite47, Thread0_P1_#t~ite48] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [885] L755-->L755-17: Formula: (and (= |v_Thread0_P1_#t~ite56_1| v_~x$r_buff1_thd2~0_6) (not (= 0 (mod v_~weak$$choice2~0_3 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_3, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6} OutVars{Thread0_P1_#t~ite56=|v_Thread0_P1_#t~ite56_1|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6, ~weak$$choice2~0=v_~weak$$choice2~0_3} AuxVars[] AssignedVars[Thread0_P1_#t~ite56] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite56|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [893] L755-17-->L759: Formula: (and (= v_~x$r_buff1_thd2~0_14 |v_Thread0_P1_#t~ite56_2|) (= v_~__unbuffered_p1_EAX$read_delayed_var~0.offset_1 |v_~#x~0.offset_6|) (= v_~__unbuffered_p1_EAX$read_delayed~0_1 1) (= v_~__unbuffered_p1_EAX$read_delayed_var~0.base_1 |v_~#x~0.base_6|) (= (select (select |v_#memory_int_7| |v_~#x~0.base_6|) |v_~#x~0.offset_6|) v_~__unbuffered_p1_EAX~0_1)) InVars {~#x~0.base=|v_~#x~0.base_6|, #memory_int=|v_#memory_int_7|, Thread0_P1_#t~ite56=|v_Thread0_P1_#t~ite56_2|, ~#x~0.offset=|v_~#x~0.offset_6|} OutVars{Thread0_P1_#t~ite52=|v_Thread0_P1_#t~ite52_1|, ~#x~0.offset=|v_~#x~0.offset_6|, ~__unbuffered_p1_EAX$read_delayed~0=v_~__unbuffered_p1_EAX$read_delayed~0_1, Thread0_P1_#t~ite53=|v_Thread0_P1_#t~ite53_1|, Thread0_P1_#t~ite51=|v_Thread0_P1_#t~ite51_1|, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=v_~__unbuffered_p1_EAX$read_delayed_var~0.offset_1, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_14, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, Thread0_P1_#t~mem57=|v_Thread0_P1_#t~mem57_1|, Thread0_P1_#t~ite56=|v_Thread0_P1_#t~ite56_3|, ~#x~0.base=|v_~#x~0.base_6|, #memory_int=|v_#memory_int_7|, ~__unbuffered_p1_EAX$read_delayed_var~0.base=v_~__unbuffered_p1_EAX$read_delayed_var~0.base_1, Thread0_P1_#t~ite54=|v_Thread0_P1_#t~ite54_1|, Thread0_P1_#t~ite55=|v_Thread0_P1_#t~ite55_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite52, ~__unbuffered_p1_EAX~0, ~__unbuffered_p1_EAX$read_delayed~0, Thread0_P1_#t~ite53, Thread0_P1_#t~mem57, Thread0_P1_#t~ite51, Thread0_P1_#t~ite56, ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset, ~x$r_buff1_thd2~0, Thread0_P1_#t~ite54, Thread0_P1_#t~ite55] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [900] L759-->L759-2: Formula: (and (not (= (mod v_~x$flush_delayed~0_2 256) 0)) (= |v_Thread0_P1_#t~ite59_1| v_~x$mem_tmp~0_2)) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_2, ~x$mem_tmp~0=v_~x$mem_tmp~0_2} OutVars{~x$mem_tmp~0=v_~x$mem_tmp~0_2, ~x$flush_delayed~0=v_~x$flush_delayed~0_2, Thread0_P1_#t~ite59=|v_Thread0_P1_#t~ite59_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite59] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite59|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [908] L759-2-->L766: Formula: (and (= |v_#memory_int_9| (store |v_#memory_int_10| |v_~#x~0.base_8| (store (select |v_#memory_int_10| |v_~#x~0.base_8|) |v_~#x~0.offset_8| |v_Thread0_P1_#t~ite59_3|))) (= v_~x$flush_delayed~0_4 0) (= v_~y~0_2 1)) InVars {#memory_int=|v_#memory_int_10|, ~#x~0.base=|v_~#x~0.base_8|, ~#x~0.offset=|v_~#x~0.offset_8|, Thread0_P1_#t~ite59=|v_Thread0_P1_#t~ite59_3|} OutVars{Thread0_P1_#t~mem58=|v_Thread0_P1_#t~mem58_2|, ~x$flush_delayed~0=v_~x$flush_delayed~0_4, ~#x~0.offset=|v_~#x~0.offset_8|, #memory_int=|v_#memory_int_9|, ~#x~0.base=|v_~#x~0.base_8|, ~y~0=v_~y~0_2, Thread0_P1_#t~ite59=|v_Thread0_P1_#t~ite59_4|} AuxVars[] AssignedVars[Thread0_P1_#t~mem58, ~x$flush_delayed~0, #memory_int, ~y~0, Thread0_P1_#t~ite59] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [914] L766-->L766-2: Formula: (or (= 0 (mod v_~x$r_buff0_thd2~0_22 256)) (= 0 (mod v_~x$w_buff0_used~0_37 256))) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_22, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_37} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_22, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_37} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [772] P0ENTRY-->L4: Formula: (and (= v_Thread1_P0_~arg.base_1 |v_Thread1_P0_#in~arg.base_1|) (= v_Thread1_P0_~arg.offset_1 |v_Thread1_P0_#in~arg.offset_1|) (= v_~x$w_buff0~0_1 1) (= v_Thread1_P0___VERIFIER_assert_~expression_1 |v_Thread1_P0___VERIFIER_assert_#in~expression_1|) (= v_~x$w_buff1~0_1 v_~x$w_buff0~0_2) (= v_~x$w_buff1_used~0_1 v_~x$w_buff0_used~0_2) (= v_~x$w_buff0_used~0_1 1) (= v_~__unbuffered_p0_EAX~0_1 v_~y~0_1) (= |v_Thread1_P0___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= 0 (mod v_~x$w_buff1_used~0_1 256))) (not (= (mod v_~x$w_buff0_used~0_1 256) 0)))) 1 0))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_2, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_1|, Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_1|, ~y~0=v_~y~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_2} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_1, Thread1_P0___VERIFIER_assert_~expression=v_Thread1_P0___VERIFIER_assert_~expression_1, Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_1|, Thread1_P0_~arg.offset=v_Thread1_P0_~arg.offset_1, ~x$w_buff1~0=v_~x$w_buff1~0_1, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_1|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_1, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_1, Thread1_P0___VERIFIER_assert_#in~expression=|v_Thread1_P0___VERIFIER_assert_#in~expression_1|, Thread1_P0_~arg.base=v_Thread1_P0_~arg.base_1, ~y~0=v_~y~0_1} AuxVars[] AssignedVars[~x$w_buff0~0, Thread1_P0___VERIFIER_assert_~expression, ~__unbuffered_p0_EAX~0, Thread1_P0_~arg.offset, Thread1_P0___VERIFIER_assert_#in~expression, ~x$w_buff1~0, Thread1_P0_~arg.base, ~x$w_buff1_used~0, ~x$w_buff0_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [774] L4-->L4-3: Formula: (not (= 0 v_Thread1_P0___VERIFIER_assert_~expression_3)) InVars {Thread1_P0___VERIFIER_assert_~expression=v_Thread1_P0___VERIFIER_assert_~expression_3} OutVars{Thread1_P0___VERIFIER_assert_~expression=v_Thread1_P0___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [921] L766-2-->L766-4: Formula: (and (= |v_Thread0_P1_#t~ite61_3| |v_Thread0_P1_#t~mem60_2|) (or (= 0 (mod v_~x$r_buff1_thd2~0_18 256)) (= (mod v_~x$w_buff1_used~0_21 256) 0)) (= (select (select |v_#memory_int_11| |v_~#x~0.base_9|) |v_~#x~0.offset_9|) |v_Thread0_P1_#t~mem60_2|)) InVars {~#x~0.base=|v_~#x~0.base_9|, #memory_int=|v_#memory_int_11|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_21, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_18, ~#x~0.offset=|v_~#x~0.offset_9|} OutVars{~#x~0.offset=|v_~#x~0.offset_9|, Thread0_P1_#t~ite61=|v_Thread0_P1_#t~ite61_3|, ~#x~0.base=|v_~#x~0.base_9|, #memory_int=|v_#memory_int_11|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_21, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_18, Thread0_P1_#t~mem60=|v_Thread0_P1_#t~mem60_2|} AuxVars[] AssignedVars[Thread0_P1_#t~ite61, Thread0_P1_#t~mem60] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite61|=0, |Thread0_P1_#t~mem60|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [777] L4-3-->L730: Formula: (and (= v_~x$r_buff0_thd1~0_1 1) (= v_~x$r_buff1_thd0~0_1 v_~x$r_buff0_thd0~0_1) (= v_~x$r_buff1_thd2~0_1 v_~x$r_buff0_thd2~0_1) (= v_~x$r_buff1_thd1~0_1 v_~x$r_buff0_thd1~0_2)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_2, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_1, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_1, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_1, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_1} AuxVars[] AssignedVars[~x$r_buff0_thd1~0, ~x$r_buff1_thd2~0, ~x$r_buff1_thd1~0, ~x$r_buff1_thd0~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite61|=0, |Thread0_P1_#t~mem60|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [778] L730-->L730-5: Formula: (and (not (= 0 (mod v_~x$w_buff0_used~0_3 256))) (= |v_Thread1_P0_#t~ite5_1| v_~x$w_buff0~0_3) (not (= 0 (mod v_~x$r_buff0_thd1~0_3 256)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_3, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_3, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_3, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_3, Thread1_P0_#t~ite5=|v_Thread1_P0_#t~ite5_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} AuxVars[] AssignedVars[Thread1_P0_#t~ite5] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite61|=0, |Thread0_P1_#t~mem60|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite5|=1, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [926] L766-4-->L766-5: Formula: (= |v_Thread0_P1_#t~ite62_4| |v_Thread0_P1_#t~ite61_4|) InVars {Thread0_P1_#t~ite61=|v_Thread0_P1_#t~ite61_4|} OutVars{Thread0_P1_#t~ite61=|v_Thread0_P1_#t~ite61_4|, Thread0_P1_#t~ite62=|v_Thread0_P1_#t~ite62_4|} AuxVars[] AssignedVars[Thread0_P1_#t~ite62] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite61|=0, |Thread0_P1_#t~ite62|=0, |Thread0_P1_#t~mem60|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite5|=1, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [919] L766-5-->L767: Formula: (= |v_#memory_int_12| (store |v_#memory_int_13| |v_~#x~0.base_10| (store (select |v_#memory_int_13| |v_~#x~0.base_10|) |v_~#x~0.offset_10| |v_Thread0_P1_#t~ite62_2|))) InVars {#memory_int=|v_#memory_int_13|, ~#x~0.base=|v_~#x~0.base_10|, ~#x~0.offset=|v_~#x~0.offset_10|, Thread0_P1_#t~ite62=|v_Thread0_P1_#t~ite62_2|} OutVars{~#x~0.offset=|v_~#x~0.offset_10|, Thread0_P1_#t~ite61=|v_Thread0_P1_#t~ite61_1|, Thread0_P1_#t~ite62=|v_Thread0_P1_#t~ite62_3|, #memory_int=|v_#memory_int_12|, ~#x~0.base=|v_~#x~0.base_10|, Thread0_P1_#t~mem60=|v_Thread0_P1_#t~mem60_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite61, Thread0_P1_#t~ite62, #memory_int, Thread0_P1_#t~mem60] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite5|=1, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [780] L730-5-->L731: Formula: (= |v_#memory_int_2| (store |v_#memory_int_3| |v_~#x~0.base_2| (store (select |v_#memory_int_3| |v_~#x~0.base_2|) |v_~#x~0.offset_2| |v_Thread1_P0_#t~ite5_2|))) InVars {#memory_int=|v_#memory_int_3|, ~#x~0.base=|v_~#x~0.base_2|, ~#x~0.offset=|v_~#x~0.offset_2|, Thread1_P0_#t~ite5=|v_Thread1_P0_#t~ite5_2|} OutVars{Thread1_P0_#t~mem3=|v_Thread1_P0_#t~mem3_1|, ~#x~0.offset=|v_~#x~0.offset_2|, #memory_int=|v_#memory_int_2|, ~#x~0.base=|v_~#x~0.base_2|, Thread1_P0_#t~ite4=|v_Thread1_P0_#t~ite4_1|, Thread1_P0_#t~ite5=|v_Thread1_P0_#t~ite5_3|} AuxVars[] AssignedVars[Thread1_P0_#t~mem3, #memory_int, Thread1_P0_#t~ite4, Thread1_P0_#t~ite5] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [925] L767-->L767-2: Formula: (and (or (= 0 (mod v_~x$w_buff0_used~0_41 256)) (= 0 (mod v_~x$r_buff0_thd2~0_26 256))) (= |v_Thread0_P1_#t~ite63_2| v_~x$w_buff0_used~0_41)) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_26, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_41} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_26, Thread0_P1_#t~ite63=|v_Thread0_P1_#t~ite63_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_41} AuxVars[] AssignedVars[Thread0_P1_#t~ite63] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite63|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [928] L767-2-->L768: Formula: (= v_~x$w_buff0_used~0_42 |v_Thread0_P1_#t~ite63_3|) InVars {Thread0_P1_#t~ite63=|v_Thread0_P1_#t~ite63_3|} OutVars{Thread0_P1_#t~ite63=|v_Thread0_P1_#t~ite63_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_42} AuxVars[] AssignedVars[Thread0_P1_#t~ite63, ~x$w_buff0_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [930] L768-->L768-2: Formula: (and (or (= 0 (mod v_~x$r_buff0_thd2~0_28 256)) (= (mod v_~x$w_buff0_used~0_44 256) 0)) (= |v_Thread0_P1_#t~ite64_2| v_~x$w_buff1_used~0_24) (or (= (mod v_~x$r_buff1_thd2~0_21 256) 0) (= (mod v_~x$w_buff1_used~0_24 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_24, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_21, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_28, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_44} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_24, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_21, Thread0_P1_#t~ite64=|v_Thread0_P1_#t~ite64_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_28, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_44} AuxVars[] AssignedVars[Thread0_P1_#t~ite64] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite64|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [931] L768-2-->L769: Formula: (= v_~x$w_buff1_used~0_25 |v_Thread0_P1_#t~ite64_3|) InVars {Thread0_P1_#t~ite64=|v_Thread0_P1_#t~ite64_3|} OutVars{Thread0_P1_#t~ite64=|v_Thread0_P1_#t~ite64_4|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_25} AuxVars[] AssignedVars[Thread0_P1_#t~ite64, ~x$w_buff1_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [933] L769-->L769-2: Formula: (and (or (= (mod v_~x$r_buff0_thd2~0_30 256) 0) (= 0 (mod v_~x$w_buff0_used~0_46 256))) (= |v_Thread0_P1_#t~ite65_2| v_~x$r_buff0_thd2~0_30)) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_30, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_46} OutVars{Thread0_P1_#t~ite65=|v_Thread0_P1_#t~ite65_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_30, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_46} AuxVars[] AssignedVars[Thread0_P1_#t~ite65] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite65|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [934] L769-2-->L770: Formula: (= v_~x$r_buff0_thd2~0_31 |v_Thread0_P1_#t~ite65_3|) InVars {Thread0_P1_#t~ite65=|v_Thread0_P1_#t~ite65_3|} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_31, Thread0_P1_#t~ite65=|v_Thread0_P1_#t~ite65_4|} AuxVars[] AssignedVars[Thread0_P1_#t~ite65, ~x$r_buff0_thd2~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [936] L770-->L770-2: Formula: (and (= |v_Thread0_P1_#t~ite66_2| v_~x$r_buff1_thd2~0_23) (or (= 0 (mod v_~x$w_buff1_used~0_27 256)) (= (mod v_~x$r_buff1_thd2~0_23 256) 0)) (or (= (mod v_~x$w_buff0_used~0_49 256) 0) (= 0 (mod v_~x$r_buff0_thd2~0_33 256)))) InVars {~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_23, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_27, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_33, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_49} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_23, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_27, Thread0_P1_#t~ite66=|v_Thread0_P1_#t~ite66_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_33, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_49} AuxVars[] AssignedVars[Thread0_P1_#t~ite66] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite66|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [937] L770-2-->L775: Formula: (and (= v_~x$r_buff1_thd2~0_24 |v_Thread0_P1_#t~ite66_3|) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {Thread0_P1_#t~ite66=|v_Thread0_P1_#t~ite66_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_24, Thread0_P1_#t~ite66=|v_Thread0_P1_#t~ite66_4|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3} AuxVars[] AssignedVars[~x$r_buff1_thd2~0, Thread0_P1_#t~ite66, ~__unbuffered_cnt~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [783] L731-->L731-2: Formula: (and (not (= 0 (mod v_~x$r_buff0_thd1~0_5 256))) (not (= (mod v_~x$w_buff0_used~0_5 256) 0)) (= |v_Thread1_P0_#t~ite6_1| 0)) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} OutVars{~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_5, Thread1_P0_#t~ite6=|v_Thread1_P0_#t~ite6_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} AuxVars[] AssignedVars[Thread1_P0_#t~ite6] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite6|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [786] L731-2-->L732: Formula: (= v_~x$w_buff0_used~0_7 |v_Thread1_P0_#t~ite6_3|) InVars {Thread1_P0_#t~ite6=|v_Thread1_P0_#t~ite6_3|} OutVars{Thread1_P0_#t~ite6=|v_Thread1_P0_#t~ite6_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_7} AuxVars[] AssignedVars[Thread1_P0_#t~ite6, ~x$w_buff0_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [788] L732-->L732-2: Formula: (and (or (= 0 (mod v_~x$r_buff1_thd1~0_5 256)) (= 0 (mod v_~x$w_buff1_used~0_5 256))) (= |v_Thread1_P0_#t~ite7_2| v_~x$w_buff1_used~0_5) (or (= (mod v_~x$w_buff0_used~0_9 256) 0) (= (mod v_~x$r_buff0_thd1~0_8 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_5, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_9} OutVars{Thread1_P0_#t~ite7=|v_Thread1_P0_#t~ite7_2|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_5, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_9} AuxVars[] AssignedVars[Thread1_P0_#t~ite7] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite7|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [789] L732-2-->L733: Formula: (= v_~x$w_buff1_used~0_6 |v_Thread1_P0_#t~ite7_3|) InVars {Thread1_P0_#t~ite7=|v_Thread1_P0_#t~ite7_3|} OutVars{Thread1_P0_#t~ite7=|v_Thread1_P0_#t~ite7_4|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_6} AuxVars[] AssignedVars[Thread1_P0_#t~ite7, ~x$w_buff1_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [791] L733-->L733-2: Formula: (and (= |v_Thread1_P0_#t~ite8_2| v_~x$r_buff0_thd1~0_10) (or (= (mod v_~x$w_buff0_used~0_11 256) 0) (= (mod v_~x$r_buff0_thd1~0_10 256) 0))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_11} OutVars{Thread1_P0_#t~ite8=|v_Thread1_P0_#t~ite8_2|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_11} AuxVars[] AssignedVars[Thread1_P0_#t~ite8] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite8|=1, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [792] L733-2-->L734: Formula: (= v_~x$r_buff0_thd1~0_11 |v_Thread1_P0_#t~ite8_3|) InVars {Thread1_P0_#t~ite8=|v_Thread1_P0_#t~ite8_3|} OutVars{Thread1_P0_#t~ite8=|v_Thread1_P0_#t~ite8_4|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_11} AuxVars[] AssignedVars[~x$r_buff0_thd1~0, Thread1_P0_#t~ite8] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [794] L734-->L734-2: Formula: (and (or (= 0 (mod v_~x$w_buff0_used~0_13 256)) (= (mod v_~x$r_buff0_thd1~0_13 256) 0)) (or (= (mod v_~x$r_buff1_thd1~0_7 256) 0) (= 0 (mod v_~x$w_buff1_used~0_8 256))) (= |v_Thread1_P0_#t~ite9_2| v_~x$r_buff1_thd1~0_7)) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_8, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_13, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_13} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_8, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_13, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, Thread1_P0_#t~ite9=|v_Thread1_P0_#t~ite9_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_13} AuxVars[] AssignedVars[Thread1_P0_#t~ite9] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite9|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [795] L734-2-->L739: Formula: (and (= v_~x$r_buff1_thd1~0_8 |v_Thread1_P0_#t~ite9_3|) (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1))) InVars {Thread1_P0_#t~ite9=|v_Thread1_P0_#t~ite9_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_8, Thread1_P0_#t~ite9=|v_Thread1_P0_#t~ite9_4|} AuxVars[] AssignedVars[~__unbuffered_cnt~0, ~x$r_buff1_thd1~0, Thread1_P0_#t~ite9] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [557] L791-1-->L795: Formula: (= v_~main$tmp_guard0~0_2 (ite (= (ite (= v_~__unbuffered_cnt~0_6 2) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_2, ULTIMATE.start_main_#t~nondet69=|v_ULTIMATE.start_main_#t~nondet69_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet69, ~main$tmp_guard0~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [751] L795-->L797: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_3 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [523] L797-->L797-2: Formula: (or (= 0 (mod v_~x$w_buff0_used~0_85 256)) (= (mod v_~x$r_buff0_thd0~0_4 256) 0)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_85} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_85} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [530] L797-2-->L797-4: Formula: (and (= |v_ULTIMATE.start_main_#t~mem70_2| (select (select |v_#memory_int_22| |v_~#x~0.base_15|) |v_~#x~0.offset_15|)) (= |v_ULTIMATE.start_main_#t~ite71_3| |v_ULTIMATE.start_main_#t~mem70_2|) (or (= 0 (mod v_~x$r_buff1_thd0~0_4 256)) (= (mod v_~x$w_buff1_used~0_49 256) 0))) InVars {~#x~0.base=|v_~#x~0.base_15|, #memory_int=|v_#memory_int_22|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_49, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_4, ~#x~0.offset=|v_~#x~0.offset_15|} OutVars{ULTIMATE.start_main_#t~ite71=|v_ULTIMATE.start_main_#t~ite71_3|, ~#x~0.offset=|v_~#x~0.offset_15|, ~#x~0.base=|v_~#x~0.base_15|, #memory_int=|v_#memory_int_22|, ULTIMATE.start_main_#t~mem70=|v_ULTIMATE.start_main_#t~mem70_2|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_49, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_4} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite71, ULTIMATE.start_main_#t~mem70] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite71|=1, |ULTIMATE.start_main_#t~mem70|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [514] L797-4-->L797-5: Formula: (= |v_ULTIMATE.start_main_#t~ite72_3| |v_ULTIMATE.start_main_#t~ite71_4|) InVars {ULTIMATE.start_main_#t~ite71=|v_ULTIMATE.start_main_#t~ite71_4|} OutVars{ULTIMATE.start_main_#t~ite71=|v_ULTIMATE.start_main_#t~ite71_4|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite72] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite71|=1, |ULTIMATE.start_main_#t~ite72|=1, |ULTIMATE.start_main_#t~mem70|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [518] L797-5-->L798: Formula: (= (store |v_#memory_int_24| |v_~#x~0.base_16| (store (select |v_#memory_int_24| |v_~#x~0.base_16|) |v_~#x~0.offset_16| |v_ULTIMATE.start_main_#t~ite72_5|)) |v_#memory_int_23|) InVars {#memory_int=|v_#memory_int_24|, ~#x~0.base=|v_~#x~0.base_16|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_5|, ~#x~0.offset=|v_~#x~0.offset_16|} OutVars{ULTIMATE.start_main_#t~ite71=|v_ULTIMATE.start_main_#t~ite71_5|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_4|, ~#x~0.offset=|v_~#x~0.offset_16|, #memory_int=|v_#memory_int_23|, ~#x~0.base=|v_~#x~0.base_16|, ULTIMATE.start_main_#t~mem70=|v_ULTIMATE.start_main_#t~mem70_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite71, ULTIMATE.start_main_#t~ite72, #memory_int, ULTIMATE.start_main_#t~mem70] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [595] L798-->L798-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite73_3| v_~x$w_buff0_used~0_87) (or (= (mod v_~x$r_buff0_thd0~0_6 256) 0) (= (mod v_~x$w_buff0_used~0_87 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_87} OutVars{ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_3|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_87} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite73] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite73|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [599] L798-2-->L799: Formula: (= v_~x$w_buff0_used~0_88 |v_ULTIMATE.start_main_#t~ite73_5|) InVars {ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_5|} OutVars{ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_88} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite73, ~x$w_buff0_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [711] L799-->L799-2: Formula: (and (or (= 0 (mod v_~x$w_buff1_used~0_51 256)) (= (mod v_~x$r_buff1_thd0~0_6 256) 0)) (= |v_ULTIMATE.start_main_#t~ite74_3| v_~x$w_buff1_used~0_51) (or (= (mod v_~x$r_buff0_thd0~0_8 256) 0) (= (mod v_~x$w_buff0_used~0_90 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_8, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_51, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_90} OutVars{ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_3|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_8, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_51, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_90} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite74] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite74|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [703] L799-2-->L800: Formula: (= v_~x$w_buff1_used~0_52 |v_ULTIMATE.start_main_#t~ite74_5|) InVars {ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_5|} OutVars{ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_4|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_52} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite74, ~x$w_buff1_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [659] L800-->L800-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_92 256) 0) (= 0 (mod v_~x$r_buff0_thd0~0_10 256))) (= |v_ULTIMATE.start_main_#t~ite75_3| v_~x$r_buff0_thd0~0_10)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_92} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_10, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_92} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite75] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite75|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [763] L800-2-->L801: Formula: (= v_~x$r_buff0_thd0~0_11 |v_ULTIMATE.start_main_#t~ite75_5|) InVars {ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_5|} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_11, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_4|} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite75] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [737] L801-->L801-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite76_3| v_~x$r_buff1_thd0~0_8) (or (= 0 (mod v_~x$r_buff0_thd0~0_13 256)) (= 0 (mod v_~x$w_buff0_used~0_94 256))) (or (= 0 (mod v_~x$r_buff1_thd0~0_8 256)) (= 0 (mod v_~x$w_buff1_used~0_54 256)))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_13, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_54, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_94} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_13, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_54, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_8, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_94} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite76] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite76|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [741] L801-2-->L805: Formula: (and (= v_~x$r_buff1_thd0~0_9 |v_ULTIMATE.start_main_#t~ite76_5|) (= v_~weak$$choice1~0_6 (ite (= (+ |v_ULTIMATE.start_main_#t~nondet77.base_3| |v_ULTIMATE.start_main_#t~nondet77.offset_3|) 0) 0 1))) InVars {ULTIMATE.start_main_#t~nondet77.offset=|v_ULTIMATE.start_main_#t~nondet77.offset_3|, ULTIMATE.start_main_#t~nondet77.base=|v_ULTIMATE.start_main_#t~nondet77.base_3|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_5|} OutVars{~weak$$choice1~0=v_~weak$$choice1~0_6, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_9, ULTIMATE.start_main_#t~nondet77.offset=|v_ULTIMATE.start_main_#t~nondet77.offset_2|, ULTIMATE.start_main_#t~nondet77.base=|v_ULTIMATE.start_main_#t~nondet77.base_2|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_4|} AuxVars[] AssignedVars[~weak$$choice1~0, ULTIMATE.start_main_#t~nondet77.offset, ~x$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet77.base, ULTIMATE.start_main_#t~ite76] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [689] L805-->L805-1: Formula: (not (= (mod v_~__unbuffered_p1_EAX$read_delayed~0_3 256) 0)) InVars {~__unbuffered_p1_EAX$read_delayed~0=v_~__unbuffered_p1_EAX$read_delayed~0_3} OutVars{~__unbuffered_p1_EAX$read_delayed~0=v_~__unbuffered_p1_EAX$read_delayed~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [671] L805-1-->L805-3: Formula: (and (= |v_ULTIMATE.start_main_#t~ite79_2| |v_ULTIMATE.start_main_#t~mem78_2|) (not (= 0 (mod v_~weak$$choice1~0_7 256))) (= |v_ULTIMATE.start_main_#t~mem78_2| (select (select |v_#memory_int_25| v_~__unbuffered_p1_EAX$read_delayed_var~0.base_3) v_~__unbuffered_p1_EAX$read_delayed_var~0.offset_3))) InVars {~__unbuffered_p1_EAX$read_delayed_var~0.base=v_~__unbuffered_p1_EAX$read_delayed_var~0.base_3, #memory_int=|v_#memory_int_25|, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=v_~__unbuffered_p1_EAX$read_delayed_var~0.offset_3, ~weak$$choice1~0=v_~weak$$choice1~0_7} OutVars{ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_2|, ~weak$$choice1~0=v_~weak$$choice1~0_7, ~__unbuffered_p1_EAX$read_delayed_var~0.base=v_~__unbuffered_p1_EAX$read_delayed_var~0.base_3, #memory_int=|v_#memory_int_25|, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=v_~__unbuffered_p1_EAX$read_delayed_var~0.offset_3, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem78, ULTIMATE.start_main_#t~ite79] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite79|=1, |ULTIMATE.start_main_#t~mem78|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [677] L805-3-->L805-5: Formula: (= |v_ULTIMATE.start_main_#t~ite80_2| |v_ULTIMATE.start_main_#t~ite79_4|) InVars {ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_4|} OutVars{ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_2|, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite80] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite79|=1, |ULTIMATE.start_main_#t~ite80|=1, |ULTIMATE.start_main_#t~mem78|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [683] L805-5-->L808: Formula: (and (= v_~main$tmp_guard1~0_2 (ite (= 0 (ite (not (and (= 1 v_~__unbuffered_p1_EAX~0_5) (= v_~__unbuffered_p0_EAX~0_3 1))) 1 0)) 0 1)) (= v_~__unbuffered_p1_EAX~0_5 |v_ULTIMATE.start_main_#t~ite80_5|)) InVars {ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_5|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_3} OutVars{ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_3|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_3, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_5, ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_4|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_2, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem78, ~__unbuffered_p1_EAX~0, ULTIMATE.start_main_#t~ite80, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite79] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [521] L808-->L808-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_3 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [526] L808-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [551] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [549] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [545] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 SUMMARY for call ~#x~0.base, ~#x~0.offset := #Ultimate.alloc(4); srcloc: L693 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 SUMMARY for call write~init~int(0, ~#x~0.base, ~#x~0.offset, 4); srcloc: L693-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 ~weak$$choice1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68, main_#t~nondet69, main_#t~ite72, main_#t~ite71, main_#t~mem70, main_#t~ite73, main_#t~ite74, main_#t~ite75, main_#t~ite76, main_#t~nondet77.base, main_#t~nondet77.offset, main_#t~ite80, main_#t~ite79, main_#t~mem78, main_~#t2669~0.base, main_~#t2669~0.offset, main_~#t2670~0.base, main_~#t2670~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t2669~0.base, main_~#t2669~0.offset := #Ultimate.alloc(4); srcloc: L788 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t2669~0.base, main_~#t2669~0.offset, 4); srcloc: L788-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t2670~0.base, main_~#t2670~0.offset := #Ultimate.alloc(4); srcloc: L790 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t2670~0.base, main_~#t2670~0.offset, 4); srcloc: L790-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~weak$$choice0~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~weak$$choice2~0 := (if 0 == #t~nondet12.base + #t~nondet12.offset then 0 else 1);havoc #t~nondet12.base, #t~nondet12.offset;~x$flush_delayed~0 := ~weak$$choice2~0;call #t~mem13 := read~int(~#x~0.base, ~#x~0.offset, 4);~x$mem_tmp~0 := #t~mem13;havoc #t~mem13;~weak$$choice1~0 := (if 0 == #t~nondet14.base + #t~nondet14.offset then 0 else 1);havoc #t~nondet14.base, #t~nondet14.offset; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 == ~x$w_buff0_used~0 % 256;call #t~mem15 := read~int(~#x~0.base, ~#x~0.offset, 4);#t~ite25 := #t~mem15; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |P1_#t~mem15|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 call write~int(#t~ite25, ~#x~0.base, ~#x~0.offset, 4);havoc #t~ite25;havoc #t~ite23;havoc #t~ite22;havoc #t~ite17;havoc #t~mem15;havoc #t~ite19;havoc #t~ite18;havoc #t~mem16;havoc #t~ite21;havoc #t~ite24;havoc #t~mem20; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite30 := ~x$w_buff0~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite30|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$w_buff0~0 := #t~ite30;havoc #t~ite29;havoc #t~ite30;havoc #t~ite28;havoc #t~ite27;havoc #t~ite26; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite35 := ~x$w_buff1~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$w_buff1~0 := #t~ite35;havoc #t~ite32;havoc #t~ite31;havoc #t~ite33;havoc #t~ite34;havoc #t~ite35; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite40 := ~x$w_buff0_used~0 % 256; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite40|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1);havoc #t~ite37;havoc #t~ite36;havoc #t~ite40;havoc #t~ite39;havoc #t~ite38; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite45 := ~x$w_buff1_used~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite45|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$w_buff1_used~0 := #t~ite45;havoc #t~ite41;havoc #t~ite43;havoc #t~ite45;havoc #t~ite42;havoc #t~ite44; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite50 := ~x$r_buff0_thd2~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite50|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$r_buff0_thd2~0 := #t~ite50;havoc #t~ite46;havoc #t~ite49;havoc #t~ite48;havoc #t~ite47;havoc #t~ite50; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite56 := ~x$r_buff1_thd2~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite56|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$r_buff1_thd2~0 := #t~ite56;havoc #t~ite53;havoc #t~ite51;havoc #t~ite55;havoc #t~ite52;havoc #t~ite56;havoc #t~ite54;~__unbuffered_p1_EAX$read_delayed~0 := 1;~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := ~#x~0.base, ~#x~0.offset;call #t~mem57 := read~int(~#x~0.base, ~#x~0.offset, 4);~__unbuffered_p1_EAX~0 := #t~mem57;havoc #t~mem57; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~x$flush_delayed~0 % 256;#t~ite59 := ~x$mem_tmp~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite59|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 call write~int(#t~ite59, ~#x~0.base, ~#x~0.offset, 4);havoc #t~ite59;havoc #t~mem58;~x$flush_delayed~0 := 0;~y~0 := 1; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~__unbuffered_p0_EAX~0 := ~y~0;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 1;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256);call #t~mem60 := read~int(~#x~0.base, ~#x~0.offset, 4);#t~ite61 := #t~mem60; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite61|=0, |P1_#t~mem60|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd1~0 := 1; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite61|=0, |P1_#t~mem60|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite5 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite61|=0, |P1_#t~mem60|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 #t~ite62 := #t~ite61; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite61|=0, |P1_#t~ite62|=0, |P1_#t~mem60|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 call write~int(#t~ite62, ~#x~0.base, ~#x~0.offset, 4);havoc #t~ite62;havoc #t~ite61;havoc #t~mem60; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 call write~int(#t~ite5, ~#x~0.base, ~#x~0.offset, 4);havoc #t~ite4;havoc #t~ite5;havoc #t~mem3; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite63 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite63|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 ~x$w_buff0_used~0 := #t~ite63;havoc #t~ite63; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite64 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite64|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 ~x$w_buff1_used~0 := #t~ite64;havoc #t~ite64; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite65 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite65|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 ~x$r_buff0_thd2~0 := #t~ite65;havoc #t~ite65; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite66 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite66|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 ~x$r_buff1_thd2~0 := #t~ite66;havoc #t~ite66;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite6 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$w_buff0_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite7 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$w_buff1_used~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite8 := ~x$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$r_buff0_thd1~0 := #t~ite8;havoc #t~ite8; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite9 := ~x$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite9|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$r_buff1_thd1~0 := #t~ite9;havoc #t~ite9;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 havoc main_#t~nondet69;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);call main_#t~mem70 := read~int(~#x~0.base, ~#x~0.offset, 4);main_#t~ite71 := main_#t~mem70; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite71|=1, |ULTIMATE.start_main_#t~mem70|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 main_#t~ite72 := main_#t~ite71; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite71|=1, |ULTIMATE.start_main_#t~ite72|=1, |ULTIMATE.start_main_#t~mem70|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 call write~int(main_#t~ite72, ~#x~0.base, ~#x~0.offset, 4);havoc main_#t~ite71;havoc main_#t~ite72;havoc main_#t~mem70; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite73 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite73|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~x$w_buff0_used~0 := main_#t~ite73;havoc main_#t~ite73; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite74 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite74|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~x$w_buff1_used~0 := main_#t~ite74;havoc main_#t~ite74; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite75 := ~x$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite75|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite75;havoc main_#t~ite75; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite76 := ~x$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite76|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite76;havoc main_#t~ite76;~weak$$choice1~0 := (if 0 == main_#t~nondet77.base + main_#t~nondet77.offset then 0 else 1);havoc main_#t~nondet77.base, main_#t~nondet77.offset; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume 0 != ~weak$$choice1~0 % 256;call main_#t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset, 4);main_#t~ite79 := main_#t~mem78; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite79|=1, |ULTIMATE.start_main_#t~mem78|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 main_#t~ite80 := main_#t~ite79; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite79|=1, |ULTIMATE.start_main_#t~ite80|=1, |ULTIMATE.start_main_#t~mem78|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~__unbuffered_p1_EAX~0 := main_#t~ite80;havoc main_#t~ite80;havoc main_#t~mem78;havoc main_#t~ite79;~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 SUMMARY for call ~#x~0.base, ~#x~0.offset := #Ultimate.alloc(4); srcloc: L693 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 SUMMARY for call write~init~int(0, ~#x~0.base, ~#x~0.offset, 4); srcloc: L693-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 ~weak$$choice1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68, main_#t~nondet69, main_#t~ite72, main_#t~ite71, main_#t~mem70, main_#t~ite73, main_#t~ite74, main_#t~ite75, main_#t~ite76, main_#t~nondet77.base, main_#t~nondet77.offset, main_#t~ite80, main_#t~ite79, main_#t~mem78, main_~#t2669~0.base, main_~#t2669~0.offset, main_~#t2670~0.base, main_~#t2670~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t2669~0.base, main_~#t2669~0.offset := #Ultimate.alloc(4); srcloc: L788 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t2669~0.base, main_~#t2669~0.offset, 4); srcloc: L788-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t2670~0.base, main_~#t2670~0.offset := #Ultimate.alloc(4); srcloc: L790 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t2670~0.base, main_~#t2670~0.offset, 4); srcloc: L790-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~weak$$choice0~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~weak$$choice2~0 := (if 0 == #t~nondet12.base + #t~nondet12.offset then 0 else 1);havoc #t~nondet12.base, #t~nondet12.offset;~x$flush_delayed~0 := ~weak$$choice2~0;call #t~mem13 := read~int(~#x~0.base, ~#x~0.offset, 4);~x$mem_tmp~0 := #t~mem13;havoc #t~mem13;~weak$$choice1~0 := (if 0 == #t~nondet14.base + #t~nondet14.offset then 0 else 1);havoc #t~nondet14.base, #t~nondet14.offset; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 == ~x$w_buff0_used~0 % 256;call #t~mem15 := read~int(~#x~0.base, ~#x~0.offset, 4);#t~ite25 := #t~mem15; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |P1_#t~mem15|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 call write~int(#t~ite25, ~#x~0.base, ~#x~0.offset, 4);havoc #t~ite25;havoc #t~ite23;havoc #t~ite22;havoc #t~ite17;havoc #t~mem15;havoc #t~ite19;havoc #t~ite18;havoc #t~mem16;havoc #t~ite21;havoc #t~ite24;havoc #t~mem20; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite30 := ~x$w_buff0~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite30|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$w_buff0~0 := #t~ite30;havoc #t~ite29;havoc #t~ite30;havoc #t~ite28;havoc #t~ite27;havoc #t~ite26; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite35 := ~x$w_buff1~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$w_buff1~0 := #t~ite35;havoc #t~ite32;havoc #t~ite31;havoc #t~ite33;havoc #t~ite34;havoc #t~ite35; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite40 := ~x$w_buff0_used~0 % 256; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite40|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1);havoc #t~ite37;havoc #t~ite36;havoc #t~ite40;havoc #t~ite39;havoc #t~ite38; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite45 := ~x$w_buff1_used~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite45|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$w_buff1_used~0 := #t~ite45;havoc #t~ite41;havoc #t~ite43;havoc #t~ite45;havoc #t~ite42;havoc #t~ite44; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite50 := ~x$r_buff0_thd2~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite50|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$r_buff0_thd2~0 := #t~ite50;havoc #t~ite46;havoc #t~ite49;havoc #t~ite48;havoc #t~ite47;havoc #t~ite50; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite56 := ~x$r_buff1_thd2~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite56|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$r_buff1_thd2~0 := #t~ite56;havoc #t~ite53;havoc #t~ite51;havoc #t~ite55;havoc #t~ite52;havoc #t~ite56;havoc #t~ite54;~__unbuffered_p1_EAX$read_delayed~0 := 1;~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := ~#x~0.base, ~#x~0.offset;call #t~mem57 := read~int(~#x~0.base, ~#x~0.offset, 4);~__unbuffered_p1_EAX~0 := #t~mem57;havoc #t~mem57; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~x$flush_delayed~0 % 256;#t~ite59 := ~x$mem_tmp~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite59|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 call write~int(#t~ite59, ~#x~0.base, ~#x~0.offset, 4);havoc #t~ite59;havoc #t~mem58;~x$flush_delayed~0 := 0;~y~0 := 1; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~__unbuffered_p0_EAX~0 := ~y~0;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 1;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256);call #t~mem60 := read~int(~#x~0.base, ~#x~0.offset, 4);#t~ite61 := #t~mem60; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite61|=0, |P1_#t~mem60|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd1~0 := 1; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite61|=0, |P1_#t~mem60|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite5 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite61|=0, |P1_#t~mem60|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 #t~ite62 := #t~ite61; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite61|=0, |P1_#t~ite62|=0, |P1_#t~mem60|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 call write~int(#t~ite62, ~#x~0.base, ~#x~0.offset, 4);havoc #t~ite62;havoc #t~ite61;havoc #t~mem60; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 call write~int(#t~ite5, ~#x~0.base, ~#x~0.offset, 4);havoc #t~ite4;havoc #t~ite5;havoc #t~mem3; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite63 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite63|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 ~x$w_buff0_used~0 := #t~ite63;havoc #t~ite63; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite64 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite64|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 ~x$w_buff1_used~0 := #t~ite64;havoc #t~ite64; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite65 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite65|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 ~x$r_buff0_thd2~0 := #t~ite65;havoc #t~ite65; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite66 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite66|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 ~x$r_buff1_thd2~0 := #t~ite66;havoc #t~ite66;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite6 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$w_buff0_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite7 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$w_buff1_used~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite8 := ~x$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$r_buff0_thd1~0 := #t~ite8;havoc #t~ite8; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite9 := ~x$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite9|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$r_buff1_thd1~0 := #t~ite9;havoc #t~ite9;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 havoc main_#t~nondet69;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);call main_#t~mem70 := read~int(~#x~0.base, ~#x~0.offset, 4);main_#t~ite71 := main_#t~mem70; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite71|=1, |ULTIMATE.start_main_#t~mem70|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 main_#t~ite72 := main_#t~ite71; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite71|=1, |ULTIMATE.start_main_#t~ite72|=1, |ULTIMATE.start_main_#t~mem70|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 call write~int(main_#t~ite72, ~#x~0.base, ~#x~0.offset, 4);havoc main_#t~ite71;havoc main_#t~ite72;havoc main_#t~mem70; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite73 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite73|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~x$w_buff0_used~0 := main_#t~ite73;havoc main_#t~ite73; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite74 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite74|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~x$w_buff1_used~0 := main_#t~ite74;havoc main_#t~ite74; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite75 := ~x$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite75|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite75;havoc main_#t~ite75; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite76 := ~x$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite76|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite76;havoc main_#t~ite76;~weak$$choice1~0 := (if 0 == main_#t~nondet77.base + main_#t~nondet77.offset then 0 else 1);havoc main_#t~nondet77.base, main_#t~nondet77.offset; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume 0 != ~weak$$choice1~0 % 256;call main_#t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset, 4);main_#t~ite79 := main_#t~mem78; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite79|=1, |ULTIMATE.start_main_#t~mem78|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 main_#t~ite80 := main_#t~ite79; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite79|=1, |ULTIMATE.start_main_#t~ite80|=1, |ULTIMATE.start_main_#t~mem78|=1, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~__unbuffered_p1_EAX~0 := main_#t~ite80;havoc main_#t~ite80;havoc main_#t~mem78;havoc main_#t~ite79;~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t2669~0.base|=6, |ULTIMATE.start_main_~#t2669~0.offset|=0, |ULTIMATE.start_main_~#t2670~0.base|=5, |ULTIMATE.start_main_~#t2670~0.offset|=0, |~#x~0.base|=7, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [L678] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L681] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L682] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L683] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L684] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L685] -1 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L686] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L687] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L688] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L689] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L690] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L691] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] -1 call ~#x~0.base, ~#x~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] -1 call write~init~int(0, ~#x~0.base, ~#x~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L694] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [L695] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [L696] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [L697] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [L698] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [L699] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [L700] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [L701] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [L702] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [L703] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0] [L704] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [L705] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [L706] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [L707] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [L709] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L710] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L711] -1 ~weak$$choice1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L712] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68, main_#t~nondet69, main_#t~ite72, main_#t~ite71, main_#t~mem70, main_#t~ite73, main_#t~ite74, main_#t~ite75, main_#t~ite76, main_#t~nondet77.base, main_#t~nondet77.offset, main_#t~ite80, main_#t~ite79, main_#t~mem78, main_~#t2669~0.base, main_~#t2669~0.offset, main_~#t2670~0.base, main_~#t2670~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L788] -1 call main_~#t2669~0.base, main_~#t2669~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 call write~int(0, main_~#t2669~0.base, main_~#t2669~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 havoc main_#t~nondet68; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L790] -1 call main_~#t2670~0.base, main_~#t2670~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] -1 call write~int(1, main_~#t2670~0.base, main_~#t2670~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L741-L776] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L744] 0 ~weak$$choice0~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L744] 0 havoc #t~nondet11.base, #t~nondet11.offset; [L745] 0 ~weak$$choice2~0 := (if 0 == #t~nondet12.base + #t~nondet12.offset then 0 else 1); [L745] 0 havoc #t~nondet12.base, #t~nondet12.offset; [L746] 0 ~x$flush_delayed~0 := ~weak$$choice2~0; [L747] 0 call #t~mem13 := read~int(~#x~0.base, ~#x~0.offset, 4); [L747] 0 ~x$mem_tmp~0 := #t~mem13; [L747] 0 havoc #t~mem13; [L748] 0 ~weak$$choice1~0 := (if 0 == #t~nondet14.base + #t~nondet14.offset then 0 else 1); [L748] 0 havoc #t~nondet14.base, #t~nondet14.offset; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] 0 assume 0 == ~x$w_buff0_used~0 % 256; [L749] 0 call #t~mem15 := read~int(~#x~0.base, ~#x~0.offset, 4); [L749] 0 #t~ite25 := #t~mem15; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~mem15=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] 0 call write~int(#t~ite25, ~#x~0.base, ~#x~0.offset, 4); [L749] 0 havoc #t~ite25; [L749] 0 havoc #t~ite23; [L749] 0 havoc #t~ite22; [L749] 0 havoc #t~ite17; [L749] 0 havoc #t~mem15; [L749] 0 havoc #t~ite19; [L749] 0 havoc #t~ite18; [L749] 0 havoc #t~mem16; [L749] 0 havoc #t~ite21; [L749] 0 havoc #t~ite24; [L749] 0 havoc #t~mem20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 assume 0 != ~weak$$choice2~0 % 256; [L750] 0 #t~ite30 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 ~x$w_buff0~0 := #t~ite30; [L750] 0 havoc #t~ite29; [L750] 0 havoc #t~ite30; [L750] 0 havoc #t~ite28; [L750] 0 havoc #t~ite27; [L750] 0 havoc #t~ite26; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 assume 0 != ~weak$$choice2~0 % 256; [L751] 0 #t~ite35 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 ~x$w_buff1~0 := #t~ite35; [L751] 0 havoc #t~ite32; [L751] 0 havoc #t~ite31; [L751] 0 havoc #t~ite33; [L751] 0 havoc #t~ite34; [L751] 0 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 assume 0 != ~weak$$choice2~0 % 256; [L752] 0 #t~ite40 := ~x$w_buff0_used~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite40=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1); [L752] 0 havoc #t~ite37; [L752] 0 havoc #t~ite36; [L752] 0 havoc #t~ite40; [L752] 0 havoc #t~ite39; [L752] 0 havoc #t~ite38; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 assume 0 != ~weak$$choice2~0 % 256; [L753] 0 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite45=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 ~x$w_buff1_used~0 := #t~ite45; [L753] 0 havoc #t~ite41; [L753] 0 havoc #t~ite43; [L753] 0 havoc #t~ite45; [L753] 0 havoc #t~ite42; [L753] 0 havoc #t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 assume 0 != ~weak$$choice2~0 % 256; [L754] 0 #t~ite50 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite50=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 ~x$r_buff0_thd2~0 := #t~ite50; [L754] 0 havoc #t~ite46; [L754] 0 havoc #t~ite49; [L754] 0 havoc #t~ite48; [L754] 0 havoc #t~ite47; [L754] 0 havoc #t~ite50; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 assume 0 != ~weak$$choice2~0 % 256; [L755] 0 #t~ite56 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite56=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 ~x$r_buff1_thd2~0 := #t~ite56; [L755] 0 havoc #t~ite53; [L755] 0 havoc #t~ite51; [L755] 0 havoc #t~ite55; [L755] 0 havoc #t~ite52; [L755] 0 havoc #t~ite56; [L755] 0 havoc #t~ite54; [L756] 0 ~__unbuffered_p1_EAX$read_delayed~0 := 1; [L757] 0 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := ~#x~0.base, ~#x~0.offset; [L758] 0 call #t~mem57 := read~int(~#x~0.base, ~#x~0.offset, 4); [L758] 0 ~__unbuffered_p1_EAX~0 := #t~mem57; [L758] 0 havoc #t~mem57; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] 0 assume 0 != ~x$flush_delayed~0 % 256; [L759] 0 #t~ite59 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite59=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] 0 call write~int(#t~ite59, ~#x~0.base, ~#x~0.offset, 4); [L759] 0 havoc #t~ite59; [L759] 0 havoc #t~mem58; [L760] 0 ~x$flush_delayed~0 := 0; [L763] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L713-L740] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L716] 1 ~__unbuffered_p0_EAX~0 := ~y~0; [L719] 1 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 1 ~x$w_buff0~0 := 1; [L721] 1 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 1 ~x$w_buff0_used~0 := 1; [L723] 1 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 1 havoc __VERIFIER_assert_~expression; [L4] 1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] 1 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256); [L766] 0 call #t~mem60 := read~int(~#x~0.base, ~#x~0.offset, 4); [L766] 0 #t~ite61 := #t~mem60; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L724] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 1 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 1 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 1 ~x$r_buff0_thd1~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L730] 1 #t~ite5 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 #t~ite62 := #t~ite61; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, #t~ite61=0, #t~ite62=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 call write~int(#t~ite62, ~#x~0.base, ~#x~0.offset, 4); [L766] 0 havoc #t~ite62; [L766] 0 havoc #t~ite61; [L766] 0 havoc #t~mem60; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] 1 call write~int(#t~ite5, ~#x~0.base, ~#x~0.offset, 4); [L730] 1 havoc #t~ite4; [L730] 1 havoc #t~ite5; [L730] 1 havoc #t~mem3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L767] 0 #t~ite63 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite63=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 ~x$w_buff0_used~0 := #t~ite63; [L767] 0 havoc #t~ite63; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L768] 0 #t~ite64 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite64=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 ~x$w_buff1_used~0 := #t~ite64; [L768] 0 havoc #t~ite64; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L769] 0 #t~ite65 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite65=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 ~x$r_buff0_thd2~0 := #t~ite65; [L769] 0 havoc #t~ite65; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L770] 0 #t~ite66 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite66=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 ~x$r_buff1_thd2~0 := #t~ite66; [L770] 0 havoc #t~ite66; [L773] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L731] 1 #t~ite6 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 ~x$w_buff0_used~0 := #t~ite6; [L731] 1 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L732] 1 #t~ite7 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 ~x$w_buff1_used~0 := #t~ite7; [L732] 1 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L733] 1 #t~ite8 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 ~x$r_buff0_thd1~0 := #t~ite8; [L733] 1 havoc #t~ite8; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L734] 1 #t~ite9 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite9=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 ~x$r_buff1_thd1~0 := #t~ite9; [L734] 1 havoc #t~ite9; [L737] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L791] -1 havoc main_#t~nondet69; [L793] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L795] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L797] -1 call main_#t~mem70 := read~int(~#x~0.base, ~#x~0.offset, 4); [L797] -1 main_#t~ite71 := main_#t~mem70; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~mem70=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 main_#t~ite72 := main_#t~ite71; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~ite72=1, main_#t~mem70=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 call write~int(main_#t~ite72, ~#x~0.base, ~#x~0.offset, 4); [L797] -1 havoc main_#t~ite71; [L797] -1 havoc main_#t~ite72; [L797] -1 havoc main_#t~mem70; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L798] -1 main_#t~ite73 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite73=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 ~x$w_buff0_used~0 := main_#t~ite73; [L798] -1 havoc main_#t~ite73; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L799] -1 main_#t~ite74 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite74=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 ~x$w_buff1_used~0 := main_#t~ite74; [L799] -1 havoc main_#t~ite74; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L800] -1 main_#t~ite75 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite75=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 ~x$r_buff0_thd0~0 := main_#t~ite75; [L800] -1 havoc main_#t~ite75; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L801] -1 main_#t~ite76 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite76=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 ~x$r_buff1_thd0~0 := main_#t~ite76; [L801] -1 havoc main_#t~ite76; [L804] -1 ~weak$$choice1~0 := (if 0 == main_#t~nondet77.base + main_#t~nondet77.offset then 0 else 1); [L804] -1 havoc main_#t~nondet77.base, main_#t~nondet77.offset; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 assume 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 assume 0 != ~weak$$choice1~0 % 256; [L805] -1 call main_#t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset, 4); [L805] -1 main_#t~ite79 := main_#t~mem78; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~mem78=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 main_#t~ite80 := main_#t~ite79; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~ite80=1, main_#t~mem78=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 ~__unbuffered_p1_EAX~0 := main_#t~ite80; [L805] -1 havoc main_#t~ite80; [L805] -1 havoc main_#t~mem78; [L805] -1 havoc main_#t~ite79; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [L678] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L681] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L682] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L683] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L684] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L685] -1 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L686] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L687] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L688] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L689] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L690] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L691] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] -1 call ~#x~0.base, ~#x~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] -1 call write~init~int(0, ~#x~0.base, ~#x~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L694] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [L695] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [L696] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [L697] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [L698] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [L699] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [L700] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [L701] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [L702] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [L703] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0] [L704] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [L705] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [L706] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [L707] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [L709] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L710] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L711] -1 ~weak$$choice1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L712] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68, main_#t~nondet69, main_#t~ite72, main_#t~ite71, main_#t~mem70, main_#t~ite73, main_#t~ite74, main_#t~ite75, main_#t~ite76, main_#t~nondet77.base, main_#t~nondet77.offset, main_#t~ite80, main_#t~ite79, main_#t~mem78, main_~#t2669~0.base, main_~#t2669~0.offset, main_~#t2670~0.base, main_~#t2670~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L788] -1 call main_~#t2669~0.base, main_~#t2669~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 call write~int(0, main_~#t2669~0.base, main_~#t2669~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 havoc main_#t~nondet68; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L790] -1 call main_~#t2670~0.base, main_~#t2670~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] -1 call write~int(1, main_~#t2670~0.base, main_~#t2670~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L741-L776] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L744] 0 ~weak$$choice0~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L744] 0 havoc #t~nondet11.base, #t~nondet11.offset; [L745] 0 ~weak$$choice2~0 := (if 0 == #t~nondet12.base + #t~nondet12.offset then 0 else 1); [L745] 0 havoc #t~nondet12.base, #t~nondet12.offset; [L746] 0 ~x$flush_delayed~0 := ~weak$$choice2~0; [L747] 0 call #t~mem13 := read~int(~#x~0.base, ~#x~0.offset, 4); [L747] 0 ~x$mem_tmp~0 := #t~mem13; [L747] 0 havoc #t~mem13; [L748] 0 ~weak$$choice1~0 := (if 0 == #t~nondet14.base + #t~nondet14.offset then 0 else 1); [L748] 0 havoc #t~nondet14.base, #t~nondet14.offset; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] 0 assume 0 == ~x$w_buff0_used~0 % 256; [L749] 0 call #t~mem15 := read~int(~#x~0.base, ~#x~0.offset, 4); [L749] 0 #t~ite25 := #t~mem15; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~mem15=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] 0 call write~int(#t~ite25, ~#x~0.base, ~#x~0.offset, 4); [L749] 0 havoc #t~ite25; [L749] 0 havoc #t~ite23; [L749] 0 havoc #t~ite22; [L749] 0 havoc #t~ite17; [L749] 0 havoc #t~mem15; [L749] 0 havoc #t~ite19; [L749] 0 havoc #t~ite18; [L749] 0 havoc #t~mem16; [L749] 0 havoc #t~ite21; [L749] 0 havoc #t~ite24; [L749] 0 havoc #t~mem20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 assume 0 != ~weak$$choice2~0 % 256; [L750] 0 #t~ite30 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 ~x$w_buff0~0 := #t~ite30; [L750] 0 havoc #t~ite29; [L750] 0 havoc #t~ite30; [L750] 0 havoc #t~ite28; [L750] 0 havoc #t~ite27; [L750] 0 havoc #t~ite26; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 assume 0 != ~weak$$choice2~0 % 256; [L751] 0 #t~ite35 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 ~x$w_buff1~0 := #t~ite35; [L751] 0 havoc #t~ite32; [L751] 0 havoc #t~ite31; [L751] 0 havoc #t~ite33; [L751] 0 havoc #t~ite34; [L751] 0 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 assume 0 != ~weak$$choice2~0 % 256; [L752] 0 #t~ite40 := ~x$w_buff0_used~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite40=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1); [L752] 0 havoc #t~ite37; [L752] 0 havoc #t~ite36; [L752] 0 havoc #t~ite40; [L752] 0 havoc #t~ite39; [L752] 0 havoc #t~ite38; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 assume 0 != ~weak$$choice2~0 % 256; [L753] 0 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite45=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 ~x$w_buff1_used~0 := #t~ite45; [L753] 0 havoc #t~ite41; [L753] 0 havoc #t~ite43; [L753] 0 havoc #t~ite45; [L753] 0 havoc #t~ite42; [L753] 0 havoc #t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 assume 0 != ~weak$$choice2~0 % 256; [L754] 0 #t~ite50 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite50=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 ~x$r_buff0_thd2~0 := #t~ite50; [L754] 0 havoc #t~ite46; [L754] 0 havoc #t~ite49; [L754] 0 havoc #t~ite48; [L754] 0 havoc #t~ite47; [L754] 0 havoc #t~ite50; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 assume 0 != ~weak$$choice2~0 % 256; [L755] 0 #t~ite56 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite56=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 ~x$r_buff1_thd2~0 := #t~ite56; [L755] 0 havoc #t~ite53; [L755] 0 havoc #t~ite51; [L755] 0 havoc #t~ite55; [L755] 0 havoc #t~ite52; [L755] 0 havoc #t~ite56; [L755] 0 havoc #t~ite54; [L756] 0 ~__unbuffered_p1_EAX$read_delayed~0 := 1; [L757] 0 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := ~#x~0.base, ~#x~0.offset; [L758] 0 call #t~mem57 := read~int(~#x~0.base, ~#x~0.offset, 4); [L758] 0 ~__unbuffered_p1_EAX~0 := #t~mem57; [L758] 0 havoc #t~mem57; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] 0 assume 0 != ~x$flush_delayed~0 % 256; [L759] 0 #t~ite59 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite59=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] 0 call write~int(#t~ite59, ~#x~0.base, ~#x~0.offset, 4); [L759] 0 havoc #t~ite59; [L759] 0 havoc #t~mem58; [L760] 0 ~x$flush_delayed~0 := 0; [L763] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L713-L740] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L716] 1 ~__unbuffered_p0_EAX~0 := ~y~0; [L719] 1 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 1 ~x$w_buff0~0 := 1; [L721] 1 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 1 ~x$w_buff0_used~0 := 1; [L723] 1 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 1 havoc __VERIFIER_assert_~expression; [L4] 1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] 1 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256); [L766] 0 call #t~mem60 := read~int(~#x~0.base, ~#x~0.offset, 4); [L766] 0 #t~ite61 := #t~mem60; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L724] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 1 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 1 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 1 ~x$r_buff0_thd1~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L730] 1 #t~ite5 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 #t~ite62 := #t~ite61; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, #t~ite61=0, #t~ite62=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 call write~int(#t~ite62, ~#x~0.base, ~#x~0.offset, 4); [L766] 0 havoc #t~ite62; [L766] 0 havoc #t~ite61; [L766] 0 havoc #t~mem60; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] 1 call write~int(#t~ite5, ~#x~0.base, ~#x~0.offset, 4); [L730] 1 havoc #t~ite4; [L730] 1 havoc #t~ite5; [L730] 1 havoc #t~mem3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L767] 0 #t~ite63 := ~x$w_buff0_used~0; WARNING: YOUR LOGFILE WAS TOO LONG, SOME LINES IN THE MIDDLE WERE REMOVED. [L709] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L710] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L711] -1 ~weak$$choice1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L712] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68, main_#t~nondet69, main_#t~ite72, main_#t~ite71, main_#t~mem70, main_#t~ite73, main_#t~ite74, main_#t~ite75, main_#t~ite76, main_#t~nondet77.base, main_#t~nondet77.offset, main_#t~ite80, main_#t~ite79, main_#t~mem78, main_~#t2669~0.base, main_~#t2669~0.offset, main_~#t2670~0.base, main_~#t2670~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L788] -1 call main_~#t2669~0.base, main_~#t2669~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 call write~int(0, main_~#t2669~0.base, main_~#t2669~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 havoc main_#t~nondet68; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L790] -1 call main_~#t2670~0.base, main_~#t2670~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] -1 call write~int(1, main_~#t2670~0.base, main_~#t2670~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L741-L776] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L744] 0 ~weak$$choice0~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L744] 0 havoc #t~nondet11.base, #t~nondet11.offset; [L745] 0 ~weak$$choice2~0 := (if 0 == #t~nondet12.base + #t~nondet12.offset then 0 else 1); [L745] 0 havoc #t~nondet12.base, #t~nondet12.offset; [L746] 0 ~x$flush_delayed~0 := ~weak$$choice2~0; [L747] 0 call #t~mem13 := read~int(~#x~0.base, ~#x~0.offset, 4); [L747] 0 ~x$mem_tmp~0 := #t~mem13; [L747] 0 havoc #t~mem13; [L748] 0 ~weak$$choice1~0 := (if 0 == #t~nondet14.base + #t~nondet14.offset then 0 else 1); [L748] 0 havoc #t~nondet14.base, #t~nondet14.offset; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] 0 assume 0 == ~x$w_buff0_used~0 % 256; [L749] 0 call #t~mem15 := read~int(~#x~0.base, ~#x~0.offset, 4); [L749] 0 #t~ite25 := #t~mem15; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~mem15=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] 0 call write~int(#t~ite25, ~#x~0.base, ~#x~0.offset, 4); [L749] 0 havoc #t~ite25; [L749] 0 havoc #t~ite23; [L749] 0 havoc #t~ite22; [L749] 0 havoc #t~ite17; [L749] 0 havoc #t~mem15; [L749] 0 havoc #t~ite19; [L749] 0 havoc #t~ite18; [L749] 0 havoc #t~mem16; [L749] 0 havoc #t~ite21; [L749] 0 havoc #t~ite24; [L749] 0 havoc #t~mem20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 assume 0 != ~weak$$choice2~0 % 256; [L750] 0 #t~ite30 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 ~x$w_buff0~0 := #t~ite30; [L750] 0 havoc #t~ite29; [L750] 0 havoc #t~ite30; [L750] 0 havoc #t~ite28; [L750] 0 havoc #t~ite27; [L750] 0 havoc #t~ite26; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 assume 0 != ~weak$$choice2~0 % 256; [L751] 0 #t~ite35 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 ~x$w_buff1~0 := #t~ite35; [L751] 0 havoc #t~ite32; [L751] 0 havoc #t~ite31; [L751] 0 havoc #t~ite33; [L751] 0 havoc #t~ite34; [L751] 0 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 assume 0 != ~weak$$choice2~0 % 256; [L752] 0 #t~ite40 := ~x$w_buff0_used~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite40=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1); [L752] 0 havoc #t~ite37; [L752] 0 havoc #t~ite36; [L752] 0 havoc #t~ite40; [L752] 0 havoc #t~ite39; [L752] 0 havoc #t~ite38; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 assume 0 != ~weak$$choice2~0 % 256; [L753] 0 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite45=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 ~x$w_buff1_used~0 := #t~ite45; [L753] 0 havoc #t~ite41; [L753] 0 havoc #t~ite43; [L753] 0 havoc #t~ite45; [L753] 0 havoc #t~ite42; [L753] 0 havoc #t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 assume 0 != ~weak$$choice2~0 % 256; [L754] 0 #t~ite50 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite50=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 ~x$r_buff0_thd2~0 := #t~ite50; [L754] 0 havoc #t~ite46; [L754] 0 havoc #t~ite49; [L754] 0 havoc #t~ite48; [L754] 0 havoc #t~ite47; [L754] 0 havoc #t~ite50; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 assume 0 != ~weak$$choice2~0 % 256; [L755] 0 #t~ite56 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite56=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 ~x$r_buff1_thd2~0 := #t~ite56; [L755] 0 havoc #t~ite53; [L755] 0 havoc #t~ite51; [L755] 0 havoc #t~ite55; [L755] 0 havoc #t~ite52; [L755] 0 havoc #t~ite56; [L755] 0 havoc #t~ite54; [L756] 0 ~__unbuffered_p1_EAX$read_delayed~0 := 1; [L757] 0 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := ~#x~0.base, ~#x~0.offset; [L758] 0 call #t~mem57 := read~int(~#x~0.base, ~#x~0.offset, 4); [L758] 0 ~__unbuffered_p1_EAX~0 := #t~mem57; [L758] 0 havoc #t~mem57; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] 0 assume 0 != ~x$flush_delayed~0 % 256; [L759] 0 #t~ite59 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite59=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] 0 call write~int(#t~ite59, ~#x~0.base, ~#x~0.offset, 4); [L759] 0 havoc #t~ite59; [L759] 0 havoc #t~mem58; [L760] 0 ~x$flush_delayed~0 := 0; [L763] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L713-L740] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L716] 1 ~__unbuffered_p0_EAX~0 := ~y~0; [L719] 1 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 1 ~x$w_buff0~0 := 1; [L721] 1 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 1 ~x$w_buff0_used~0 := 1; [L723] 1 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 1 havoc __VERIFIER_assert_~expression; [L4] 1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] 1 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256); [L766] 0 call #t~mem60 := read~int(~#x~0.base, ~#x~0.offset, 4); [L766] 0 #t~ite61 := #t~mem60; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L724] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 1 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 1 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 1 ~x$r_buff0_thd1~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L730] 1 #t~ite5 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 #t~ite62 := #t~ite61; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, #t~ite61=0, #t~ite62=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 call write~int(#t~ite62, ~#x~0.base, ~#x~0.offset, 4); [L766] 0 havoc #t~ite62; [L766] 0 havoc #t~ite61; [L766] 0 havoc #t~mem60; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] 1 call write~int(#t~ite5, ~#x~0.base, ~#x~0.offset, 4); [L730] 1 havoc #t~ite4; [L730] 1 havoc #t~ite5; [L730] 1 havoc #t~mem3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L767] 0 #t~ite63 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite63=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 ~x$w_buff0_used~0 := #t~ite63; [L767] 0 havoc #t~ite63; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L768] 0 #t~ite64 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite64=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 ~x$w_buff1_used~0 := #t~ite64; [L768] 0 havoc #t~ite64; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L769] 0 #t~ite65 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite65=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 ~x$r_buff0_thd2~0 := #t~ite65; [L769] 0 havoc #t~ite65; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L770] 0 #t~ite66 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite66=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 ~x$r_buff1_thd2~0 := #t~ite66; [L770] 0 havoc #t~ite66; [L773] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L731] 1 #t~ite6 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 ~x$w_buff0_used~0 := #t~ite6; [L731] 1 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L732] 1 #t~ite7 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 ~x$w_buff1_used~0 := #t~ite7; [L732] 1 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L733] 1 #t~ite8 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 ~x$r_buff0_thd1~0 := #t~ite8; [L733] 1 havoc #t~ite8; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L734] 1 #t~ite9 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite9=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 ~x$r_buff1_thd1~0 := #t~ite9; [L734] 1 havoc #t~ite9; [L737] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L791] -1 havoc main_#t~nondet69; [L793] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L795] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L797] -1 call main_#t~mem70 := read~int(~#x~0.base, ~#x~0.offset, 4); [L797] -1 main_#t~ite71 := main_#t~mem70; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~mem70=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 main_#t~ite72 := main_#t~ite71; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~ite72=1, main_#t~mem70=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 call write~int(main_#t~ite72, ~#x~0.base, ~#x~0.offset, 4); [L797] -1 havoc main_#t~ite71; [L797] -1 havoc main_#t~ite72; [L797] -1 havoc main_#t~mem70; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L798] -1 main_#t~ite73 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite73=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 ~x$w_buff0_used~0 := main_#t~ite73; [L798] -1 havoc main_#t~ite73; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L799] -1 main_#t~ite74 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite74=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 ~x$w_buff1_used~0 := main_#t~ite74; [L799] -1 havoc main_#t~ite74; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L800] -1 main_#t~ite75 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite75=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 ~x$r_buff0_thd0~0 := main_#t~ite75; [L800] -1 havoc main_#t~ite75; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L801] -1 main_#t~ite76 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite76=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 ~x$r_buff1_thd0~0 := main_#t~ite76; [L801] -1 havoc main_#t~ite76; [L804] -1 ~weak$$choice1~0 := (if 0 == main_#t~nondet77.base + main_#t~nondet77.offset then 0 else 1); [L804] -1 havoc main_#t~nondet77.base, main_#t~nondet77.offset; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 assume 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 assume 0 != ~weak$$choice1~0 % 256; [L805] -1 call main_#t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset, 4); [L805] -1 main_#t~ite79 := main_#t~mem78; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~mem78=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 main_#t~ite80 := main_#t~ite79; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~ite80=1, main_#t~mem78=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 ~__unbuffered_p1_EAX~0 := main_#t~ite80; [L805] -1 havoc main_#t~ite80; [L805] -1 havoc main_#t~mem78; [L805] -1 havoc main_#t~ite79; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [L678] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L681] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L682] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L683] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L684] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L685] -1 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L686] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L687] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L688] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L689] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L690] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L691] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] -1 call ~#x~0.base, ~#x~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] -1 call write~init~int(0, ~#x~0.base, ~#x~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L694] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [L695] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [L696] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [L697] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [L698] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [L699] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [L700] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [L701] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [L702] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [L703] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0] [L704] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [L705] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [L706] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [L707] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [L709] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L710] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L711] -1 ~weak$$choice1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L712] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68, main_#t~nondet69, main_#t~ite72, main_#t~ite71, main_#t~mem70, main_#t~ite73, main_#t~ite74, main_#t~ite75, main_#t~ite76, main_#t~nondet77.base, main_#t~nondet77.offset, main_#t~ite80, main_#t~ite79, main_#t~mem78, main_~#t2669~0.base, main_~#t2669~0.offset, main_~#t2670~0.base, main_~#t2670~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L788] -1 call main_~#t2669~0.base, main_~#t2669~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 call write~int(0, main_~#t2669~0.base, main_~#t2669~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 havoc main_#t~nondet68; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L790] -1 call main_~#t2670~0.base, main_~#t2670~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] -1 call write~int(1, main_~#t2670~0.base, main_~#t2670~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L741-L776] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L744] 0 ~weak$$choice0~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L744] 0 havoc #t~nondet11.base, #t~nondet11.offset; [L745] 0 ~weak$$choice2~0 := (if 0 == #t~nondet12.base + #t~nondet12.offset then 0 else 1); [L745] 0 havoc #t~nondet12.base, #t~nondet12.offset; [L746] 0 ~x$flush_delayed~0 := ~weak$$choice2~0; [L747] 0 call #t~mem13 := read~int(~#x~0.base, ~#x~0.offset, 4); [L747] 0 ~x$mem_tmp~0 := #t~mem13; [L747] 0 havoc #t~mem13; [L748] 0 ~weak$$choice1~0 := (if 0 == #t~nondet14.base + #t~nondet14.offset then 0 else 1); [L748] 0 havoc #t~nondet14.base, #t~nondet14.offset; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] 0 assume 0 == ~x$w_buff0_used~0 % 256; [L749] 0 call #t~mem15 := read~int(~#x~0.base, ~#x~0.offset, 4); [L749] 0 #t~ite25 := #t~mem15; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~mem15=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] 0 call write~int(#t~ite25, ~#x~0.base, ~#x~0.offset, 4); [L749] 0 havoc #t~ite25; [L749] 0 havoc #t~ite23; [L749] 0 havoc #t~ite22; [L749] 0 havoc #t~ite17; [L749] 0 havoc #t~mem15; [L749] 0 havoc #t~ite19; [L749] 0 havoc #t~ite18; [L749] 0 havoc #t~mem16; [L749] 0 havoc #t~ite21; [L749] 0 havoc #t~ite24; [L749] 0 havoc #t~mem20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 assume 0 != ~weak$$choice2~0 % 256; [L750] 0 #t~ite30 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 ~x$w_buff0~0 := #t~ite30; [L750] 0 havoc #t~ite29; [L750] 0 havoc #t~ite30; [L750] 0 havoc #t~ite28; [L750] 0 havoc #t~ite27; [L750] 0 havoc #t~ite26; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 assume 0 != ~weak$$choice2~0 % 256; [L751] 0 #t~ite35 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 ~x$w_buff1~0 := #t~ite35; [L751] 0 havoc #t~ite32; [L751] 0 havoc #t~ite31; [L751] 0 havoc #t~ite33; [L751] 0 havoc #t~ite34; [L751] 0 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 assume 0 != ~weak$$choice2~0 % 256; [L752] 0 #t~ite40 := ~x$w_buff0_used~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite40=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1); [L752] 0 havoc #t~ite37; [L752] 0 havoc #t~ite36; [L752] 0 havoc #t~ite40; [L752] 0 havoc #t~ite39; [L752] 0 havoc #t~ite38; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 assume 0 != ~weak$$choice2~0 % 256; [L753] 0 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite45=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 ~x$w_buff1_used~0 := #t~ite45; [L753] 0 havoc #t~ite41; [L753] 0 havoc #t~ite43; [L753] 0 havoc #t~ite45; [L753] 0 havoc #t~ite42; [L753] 0 havoc #t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 assume 0 != ~weak$$choice2~0 % 256; [L754] 0 #t~ite50 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite50=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 ~x$r_buff0_thd2~0 := #t~ite50; [L754] 0 havoc #t~ite46; [L754] 0 havoc #t~ite49; [L754] 0 havoc #t~ite48; [L754] 0 havoc #t~ite47; [L754] 0 havoc #t~ite50; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 assume 0 != ~weak$$choice2~0 % 256; [L755] 0 #t~ite56 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite56=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 ~x$r_buff1_thd2~0 := #t~ite56; [L755] 0 havoc #t~ite53; [L755] 0 havoc #t~ite51; [L755] 0 havoc #t~ite55; [L755] 0 havoc #t~ite52; [L755] 0 havoc #t~ite56; [L755] 0 havoc #t~ite54; [L756] 0 ~__unbuffered_p1_EAX$read_delayed~0 := 1; [L757] 0 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := ~#x~0.base, ~#x~0.offset; [L758] 0 call #t~mem57 := read~int(~#x~0.base, ~#x~0.offset, 4); [L758] 0 ~__unbuffered_p1_EAX~0 := #t~mem57; [L758] 0 havoc #t~mem57; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] 0 assume 0 != ~x$flush_delayed~0 % 256; [L759] 0 #t~ite59 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite59=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] 0 call write~int(#t~ite59, ~#x~0.base, ~#x~0.offset, 4); [L759] 0 havoc #t~ite59; [L759] 0 havoc #t~mem58; [L760] 0 ~x$flush_delayed~0 := 0; [L763] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L713-L740] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L716] 1 ~__unbuffered_p0_EAX~0 := ~y~0; [L719] 1 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 1 ~x$w_buff0~0 := 1; [L721] 1 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 1 ~x$w_buff0_used~0 := 1; [L723] 1 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 1 havoc __VERIFIER_assert_~expression; [L4] 1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] 1 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256); [L766] 0 call #t~mem60 := read~int(~#x~0.base, ~#x~0.offset, 4); [L766] 0 #t~ite61 := #t~mem60; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L724] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 1 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 1 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 1 ~x$r_buff0_thd1~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L730] 1 #t~ite5 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 #t~ite62 := #t~ite61; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, #t~ite61=0, #t~ite62=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 call write~int(#t~ite62, ~#x~0.base, ~#x~0.offset, 4); [L766] 0 havoc #t~ite62; [L766] 0 havoc #t~ite61; [L766] 0 havoc #t~mem60; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] 1 call write~int(#t~ite5, ~#x~0.base, ~#x~0.offset, 4); [L730] 1 havoc #t~ite4; [L730] 1 havoc #t~ite5; [L730] 1 havoc #t~mem3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L767] 0 #t~ite63 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite63=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 ~x$w_buff0_used~0 := #t~ite63; [L767] 0 havoc #t~ite63; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L768] 0 #t~ite64 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite64=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 ~x$w_buff1_used~0 := #t~ite64; [L768] 0 havoc #t~ite64; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L769] 0 #t~ite65 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite65=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 ~x$r_buff0_thd2~0 := #t~ite65; [L769] 0 havoc #t~ite65; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L770] 0 #t~ite66 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite66=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 ~x$r_buff1_thd2~0 := #t~ite66; [L770] 0 havoc #t~ite66; [L773] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L731] 1 #t~ite6 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 ~x$w_buff0_used~0 := #t~ite6; [L731] 1 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L732] 1 #t~ite7 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 ~x$w_buff1_used~0 := #t~ite7; [L732] 1 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L733] 1 #t~ite8 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 ~x$r_buff0_thd1~0 := #t~ite8; [L733] 1 havoc #t~ite8; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L734] 1 #t~ite9 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite9=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 ~x$r_buff1_thd1~0 := #t~ite9; [L734] 1 havoc #t~ite9; [L737] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L791] -1 havoc main_#t~nondet69; [L793] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L795] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L797] -1 call main_#t~mem70 := read~int(~#x~0.base, ~#x~0.offset, 4); [L797] -1 main_#t~ite71 := main_#t~mem70; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~mem70=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 main_#t~ite72 := main_#t~ite71; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~ite72=1, main_#t~mem70=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 call write~int(main_#t~ite72, ~#x~0.base, ~#x~0.offset, 4); [L797] -1 havoc main_#t~ite71; [L797] -1 havoc main_#t~ite72; [L797] -1 havoc main_#t~mem70; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L798] -1 main_#t~ite73 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite73=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 ~x$w_buff0_used~0 := main_#t~ite73; [L798] -1 havoc main_#t~ite73; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L799] -1 main_#t~ite74 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite74=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 ~x$w_buff1_used~0 := main_#t~ite74; [L799] -1 havoc main_#t~ite74; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L800] -1 main_#t~ite75 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite75=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 ~x$r_buff0_thd0~0 := main_#t~ite75; [L800] -1 havoc main_#t~ite75; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L801] -1 main_#t~ite76 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite76=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 ~x$r_buff1_thd0~0 := main_#t~ite76; [L801] -1 havoc main_#t~ite76; [L804] -1 ~weak$$choice1~0 := (if 0 == main_#t~nondet77.base + main_#t~nondet77.offset then 0 else 1); [L804] -1 havoc main_#t~nondet77.base, main_#t~nondet77.offset; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 assume 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 assume 0 != ~weak$$choice1~0 % 256; [L805] -1 call main_#t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset, 4); [L805] -1 main_#t~ite79 := main_#t~mem78; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~mem78=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 main_#t~ite80 := main_#t~ite79; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~ite80=1, main_#t~mem78=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 ~__unbuffered_p1_EAX~0 := main_#t~ite80; [L805] -1 havoc main_#t~ite80; [L805] -1 havoc main_#t~mem78; [L805] -1 havoc main_#t~ite79; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t2669~0.base=6, main_~#t2669~0.offset=0, main_~#t2670~0.base=5, main_~#t2670~0.offset=0, ~#x~0.base=7, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=7, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [L678] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L681] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L682] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L683] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L684] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L685] -1 ~__unbuffered_p1_EAX$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L686] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L687] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L688] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L689] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L690] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L691] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] FCALL -1 call ~#x~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] FCALL -1 call write~init~int(0, ~#x~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L694] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [L695] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [L696] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [L697] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [L698] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [L699] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [L700] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [L701] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [L702] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [L703] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0] [L704] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [L705] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [L706] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [L707] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [L709] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L710] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L711] -1 ~weak$$choice1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L712] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68, main_#t~nondet69, main_#t~ite72, main_#t~ite71, main_#t~mem70, main_#t~ite73, main_#t~ite74, main_#t~ite75, main_#t~ite76, main_#t~nondet77, main_#t~ite80, main_#t~ite79, main_#t~mem78, main_~#t2669~0, main_~#t2670~0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L788] FCALL -1 call main_~#t2669~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FCALL -1 call write~int(0, main_~#t2669~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 havoc main_#t~nondet68; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L790] FCALL -1 call main_~#t2670~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FCALL -1 call write~int(1, main_~#t2670~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L741-L776] 0 ~arg := #in~arg; [L744] 0 ~weak$$choice0~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L744] 0 havoc #t~nondet11; [L745] 0 ~weak$$choice2~0 := (if 0 == #t~nondet12!base + #t~nondet12!offset then 0 else 1); [L745] 0 havoc #t~nondet12; [L746] 0 ~x$flush_delayed~0 := ~weak$$choice2~0; [L747] FCALL 0 call #t~mem13 := read~int(~#x~0, 4); [L747] 0 ~x$mem_tmp~0 := #t~mem13; [L747] 0 havoc #t~mem13; [L748] 0 ~weak$$choice1~0 := (if 0 == #t~nondet14!base + #t~nondet14!offset then 0 else 1); [L748] 0 havoc #t~nondet14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] COND TRUE 0 0 == ~x$w_buff0_used~0 % 256 [L749] FCALL 0 call #t~mem15 := read~int(~#x~0, 4); [L749] 0 #t~ite25 := #t~mem15; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~mem15=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] FCALL 0 call write~int(#t~ite25, ~#x~0, 4); [L749] 0 havoc #t~ite25; [L749] 0 havoc #t~ite23; [L749] 0 havoc #t~ite22; [L749] 0 havoc #t~ite17; [L749] 0 havoc #t~mem15; [L749] 0 havoc #t~ite19; [L749] 0 havoc #t~ite18; [L749] 0 havoc #t~mem16; [L749] 0 havoc #t~ite21; [L749] 0 havoc #t~ite24; [L749] 0 havoc #t~mem20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L750] 0 #t~ite30 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 ~x$w_buff0~0 := #t~ite30; [L750] 0 havoc #t~ite29; [L750] 0 havoc #t~ite30; [L750] 0 havoc #t~ite28; [L750] 0 havoc #t~ite27; [L750] 0 havoc #t~ite26; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L751] 0 #t~ite35 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 ~x$w_buff1~0 := #t~ite35; [L751] 0 havoc #t~ite32; [L751] 0 havoc #t~ite31; [L751] 0 havoc #t~ite33; [L751] 0 havoc #t~ite34; [L751] 0 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L752] 0 #t~ite40 := ~x$w_buff0_used~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite40=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1); [L752] 0 havoc #t~ite37; [L752] 0 havoc #t~ite36; [L752] 0 havoc #t~ite40; [L752] 0 havoc #t~ite39; [L752] 0 havoc #t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L753] 0 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite45=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 ~x$w_buff1_used~0 := #t~ite45; [L753] 0 havoc #t~ite41; [L753] 0 havoc #t~ite43; [L753] 0 havoc #t~ite45; [L753] 0 havoc #t~ite42; [L753] 0 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L754] 0 #t~ite50 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite50=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 ~x$r_buff0_thd2~0 := #t~ite50; [L754] 0 havoc #t~ite46; [L754] 0 havoc #t~ite49; [L754] 0 havoc #t~ite48; [L754] 0 havoc #t~ite47; [L754] 0 havoc #t~ite50; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L755] 0 #t~ite56 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite56=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 ~x$r_buff1_thd2~0 := #t~ite56; [L755] 0 havoc #t~ite53; [L755] 0 havoc #t~ite51; [L755] 0 havoc #t~ite55; [L755] 0 havoc #t~ite52; [L755] 0 havoc #t~ite56; [L755] 0 havoc #t~ite54; [L756] 0 ~__unbuffered_p1_EAX$read_delayed~0 := 1; [L757] 0 ~__unbuffered_p1_EAX$read_delayed_var~0 := ~#x~0; [L758] FCALL 0 call #t~mem57 := read~int(~#x~0, 4); [L758] 0 ~__unbuffered_p1_EAX~0 := #t~mem57; [L758] 0 havoc #t~mem57; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] COND TRUE 0 0 != ~x$flush_delayed~0 % 256 [L759] 0 #t~ite59 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite59=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] FCALL 0 call write~int(#t~ite59, ~#x~0, 4); [L759] 0 havoc #t~ite59; [L759] 0 havoc #t~mem58; [L760] 0 ~x$flush_delayed~0 := 0; [L763] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L713-L740] 1 ~arg := #in~arg; [L716] 1 ~__unbuffered_p0_EAX~0 := ~y~0; [L719] 1 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 1 ~x$w_buff0~0 := 1; [L721] 1 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 1 ~x$w_buff0_used~0 := 1; [L723] 1 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 1 havoc __VERIFIER_assert_~expression; [L4] 1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] COND FALSE 1 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] COND FALSE 0 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L766] FCALL 0 call #t~mem60 := read~int(~#x~0, 4); [L766] 0 #t~ite61 := #t~mem60; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L724] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 1 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 1 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 1 ~x$r_buff0_thd1~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] COND TRUE 1 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L730] 1 #t~ite5 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 #t~ite62 := #t~ite61; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, #t~ite61=0, #t~ite62=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] FCALL 0 call write~int(#t~ite62, ~#x~0, 4); [L766] 0 havoc #t~ite62; [L766] 0 havoc #t~ite61; [L766] 0 havoc #t~mem60; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] FCALL 1 call write~int(#t~ite5, ~#x~0, 4); [L730] 1 havoc #t~ite4; [L730] 1 havoc #t~ite5; [L730] 1 havoc #t~mem3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L767] 0 #t~ite63 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite63=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 ~x$w_buff0_used~0 := #t~ite63; [L767] 0 havoc #t~ite63; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L768] 0 #t~ite64 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite64=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 ~x$w_buff1_used~0 := #t~ite64; [L768] 0 havoc #t~ite64; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L769] 0 #t~ite65 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite65=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 ~x$r_buff0_thd2~0 := #t~ite65; [L769] 0 havoc #t~ite65; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L770] 0 #t~ite66 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite66=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 ~x$r_buff1_thd2~0 := #t~ite66; [L770] 0 havoc #t~ite66; [L773] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] COND TRUE 1 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L731] 1 #t~ite6 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 ~x$w_buff0_used~0 := #t~ite6; [L731] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L732] 1 #t~ite7 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 ~x$w_buff1_used~0 := #t~ite7; [L732] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L733] 1 #t~ite8 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 ~x$r_buff0_thd1~0 := #t~ite8; [L733] 1 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L734] 1 #t~ite9 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite9=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 ~x$r_buff1_thd1~0 := #t~ite9; [L734] 1 havoc #t~ite9; [L737] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L791] -1 havoc main_#t~nondet69; [L793] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L795] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L797] FCALL -1 call main_#t~mem70 := read~int(~#x~0, 4); [L797] -1 main_#t~ite71 := main_#t~mem70; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~mem70=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 main_#t~ite72 := main_#t~ite71; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~ite72=1, main_#t~mem70=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] FCALL -1 call write~int(main_#t~ite72, ~#x~0, 4); [L797] -1 havoc main_#t~ite71; [L797] -1 havoc main_#t~ite72; [L797] -1 havoc main_#t~mem70; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L798] -1 main_#t~ite73 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite73=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 ~x$w_buff0_used~0 := main_#t~ite73; [L798] -1 havoc main_#t~ite73; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L799] -1 main_#t~ite74 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite74=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 ~x$w_buff1_used~0 := main_#t~ite74; [L799] -1 havoc main_#t~ite74; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L800] -1 main_#t~ite75 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite75=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 ~x$r_buff0_thd0~0 := main_#t~ite75; [L800] -1 havoc main_#t~ite75; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L801] -1 main_#t~ite76 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite76=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 ~x$r_buff1_thd0~0 := main_#t~ite76; [L801] -1 havoc main_#t~ite76; [L804] -1 ~weak$$choice1~0 := (if 0 == main_#t~nondet77!base + main_#t~nondet77!offset then 0 else 1); [L804] -1 havoc main_#t~nondet77; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] COND TRUE -1 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256 VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] COND TRUE -1 0 != ~weak$$choice1~0 % 256 [L805] FCALL -1 call main_#t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0, 4); [L805] -1 main_#t~ite79 := main_#t~mem78; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~mem78=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 main_#t~ite80 := main_#t~ite79; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~ite80=1, main_#t~mem78=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 ~__unbuffered_p1_EAX~0 := main_#t~ite80; [L805] -1 havoc main_#t~ite80; [L805] -1 havoc main_#t~mem78; [L805] -1 havoc main_#t~ite79; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [L678] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L681] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L682] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L683] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L684] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L685] -1 ~__unbuffered_p1_EAX$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L686] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L687] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L688] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L689] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L690] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L691] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] FCALL -1 call ~#x~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] FCALL -1 call write~init~int(0, ~#x~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L694] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [L695] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [L696] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [L697] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [L698] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [L699] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [L700] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [L701] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [L702] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [L703] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0] [L704] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [L705] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [L706] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [L707] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [L709] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L710] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L711] -1 ~weak$$choice1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L712] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68, main_#t~nondet69, main_#t~ite72, main_#t~ite71, main_#t~mem70, main_#t~ite73, main_#t~ite74, main_#t~ite75, main_#t~ite76, main_#t~nondet77, main_#t~ite80, main_#t~ite79, main_#t~mem78, main_~#t2669~0, main_~#t2670~0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L788] FCALL -1 call main_~#t2669~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FCALL -1 call write~int(0, main_~#t2669~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 havoc main_#t~nondet68; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L790] FCALL -1 call main_~#t2670~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FCALL -1 call write~int(1, main_~#t2670~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L741-L776] 0 ~arg := #in~arg; [L744] 0 ~weak$$choice0~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L744] 0 havoc #t~nondet11; [L745] 0 ~weak$$choice2~0 := (if 0 == #t~nondet12!base + #t~nondet12!offset then 0 else 1); [L745] 0 havoc #t~nondet12; [L746] 0 ~x$flush_delayed~0 := ~weak$$choice2~0; [L747] FCALL 0 call #t~mem13 := read~int(~#x~0, 4); [L747] 0 ~x$mem_tmp~0 := #t~mem13; [L747] 0 havoc #t~mem13; [L748] 0 ~weak$$choice1~0 := (if 0 == #t~nondet14!base + #t~nondet14!offset then 0 else 1); [L748] 0 havoc #t~nondet14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] COND TRUE 0 0 == ~x$w_buff0_used~0 % 256 [L749] FCALL 0 call #t~mem15 := read~int(~#x~0, 4); [L749] 0 #t~ite25 := #t~mem15; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~mem15=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] FCALL 0 call write~int(#t~ite25, ~#x~0, 4); [L749] 0 havoc #t~ite25; [L749] 0 havoc #t~ite23; [L749] 0 havoc #t~ite22; [L749] 0 havoc #t~ite17; [L749] 0 havoc #t~mem15; [L749] 0 havoc #t~ite19; [L749] 0 havoc #t~ite18; [L749] 0 havoc #t~mem16; [L749] 0 havoc #t~ite21; [L749] 0 havoc #t~ite24; [L749] 0 havoc #t~mem20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L750] 0 #t~ite30 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 ~x$w_buff0~0 := #t~ite30; [L750] 0 havoc #t~ite29; [L750] 0 havoc #t~ite30; [L750] 0 havoc #t~ite28; [L750] 0 havoc #t~ite27; [L750] 0 havoc #t~ite26; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L751] 0 #t~ite35 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 ~x$w_buff1~0 := #t~ite35; [L751] 0 havoc #t~ite32; [L751] 0 havoc #t~ite31; [L751] 0 havoc #t~ite33; [L751] 0 havoc #t~ite34; [L751] 0 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L752] 0 #t~ite40 := ~x$w_buff0_used~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite40=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1); [L752] 0 havoc #t~ite37; [L752] 0 havoc #t~ite36; [L752] 0 havoc #t~ite40; [L752] 0 havoc #t~ite39; [L752] 0 havoc #t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L753] 0 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite45=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 ~x$w_buff1_used~0 := #t~ite45; [L753] 0 havoc #t~ite41; [L753] 0 havoc #t~ite43; [L753] 0 havoc #t~ite45; [L753] 0 havoc #t~ite42; [L753] 0 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L754] 0 #t~ite50 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite50=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 ~x$r_buff0_thd2~0 := #t~ite50; [L754] 0 havoc #t~ite46; [L754] 0 havoc #t~ite49; [L754] 0 havoc #t~ite48; [L754] 0 havoc #t~ite47; [L754] 0 havoc #t~ite50; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L755] 0 #t~ite56 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite56=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 ~x$r_buff1_thd2~0 := #t~ite56; [L755] 0 havoc #t~ite53; [L755] 0 havoc #t~ite51; [L755] 0 havoc #t~ite55; [L755] 0 havoc #t~ite52; [L755] 0 havoc #t~ite56; [L755] 0 havoc #t~ite54; [L756] 0 ~__unbuffered_p1_EAX$read_delayed~0 := 1; [L757] 0 ~__unbuffered_p1_EAX$read_delayed_var~0 := ~#x~0; [L758] FCALL 0 call #t~mem57 := read~int(~#x~0, 4); [L758] 0 ~__unbuffered_p1_EAX~0 := #t~mem57; [L758] 0 havoc #t~mem57; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] COND TRUE 0 0 != ~x$flush_delayed~0 % 256 [L759] 0 #t~ite59 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite59=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] FCALL 0 call write~int(#t~ite59, ~#x~0, 4); [L759] 0 havoc #t~ite59; [L759] 0 havoc #t~mem58; [L760] 0 ~x$flush_delayed~0 := 0; [L763] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L713-L740] 1 ~arg := #in~arg; [L716] 1 ~__unbuffered_p0_EAX~0 := ~y~0; [L719] 1 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 1 ~x$w_buff0~0 := 1; [L721] 1 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 1 ~x$w_buff0_used~0 := 1; [L723] 1 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 1 havoc __VERIFIER_assert_~expression; [L4] 1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] COND FALSE 1 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] COND FALSE 0 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L766] FCALL 0 call #t~mem60 := read~int(~#x~0, 4); [L766] 0 #t~ite61 := #t~mem60; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L724] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 1 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 1 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 1 ~x$r_buff0_thd1~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] COND TRUE 1 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L730] 1 #t~ite5 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 #t~ite62 := #t~ite61; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, #t~ite61=0, #t~ite62=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] FCALL 0 call write~int(#t~ite62, ~#x~0, 4); [L766] 0 havoc #t~ite62; [L766] 0 havoc #t~ite61; [L766] 0 havoc #t~mem60; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] FCALL 1 call write~int(#t~ite5, ~#x~0, 4); [L730] 1 havoc #t~ite4; [L730] 1 havoc #t~ite5; [L730] 1 havoc #t~mem3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L767] 0 #t~ite63 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite63=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 ~x$w_buff0_used~0 := #t~ite63; [L767] 0 havoc #t~ite63; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L768] 0 #t~ite64 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite64=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 ~x$w_buff1_used~0 := #t~ite64; [L768] 0 havoc #t~ite64; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L769] 0 #t~ite65 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite65=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 ~x$r_buff0_thd2~0 := #t~ite65; [L769] 0 havoc #t~ite65; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L770] 0 #t~ite66 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite66=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 ~x$r_buff1_thd2~0 := #t~ite66; [L770] 0 havoc #t~ite66; [L773] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] COND TRUE 1 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L731] 1 #t~ite6 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 ~x$w_buff0_used~0 := #t~ite6; [L731] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L732] 1 #t~ite7 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 ~x$w_buff1_used~0 := #t~ite7; [L732] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L733] 1 #t~ite8 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 ~x$r_buff0_thd1~0 := #t~ite8; [L733] 1 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L734] 1 #t~ite9 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite9=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 ~x$r_buff1_thd1~0 := #t~ite9; [L734] 1 havoc #t~ite9; [L737] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L791] -1 havoc main_#t~nondet69; [L793] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L795] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L797] FCALL -1 call main_#t~mem70 := read~int(~#x~0, 4); [L797] -1 main_#t~ite71 := main_#t~mem70; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~mem70=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 main_#t~ite72 := main_#t~ite71; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~ite72=1, main_#t~mem70=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] FCALL -1 call write~int(main_#t~ite72, ~#x~0, 4); [L797] -1 havoc main_#t~ite71; [L797] -1 havoc main_#t~ite72; [L797] -1 havoc main_#t~mem70; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L798] -1 main_#t~ite73 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite73=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 ~x$w_buff0_used~0 := main_#t~ite73; [L798] -1 havoc main_#t~ite73; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L799] -1 main_#t~ite74 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite74=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 ~x$w_buff1_used~0 := main_#t~ite74; [L799] -1 havoc main_#t~ite74; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L800] -1 main_#t~ite75 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite75=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 ~x$r_buff0_thd0~0 := main_#t~ite75; [L800] -1 havoc main_#t~ite75; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L801] -1 main_#t~ite76 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite76=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 ~x$r_buff1_thd0~0 := main_#t~ite76; [L801] -1 havoc main_#t~ite76; [L804] -1 ~weak$$choice1~0 := (if 0 == main_#t~nondet77!base + main_#t~nondet77!offset then 0 else 1); [L804] -1 havoc main_#t~nondet77; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] COND TRUE -1 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256 VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] COND TRUE -1 0 != ~weak$$choice1~0 % 256 [L805] FCALL -1 call main_#t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0, 4); [L805] -1 main_#t~ite79 := main_#t~mem78; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~mem78=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 main_#t~ite80 := main_#t~ite79; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~ite80=1, main_#t~mem78=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 ~__unbuffered_p1_EAX~0 := main_#t~ite80; [L805] -1 havoc main_#t~ite80; [L805] -1 havoc main_#t~mem78; [L805] -1 havoc main_#t~ite79; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t2669~0!base=6, main_~#t2669~0!offset=0, main_~#t2670~0!base=5, main_~#t2670~0!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [L678] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L681] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L682] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L683] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L684] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L685] -1 ~__unbuffered_p1_EAX$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L686] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L687] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L688] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L689] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L690] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L691] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] FCALL -1 call ~#x~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] FCALL -1 call write~init~int(0, ~#x~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L694] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [L695] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [L696] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [L697] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [L698] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [L699] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [L700] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [L701] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [L702] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [L703] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0] [L704] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [L705] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [L706] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [L707] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [L709] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L710] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L711] -1 ~weak$$choice1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L712] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L788] FCALL -1 call ~#t2669~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FCALL -1 call write~int(0, ~#t2669~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 havoc #t~nondet68; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L790] FCALL -1 call ~#t2670~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FCALL -1 call write~int(1, ~#t2670~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L741-L776] 0 ~arg := #in~arg; [L744] 0 ~weak$$choice0~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L744] 0 havoc #t~nondet11; [L745] 0 ~weak$$choice2~0 := (if 0 == #t~nondet12!base + #t~nondet12!offset then 0 else 1); [L745] 0 havoc #t~nondet12; [L746] 0 ~x$flush_delayed~0 := ~weak$$choice2~0; [L747] FCALL 0 call #t~mem13 := read~int(~#x~0, 4); [L747] 0 ~x$mem_tmp~0 := #t~mem13; [L747] 0 havoc #t~mem13; [L748] 0 ~weak$$choice1~0 := (if 0 == #t~nondet14!base + #t~nondet14!offset then 0 else 1); [L748] 0 havoc #t~nondet14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] COND TRUE 0 0 == ~x$w_buff0_used~0 % 256 [L749] FCALL 0 call #t~mem15 := read~int(~#x~0, 4); [L749] 0 #t~ite25 := #t~mem15; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~mem15=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] FCALL 0 call write~int(#t~ite25, ~#x~0, 4); [L749] 0 havoc #t~ite25; [L749] 0 havoc #t~ite23; [L749] 0 havoc #t~ite22; [L749] 0 havoc #t~ite17; [L749] 0 havoc #t~mem15; [L749] 0 havoc #t~ite19; [L749] 0 havoc #t~ite18; [L749] 0 havoc #t~mem16; [L749] 0 havoc #t~ite21; [L749] 0 havoc #t~ite24; [L749] 0 havoc #t~mem20; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L750] 0 #t~ite30 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 ~x$w_buff0~0 := #t~ite30; [L750] 0 havoc #t~ite29; [L750] 0 havoc #t~ite30; [L750] 0 havoc #t~ite28; [L750] 0 havoc #t~ite27; [L750] 0 havoc #t~ite26; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L751] 0 #t~ite35 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 ~x$w_buff1~0 := #t~ite35; [L751] 0 havoc #t~ite32; [L751] 0 havoc #t~ite31; [L751] 0 havoc #t~ite33; [L751] 0 havoc #t~ite34; [L751] 0 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L752] 0 #t~ite40 := ~x$w_buff0_used~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite40=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1); [L752] 0 havoc #t~ite37; [L752] 0 havoc #t~ite36; [L752] 0 havoc #t~ite40; [L752] 0 havoc #t~ite39; [L752] 0 havoc #t~ite38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L753] 0 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite45=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 ~x$w_buff1_used~0 := #t~ite45; [L753] 0 havoc #t~ite41; [L753] 0 havoc #t~ite43; [L753] 0 havoc #t~ite45; [L753] 0 havoc #t~ite42; [L753] 0 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L754] 0 #t~ite50 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite50=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 ~x$r_buff0_thd2~0 := #t~ite50; [L754] 0 havoc #t~ite46; [L754] 0 havoc #t~ite49; [L754] 0 havoc #t~ite48; [L754] 0 havoc #t~ite47; [L754] 0 havoc #t~ite50; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L755] 0 #t~ite56 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite56=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 ~x$r_buff1_thd2~0 := #t~ite56; [L755] 0 havoc #t~ite53; [L755] 0 havoc #t~ite51; [L755] 0 havoc #t~ite55; [L755] 0 havoc #t~ite52; [L755] 0 havoc #t~ite56; [L755] 0 havoc #t~ite54; [L756] 0 ~__unbuffered_p1_EAX$read_delayed~0 := 1; [L757] 0 ~__unbuffered_p1_EAX$read_delayed_var~0 := ~#x~0; [L758] FCALL 0 call #t~mem57 := read~int(~#x~0, 4); [L758] 0 ~__unbuffered_p1_EAX~0 := #t~mem57; [L758] 0 havoc #t~mem57; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] COND TRUE 0 0 != ~x$flush_delayed~0 % 256 [L759] 0 #t~ite59 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite59=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] FCALL 0 call write~int(#t~ite59, ~#x~0, 4); [L759] 0 havoc #t~ite59; [L759] 0 havoc #t~mem58; [L760] 0 ~x$flush_delayed~0 := 0; [L763] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L713-L740] 1 ~arg := #in~arg; [L716] 1 ~__unbuffered_p0_EAX~0 := ~y~0; [L719] 1 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 1 ~x$w_buff0~0 := 1; [L721] 1 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 1 ~x$w_buff0_used~0 := 1; [L4] 1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] COND FALSE 1 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] COND FALSE 0 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L766] FCALL 0 call #t~mem60 := read~int(~#x~0, 4); [L766] 0 #t~ite61 := #t~mem60; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L724] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 1 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 1 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 1 ~x$r_buff0_thd1~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] COND TRUE 1 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L730] 1 #t~ite5 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 #t~ite62 := #t~ite61; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~ite62=0, #t~mem60=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] FCALL 0 call write~int(#t~ite62, ~#x~0, 4); [L766] 0 havoc #t~ite62; [L766] 0 havoc #t~ite61; [L766] 0 havoc #t~mem60; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] FCALL 1 call write~int(#t~ite5, ~#x~0, 4); [L730] 1 havoc #t~ite4; [L730] 1 havoc #t~ite5; [L730] 1 havoc #t~mem3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L767] 0 #t~ite63 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite63=1, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 ~x$w_buff0_used~0 := #t~ite63; [L767] 0 havoc #t~ite63; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L768] 0 #t~ite64 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite64=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 ~x$w_buff1_used~0 := #t~ite64; [L768] 0 havoc #t~ite64; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L769] 0 #t~ite65 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite65=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 ~x$r_buff0_thd2~0 := #t~ite65; [L769] 0 havoc #t~ite65; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L770] 0 #t~ite66 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite66=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 ~x$r_buff1_thd2~0 := #t~ite66; [L770] 0 havoc #t~ite66; [L773] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] COND TRUE 1 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L731] 1 #t~ite6 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 ~x$w_buff0_used~0 := #t~ite6; [L731] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L732] 1 #t~ite7 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 ~x$w_buff1_used~0 := #t~ite7; [L732] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L733] 1 #t~ite8 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 ~x$r_buff0_thd1~0 := #t~ite8; [L733] 1 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L734] 1 #t~ite9 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 ~x$r_buff1_thd1~0 := #t~ite9; [L734] 1 havoc #t~ite9; [L737] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L791] -1 havoc #t~nondet69; [L793] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L795] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L797] FCALL -1 call #t~mem70 := read~int(~#x~0, 4); [L797] -1 #t~ite71 := #t~mem70; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 #t~ite72 := #t~ite71; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] FCALL -1 call write~int(#t~ite72, ~#x~0, 4); [L797] -1 havoc #t~ite71; [L797] -1 havoc #t~ite72; [L797] -1 havoc #t~mem70; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L798] -1 #t~ite73 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 ~x$w_buff0_used~0 := #t~ite73; [L798] -1 havoc #t~ite73; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L799] -1 #t~ite74 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 ~x$w_buff1_used~0 := #t~ite74; [L799] -1 havoc #t~ite74; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L800] -1 #t~ite75 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 ~x$r_buff0_thd0~0 := #t~ite75; [L800] -1 havoc #t~ite75; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L801] -1 #t~ite76 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 ~x$r_buff1_thd0~0 := #t~ite76; [L801] -1 havoc #t~ite76; [L804] -1 ~weak$$choice1~0 := (if 0 == #t~nondet77!base + #t~nondet77!offset then 0 else 1); [L804] -1 havoc #t~nondet77; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] COND TRUE -1 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] COND TRUE -1 0 != ~weak$$choice1~0 % 256 [L805] FCALL -1 call #t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0, 4); [L805] -1 #t~ite79 := #t~mem78; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 #t~ite80 := #t~ite79; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 ~__unbuffered_p1_EAX~0 := #t~ite80; [L805] -1 havoc #t~ite80; [L805] -1 havoc #t~mem78; [L805] -1 havoc #t~ite79; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [L678] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L681] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L682] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L683] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L684] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L685] -1 ~__unbuffered_p1_EAX$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L686] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L687] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L688] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L689] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L690] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L691] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] FCALL -1 call ~#x~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] FCALL -1 call write~init~int(0, ~#x~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L694] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [L695] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [L696] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [L697] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [L698] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [L699] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [L700] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [L701] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [L702] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [L703] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0] [L704] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [L705] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [L706] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [L707] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [L709] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L710] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L711] -1 ~weak$$choice1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L712] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L788] FCALL -1 call ~#t2669~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FCALL -1 call write~int(0, ~#t2669~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 havoc #t~nondet68; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L790] FCALL -1 call ~#t2670~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FCALL -1 call write~int(1, ~#t2670~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L741-L776] 0 ~arg := #in~arg; [L744] 0 ~weak$$choice0~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L744] 0 havoc #t~nondet11; [L745] 0 ~weak$$choice2~0 := (if 0 == #t~nondet12!base + #t~nondet12!offset then 0 else 1); [L745] 0 havoc #t~nondet12; [L746] 0 ~x$flush_delayed~0 := ~weak$$choice2~0; [L747] FCALL 0 call #t~mem13 := read~int(~#x~0, 4); [L747] 0 ~x$mem_tmp~0 := #t~mem13; [L747] 0 havoc #t~mem13; [L748] 0 ~weak$$choice1~0 := (if 0 == #t~nondet14!base + #t~nondet14!offset then 0 else 1); [L748] 0 havoc #t~nondet14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] COND TRUE 0 0 == ~x$w_buff0_used~0 % 256 [L749] FCALL 0 call #t~mem15 := read~int(~#x~0, 4); [L749] 0 #t~ite25 := #t~mem15; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~mem15=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] FCALL 0 call write~int(#t~ite25, ~#x~0, 4); [L749] 0 havoc #t~ite25; [L749] 0 havoc #t~ite23; [L749] 0 havoc #t~ite22; [L749] 0 havoc #t~ite17; [L749] 0 havoc #t~mem15; [L749] 0 havoc #t~ite19; [L749] 0 havoc #t~ite18; [L749] 0 havoc #t~mem16; [L749] 0 havoc #t~ite21; [L749] 0 havoc #t~ite24; [L749] 0 havoc #t~mem20; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L750] 0 #t~ite30 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 ~x$w_buff0~0 := #t~ite30; [L750] 0 havoc #t~ite29; [L750] 0 havoc #t~ite30; [L750] 0 havoc #t~ite28; [L750] 0 havoc #t~ite27; [L750] 0 havoc #t~ite26; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L751] 0 #t~ite35 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 ~x$w_buff1~0 := #t~ite35; [L751] 0 havoc #t~ite32; [L751] 0 havoc #t~ite31; [L751] 0 havoc #t~ite33; [L751] 0 havoc #t~ite34; [L751] 0 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L752] 0 #t~ite40 := ~x$w_buff0_used~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite40=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1); [L752] 0 havoc #t~ite37; [L752] 0 havoc #t~ite36; [L752] 0 havoc #t~ite40; [L752] 0 havoc #t~ite39; [L752] 0 havoc #t~ite38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L753] 0 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite45=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 ~x$w_buff1_used~0 := #t~ite45; [L753] 0 havoc #t~ite41; [L753] 0 havoc #t~ite43; [L753] 0 havoc #t~ite45; [L753] 0 havoc #t~ite42; [L753] 0 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L754] 0 #t~ite50 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite50=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 ~x$r_buff0_thd2~0 := #t~ite50; [L754] 0 havoc #t~ite46; [L754] 0 havoc #t~ite49; [L754] 0 havoc #t~ite48; [L754] 0 havoc #t~ite47; [L754] 0 havoc #t~ite50; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L755] 0 #t~ite56 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite56=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 ~x$r_buff1_thd2~0 := #t~ite56; [L755] 0 havoc #t~ite53; [L755] 0 havoc #t~ite51; [L755] 0 havoc #t~ite55; [L755] 0 havoc #t~ite52; [L755] 0 havoc #t~ite56; [L755] 0 havoc #t~ite54; [L756] 0 ~__unbuffered_p1_EAX$read_delayed~0 := 1; [L757] 0 ~__unbuffered_p1_EAX$read_delayed_var~0 := ~#x~0; [L758] FCALL 0 call #t~mem57 := read~int(~#x~0, 4); [L758] 0 ~__unbuffered_p1_EAX~0 := #t~mem57; [L758] 0 havoc #t~mem57; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] COND TRUE 0 0 != ~x$flush_delayed~0 % 256 [L759] 0 #t~ite59 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite59=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] FCALL 0 call write~int(#t~ite59, ~#x~0, 4); [L759] 0 havoc #t~ite59; [L759] 0 havoc #t~mem58; [L760] 0 ~x$flush_delayed~0 := 0; [L763] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L713-L740] 1 ~arg := #in~arg; [L716] 1 ~__unbuffered_p0_EAX~0 := ~y~0; [L719] 1 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 1 ~x$w_buff0~0 := 1; [L721] 1 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 1 ~x$w_buff0_used~0 := 1; [L4] 1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] COND FALSE 1 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] COND FALSE 0 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L766] FCALL 0 call #t~mem60 := read~int(~#x~0, 4); [L766] 0 #t~ite61 := #t~mem60; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L724] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 1 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 1 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 1 ~x$r_buff0_thd1~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] COND TRUE 1 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L730] 1 #t~ite5 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 #t~ite62 := #t~ite61; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~ite62=0, #t~mem60=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] FCALL 0 call write~int(#t~ite62, ~#x~0, 4); [L766] 0 havoc #t~ite62; [L766] 0 havoc #t~ite61; [L766] 0 havoc #t~mem60; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] FCALL 1 call write~int(#t~ite5, ~#x~0, 4); [L730] 1 havoc #t~ite4; [L730] 1 havoc #t~ite5; [L730] 1 havoc #t~mem3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L767] 0 #t~ite63 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite63=1, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 ~x$w_buff0_used~0 := #t~ite63; [L767] 0 havoc #t~ite63; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L768] 0 #t~ite64 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite64=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 ~x$w_buff1_used~0 := #t~ite64; [L768] 0 havoc #t~ite64; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L769] 0 #t~ite65 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite65=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 ~x$r_buff0_thd2~0 := #t~ite65; [L769] 0 havoc #t~ite65; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L770] 0 #t~ite66 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite66=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 ~x$r_buff1_thd2~0 := #t~ite66; [L770] 0 havoc #t~ite66; [L773] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] COND TRUE 1 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L731] 1 #t~ite6 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 ~x$w_buff0_used~0 := #t~ite6; [L731] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L732] 1 #t~ite7 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 ~x$w_buff1_used~0 := #t~ite7; [L732] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L733] 1 #t~ite8 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 ~x$r_buff0_thd1~0 := #t~ite8; [L733] 1 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L734] 1 #t~ite9 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 ~x$r_buff1_thd1~0 := #t~ite9; [L734] 1 havoc #t~ite9; [L737] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L791] -1 havoc #t~nondet69; [L793] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L795] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L797] FCALL -1 call #t~mem70 := read~int(~#x~0, 4); [L797] -1 #t~ite71 := #t~mem70; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 #t~ite72 := #t~ite71; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] FCALL -1 call write~int(#t~ite72, ~#x~0, 4); [L797] -1 havoc #t~ite71; [L797] -1 havoc #t~ite72; [L797] -1 havoc #t~mem70; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L798] -1 #t~ite73 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 ~x$w_buff0_used~0 := #t~ite73; [L798] -1 havoc #t~ite73; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L799] -1 #t~ite74 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 ~x$w_buff1_used~0 := #t~ite74; [L799] -1 havoc #t~ite74; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L800] -1 #t~ite75 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 ~x$r_buff0_thd0~0 := #t~ite75; [L800] -1 havoc #t~ite75; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L801] -1 #t~ite76 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 ~x$r_buff1_thd0~0 := #t~ite76; [L801] -1 havoc #t~ite76; [L804] -1 ~weak$$choice1~0 := (if 0 == #t~nondet77!base + #t~nondet77!offset then 0 else 1); [L804] -1 havoc #t~nondet77; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] COND TRUE -1 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] COND TRUE -1 0 != ~weak$$choice1~0 % 256 [L805] FCALL -1 call #t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0, 4); [L805] -1 #t~ite79 := #t~mem78; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 #t~ite80 := #t~ite79; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 ~__unbuffered_p1_EAX~0 := #t~ite80; [L805] -1 havoc #t~ite80; [L805] -1 havoc #t~mem78; [L805] -1 havoc #t~ite79; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=7, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=7, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p0_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0] [L675] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0] [L676] -1 _Bool __unbuffered_p1_EAX$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0] [L677] -1 int __unbuffered_p1_EAX$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0] [L678] -1 _Bool __unbuffered_p1_EAX$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0] [L679] -1 _Bool __unbuffered_p1_EAX$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0] [L680] -1 _Bool __unbuffered_p1_EAX$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0] [L681] -1 _Bool __unbuffered_p1_EAX$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0] [L682] -1 _Bool __unbuffered_p1_EAX$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0] [L683] -1 _Bool __unbuffered_p1_EAX$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0] [L684] -1 _Bool __unbuffered_p1_EAX$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0] [L685] -1 int *__unbuffered_p1_EAX$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}] [L686] -1 int __unbuffered_p1_EAX$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0] [L687] -1 _Bool __unbuffered_p1_EAX$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0] [L688] -1 int __unbuffered_p1_EAX$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0] [L689] -1 _Bool __unbuffered_p1_EAX$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0] [L690] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0] [L691] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0] [L693] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}] [L694] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0] [L695] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0] [L696] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L697] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L698] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L699] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L700] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L701] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L702] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L703] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L704] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L705] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L706] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L707] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L709] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L710] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L711] -1 _Bool weak$$choice1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L712] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L788] -1 pthread_t t2669; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L789] FCALL, FORK -1 pthread_create(&t2669, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L790] -1 pthread_t t2670; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L791] FCALL, FORK -1 pthread_create(&t2670, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L744] 0 weak$$choice0 = __VERIFIER_nondet_pointer() [L745] 0 weak$$choice2 = __VERIFIER_nondet_pointer() [L746] 0 x$flush_delayed = weak$$choice2 [L747] EXPR 0 \read(x) [L747] 0 x$mem_tmp = x [L748] 0 weak$$choice1 = __VERIFIER_nondet_pointer() [L749] EXPR 0 !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) [L749] EXPR 0 \read(x) [L749] EXPR 0 !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) VAL [!x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x))))=0, \read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L749] 0 x = !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) [L750] EXPR 0 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0))))=0, x={7:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L750] 0 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)))) [L751] EXPR 0 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1))))=0, x={7:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L751] 0 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)))) [L752] EXPR 0 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0))))=0, x={7:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L752] 0 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0)))) [L753] EXPR 0 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))))=0, x={7:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L753] 0 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L754] EXPR 0 weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))))=0, x={7:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L754] 0 x$r_buff0_thd2 = weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L755] EXPR 0 weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))))=0, x={7:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L755] 0 x$r_buff1_thd2 = weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L756] 0 __unbuffered_p1_EAX$read_delayed = (_Bool)1 [L757] 0 __unbuffered_p1_EAX$read_delayed_var = &x [L758] EXPR 0 \read(x) [L758] 0 __unbuffered_p1_EAX = x [L759] EXPR 0 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=1, x$flush_delayed ? x$mem_tmp : x=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L759] 0 x = x$flush_delayed ? x$mem_tmp : x [L760] 0 x$flush_delayed = (_Bool)0 [L763] 0 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L766] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L716] 1 __unbuffered_p0_EAX = y [L719] 1 x$w_buff1 = x$w_buff0 [L720] 1 x$w_buff0 = 1 [L721] 1 x$w_buff1_used = x$w_buff0_used [L722] 1 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 1 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L766] EXPR 0 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x [L766] EXPR 0 \read(x) [L766] EXPR 0 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L724] 1 x$r_buff1_thd0 = x$r_buff0_thd0 [L725] 1 x$r_buff1_thd1 = x$r_buff0_thd1 [L726] 1 x$r_buff1_thd2 = x$r_buff0_thd2 [L727] 1 x$r_buff0_thd1 = (_Bool)1 VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L730] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L766] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x)=0, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L766] 0 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L730] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L767] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L767] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L768] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L768] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L769] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L769] 0 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L770] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L770] 0 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L773] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L731] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L731] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L732] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L732] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L733] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L733] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L734] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L734] 1 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L737] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L793] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x [L797] EXPR -1 \read(x) [L797] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L798] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L798] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L799] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L799] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L800] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L800] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L801] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L801] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L804] -1 weak$$choice1 = __VERIFIER_nondet_pointer() [L805] EXPR -1 __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L805] EXPR -1 weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX [L805] EXPR -1 \read(*__unbuffered_p1_EAX$read_delayed_var) [L805] EXPR -1 weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L805] EXPR -1 __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L805] -1 __unbuffered_p1_EAX = __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX [L806] -1 main$tmp_guard1 = !(__unbuffered_p0_EAX == 1 && __unbuffered_p1_EAX == 1) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] ----- [2018-11-23 03:31:48,110 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_68853c4d-c738-42b3-b062-41fa6f6ad7ab/bin-2019/uautomizer/witness.graphml [2018-11-23 03:31:48,110 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 03:31:48,111 INFO L168 Benchmark]: Toolchain (without parser) took 72281.78 ms. Allocated memory was 1.0 GB in the beginning and 5.2 GB in the end (delta: 4.2 GB). Free memory was 956.4 MB in the beginning and 1.5 GB in the end (delta: -584.0 MB). Peak memory consumption was 3.6 GB. Max. memory is 11.5 GB. [2018-11-23 03:31:48,112 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 03:31:48,112 INFO L168 Benchmark]: CACSL2BoogieTranslator took 435.02 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 147.8 MB). Free memory was 956.4 MB in the beginning and 1.1 GB in the end (delta: -165.4 MB). Peak memory consumption was 38.5 MB. Max. memory is 11.5 GB. [2018-11-23 03:31:48,112 INFO L168 Benchmark]: Boogie Procedure Inliner took 34.47 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 03:31:48,112 INFO L168 Benchmark]: Boogie Preprocessor took 22.68 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. [2018-11-23 03:31:48,112 INFO L168 Benchmark]: RCFGBuilder took 587.44 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 65.1 MB). Peak memory consumption was 65.1 MB. Max. memory is 11.5 GB. [2018-11-23 03:31:48,113 INFO L168 Benchmark]: TraceAbstraction took 59134.15 ms. Allocated memory was 1.2 GB in the beginning and 5.2 GB in the end (delta: 4.1 GB). Free memory was 1.1 GB in the beginning and 1.8 GB in the end (delta: -731.5 MB). Peak memory consumption was 3.3 GB. Max. memory is 11.5 GB. [2018-11-23 03:31:48,113 INFO L168 Benchmark]: Witness Printer took 12064.80 ms. Allocated memory is still 5.2 GB. Free memory was 1.8 GB in the beginning and 1.5 GB in the end (delta: 244.5 MB). Peak memory consumption was 244.5 MB. Max. memory is 11.5 GB. [2018-11-23 03:31:48,114 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 435.02 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 147.8 MB). Free memory was 956.4 MB in the beginning and 1.1 GB in the end (delta: -165.4 MB). Peak memory consumption was 38.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 34.47 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 22.68 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. * RCFGBuilder took 587.44 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 65.1 MB). Peak memory consumption was 65.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 59134.15 ms. Allocated memory was 1.2 GB in the beginning and 5.2 GB in the end (delta: 4.1 GB). Free memory was 1.1 GB in the beginning and 1.8 GB in the end (delta: -731.5 MB). Peak memory consumption was 3.3 GB. Max. memory is 11.5 GB. * Witness Printer took 12064.80 ms. Allocated memory is still 5.2 GB. Free memory was 1.8 GB in the beginning and 1.5 GB in the end (delta: 244.5 MB). Peak memory consumption was 244.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p0_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0] [L675] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0] [L676] -1 _Bool __unbuffered_p1_EAX$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0] [L677] -1 int __unbuffered_p1_EAX$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0] [L678] -1 _Bool __unbuffered_p1_EAX$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0] [L679] -1 _Bool __unbuffered_p1_EAX$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0] [L680] -1 _Bool __unbuffered_p1_EAX$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0] [L681] -1 _Bool __unbuffered_p1_EAX$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0] [L682] -1 _Bool __unbuffered_p1_EAX$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0] [L683] -1 _Bool __unbuffered_p1_EAX$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0] [L684] -1 _Bool __unbuffered_p1_EAX$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0] [L685] -1 int *__unbuffered_p1_EAX$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}] [L686] -1 int __unbuffered_p1_EAX$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0] [L687] -1 _Bool __unbuffered_p1_EAX$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0] [L688] -1 int __unbuffered_p1_EAX$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0] [L689] -1 _Bool __unbuffered_p1_EAX$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0] [L690] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0] [L691] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0] [L693] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}] [L694] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0] [L695] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0] [L696] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L697] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L698] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L699] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L700] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L701] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L702] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L703] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L704] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L705] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L706] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L707] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L709] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L710] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L711] -1 _Bool weak$$choice1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L712] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L788] -1 pthread_t t2669; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L789] FCALL, FORK -1 pthread_create(&t2669, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L790] -1 pthread_t t2670; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L791] FCALL, FORK -1 pthread_create(&t2670, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L744] 0 weak$$choice0 = __VERIFIER_nondet_pointer() [L745] 0 weak$$choice2 = __VERIFIER_nondet_pointer() [L746] 0 x$flush_delayed = weak$$choice2 [L747] EXPR 0 \read(x) [L747] 0 x$mem_tmp = x [L748] 0 weak$$choice1 = __VERIFIER_nondet_pointer() [L749] EXPR 0 !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) [L749] EXPR 0 \read(x) [L749] EXPR 0 !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) VAL [!x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x))))=0, \read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L749] 0 x = !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) [L750] EXPR 0 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0))))=0, x={7:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L750] 0 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)))) [L751] EXPR 0 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1))))=0, x={7:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L751] 0 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)))) [L752] EXPR 0 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0))))=0, x={7:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L752] 0 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0)))) [L753] EXPR 0 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))))=0, x={7:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L753] 0 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L754] EXPR 0 weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))))=0, x={7:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L754] 0 x$r_buff0_thd2 = weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L755] EXPR 0 weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))))=0, x={7:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L755] 0 x$r_buff1_thd2 = weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L756] 0 __unbuffered_p1_EAX$read_delayed = (_Bool)1 [L757] 0 __unbuffered_p1_EAX$read_delayed_var = &x [L758] EXPR 0 \read(x) [L758] 0 __unbuffered_p1_EAX = x [L759] EXPR 0 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=1, x$flush_delayed ? x$mem_tmp : x=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L759] 0 x = x$flush_delayed ? x$mem_tmp : x [L760] 0 x$flush_delayed = (_Bool)0 [L763] 0 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L766] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L716] 1 __unbuffered_p0_EAX = y [L719] 1 x$w_buff1 = x$w_buff0 [L720] 1 x$w_buff0 = 1 [L721] 1 x$w_buff1_used = x$w_buff0_used [L722] 1 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 1 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L766] EXPR 0 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x [L766] EXPR 0 \read(x) [L766] EXPR 0 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L724] 1 x$r_buff1_thd0 = x$r_buff0_thd0 [L725] 1 x$r_buff1_thd1 = x$r_buff0_thd1 [L726] 1 x$r_buff1_thd2 = x$r_buff0_thd2 [L727] 1 x$r_buff0_thd1 = (_Bool)1 VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L730] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L766] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x)=0, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L766] 0 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L730] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L767] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L767] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L768] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L768] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L769] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L769] 0 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L770] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L770] 0 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L773] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L731] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L731] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L732] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L732] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L733] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L733] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L734] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L734] 1 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L737] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L793] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x [L797] EXPR -1 \read(x) [L797] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L798] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L798] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L799] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L799] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L800] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L800] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L801] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L801] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L804] -1 weak$$choice1 = __VERIFIER_nondet_pointer() [L805] EXPR -1 __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L805] EXPR -1 weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX [L805] EXPR -1 \read(*__unbuffered_p1_EAX$read_delayed_var) [L805] EXPR -1 weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L805] EXPR -1 __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L805] -1 __unbuffered_p1_EAX = __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX [L806] -1 main$tmp_guard1 = !(__unbuffered_p0_EAX == 1 && __unbuffered_p1_EAX == 1) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 318 locations, 3 error locations. UNSAFE Result, 59.0s OverallTime, 38 OverallIterations, 1 TraceHistogramMax, 22.2s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 13341 SDtfs, 17579 SDslu, 32160 SDs, 0 SdLazy, 13171 SolverSat, 1113 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 7.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 418 GetRequests, 91 SyntacticMatches, 28 SemanticMatches, 299 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 974 ImplicationChecksByTransitivity, 3.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=162964occurred in iteration=8, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 23.8s AutomataMinimizationTime, 37 MinimizatonAttempts, 368614 StatesRemovedByMinimization, 33 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 2.7s InterpolantComputationTime, 3480 NumberOfCodeBlocks, 3480 NumberOfCodeBlocksAsserted, 38 NumberOfCheckSat, 3328 ConstructedInterpolants, 0 QuantifiedInterpolants, 912691 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 37 InterpolantComputations, 37 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...