./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.05_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.05_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 8ef5d3a30c95e1a42cc229ca801f47c5cf92951a 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 16:09:33,505 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 16:09:33,506 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 16:09:33,512 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 16:09:33,513 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 16:09:33,513 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 16:09:33,514 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 16:09:33,515 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 16:09:33,516 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 16:09:33,517 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 16:09:33,517 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 16:09:33,518 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 16:09:33,518 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 16:09:33,519 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 16:09:33,520 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 16:09:33,520 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 16:09:33,521 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 16:09:33,522 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 16:09:33,523 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 16:09:33,524 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 16:09:33,525 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 16:09:33,526 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 16:09:33,527 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 16:09:33,527 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 16:09:33,528 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 16:09:33,528 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 16:09:33,529 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 16:09:33,529 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 16:09:33,530 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 16:09:33,531 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 16:09:33,531 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 16:09:33,531 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 16:09:33,531 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 16:09:33,532 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 16:09:33,532 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 16:09:33,533 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 16:09:33,533 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-23 16:09:33,542 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 16:09:33,542 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 16:09:33,543 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 16:09:33,543 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 16:09:33,543 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 16:09:33,543 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 16:09:33,543 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 16:09:33,544 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 16:09:33,544 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 16:09:33,544 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 16:09:33,544 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 16:09:33,544 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 16:09:33,544 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 16:09:33,544 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 16:09:33,545 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 16:09:33,545 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 16:09:33,545 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 16:09:33,545 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 16:09:33,545 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 16:09:33,545 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 16:09:33,545 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 16:09:33,545 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 16:09:33,546 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 16:09:33,546 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 16:09:33,546 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 16:09:33,546 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 16:09:33,546 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 16:09:33,546 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 16:09:33,546 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 16:09:33,547 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 16:09:33,547 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 8ef5d3a30c95e1a42cc229ca801f47c5cf92951a [2018-11-23 16:09:33,568 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 16:09:33,578 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 16:09:33,580 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 16:09:33,581 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 16:09:33,581 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 16:09:33,581 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.05_false-unreach-call_false-termination.cil.c [2018-11-23 16:09:33,616 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/data/77890031b/f4bfb37362cb4707a2a3295ff6055c53/FLAGf75372468 [2018-11-23 16:09:34,039 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 16:09:34,040 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/sv-benchmarks/c/systemc/transmitter.05_false-unreach-call_false-termination.cil.c [2018-11-23 16:09:34,045 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/data/77890031b/f4bfb37362cb4707a2a3295ff6055c53/FLAGf75372468 [2018-11-23 16:09:34,057 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/data/77890031b/f4bfb37362cb4707a2a3295ff6055c53 [2018-11-23 16:09:34,059 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 16:09:34,060 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 16:09:34,061 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 16:09:34,061 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 16:09:34,064 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 16:09:34,065 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 04:09:34" (1/1) ... [2018-11-23 16:09:34,067 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2ebf8353 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:09:34, skipping insertion in model container [2018-11-23 16:09:34,067 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 04:09:34" (1/1) ... [2018-11-23 16:09:34,075 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 16:09:34,104 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 16:09:34,272 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 16:09:34,276 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 16:09:34,306 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 16:09:34,317 INFO L195 MainTranslator]: Completed translation [2018-11-23 16:09:34,317 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:09:34 WrapperNode [2018-11-23 16:09:34,318 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 16:09:34,318 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 16:09:34,318 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 16:09:34,318 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 16:09:34,359 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:09:34" (1/1) ... [2018-11-23 16:09:34,367 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:09:34" (1/1) ... [2018-11-23 16:09:34,374 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 16:09:34,374 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 16:09:34,374 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 16:09:34,374 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 16:09:34,382 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:09:34" (1/1) ... [2018-11-23 16:09:34,382 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:09:34" (1/1) ... [2018-11-23 16:09:34,385 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:09:34" (1/1) ... [2018-11-23 16:09:34,385 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:09:34" (1/1) ... [2018-11-23 16:09:34,394 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:09:34" (1/1) ... [2018-11-23 16:09:34,405 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:09:34" (1/1) ... [2018-11-23 16:09:34,410 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:09:34" (1/1) ... [2018-11-23 16:09:34,413 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 16:09:34,414 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 16:09:34,414 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 16:09:34,414 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 16:09:34,414 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:09:34" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 16:09:34,451 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2018-11-23 16:09:34,452 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2018-11-23 16:09:34,452 INFO L130 BoogieDeclarations]: Found specification of procedure transmit3 [2018-11-23 16:09:34,452 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit3 [2018-11-23 16:09:34,452 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2018-11-23 16:09:34,452 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2018-11-23 16:09:34,452 INFO L130 BoogieDeclarations]: Found specification of procedure transmit5 [2018-11-23 16:09:34,452 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit5 [2018-11-23 16:09:34,452 INFO L130 BoogieDeclarations]: Found specification of procedure transmit4 [2018-11-23 16:09:34,452 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit4 [2018-11-23 16:09:34,452 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 16:09:34,453 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 16:09:34,453 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-11-23 16:09:34,453 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-11-23 16:09:34,453 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-11-23 16:09:34,453 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-11-23 16:09:34,453 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2018-11-23 16:09:34,453 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2018-11-23 16:09:34,453 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-11-23 16:09:34,453 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-11-23 16:09:34,454 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2018-11-23 16:09:34,454 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2018-11-23 16:09:34,454 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-11-23 16:09:34,454 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-11-23 16:09:34,454 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit4_triggered [2018-11-23 16:09:34,454 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit4_triggered [2018-11-23 16:09:34,454 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-11-23 16:09:34,454 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-11-23 16:09:34,454 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-11-23 16:09:34,455 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-11-23 16:09:34,455 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-11-23 16:09:34,455 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-11-23 16:09:34,455 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-11-23 16:09:34,455 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-11-23 16:09:34,455 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2018-11-23 16:09:34,455 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2018-11-23 16:09:34,455 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-11-23 16:09:34,455 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-11-23 16:09:34,456 INFO L130 BoogieDeclarations]: Found specification of procedure master [2018-11-23 16:09:34,456 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2018-11-23 16:09:34,456 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-11-23 16:09:34,456 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-11-23 16:09:34,456 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 16:09:34,456 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 16:09:34,456 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-11-23 16:09:34,456 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-11-23 16:09:34,456 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit3_triggered [2018-11-23 16:09:34,457 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit3_triggered [2018-11-23 16:09:34,457 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit5_triggered [2018-11-23 16:09:34,457 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit5_triggered [2018-11-23 16:09:34,457 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-11-23 16:09:34,457 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-11-23 16:09:34,457 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-11-23 16:09:34,457 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-11-23 16:09:34,457 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 16:09:34,457 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 16:09:34,457 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-11-23 16:09:34,458 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-11-23 16:09:34,936 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 16:09:34,936 INFO L280 CfgBuilder]: Removed 9 assue(true) statements. [2018-11-23 16:09:34,936 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 04:09:34 BoogieIcfgContainer [2018-11-23 16:09:34,936 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 16:09:34,937 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 16:09:34,937 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 16:09:34,939 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 16:09:34,940 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 04:09:34" (1/3) ... [2018-11-23 16:09:34,940 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@cb935a3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 04:09:34, skipping insertion in model container [2018-11-23 16:09:34,940 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:09:34" (2/3) ... [2018-11-23 16:09:34,940 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@cb935a3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 04:09:34, skipping insertion in model container [2018-11-23 16:09:34,941 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 04:09:34" (3/3) ... [2018-11-23 16:09:34,942 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.05_false-unreach-call_false-termination.cil.c [2018-11-23 16:09:34,947 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 16:09:34,952 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 16:09:34,961 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 16:09:34,980 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 16:09:34,980 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 16:09:34,981 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 16:09:34,981 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 16:09:34,981 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 16:09:34,981 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 16:09:34,981 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 16:09:34,981 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 16:09:34,981 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 16:09:34,998 INFO L276 IsEmpty]: Start isEmpty. Operand 259 states. [2018-11-23 16:09:35,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:35,007 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:35,008 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:35,009 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:35,012 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:35,012 INFO L82 PathProgramCache]: Analyzing trace with hash 1978768940, now seen corresponding path program 1 times [2018-11-23 16:09:35,013 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:35,014 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:35,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:35,049 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:35,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:35,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:35,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:35,232 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:35,233 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 16:09:35,236 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 16:09:35,244 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 16:09:35,244 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 16:09:35,246 INFO L87 Difference]: Start difference. First operand 259 states. Second operand 4 states. [2018-11-23 16:09:35,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:35,470 INFO L93 Difference]: Finished difference Result 499 states and 743 transitions. [2018-11-23 16:09:35,470 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 16:09:35,471 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 135 [2018-11-23 16:09:35,471 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:35,480 INFO L225 Difference]: With dead ends: 499 [2018-11-23 16:09:35,480 INFO L226 Difference]: Without dead ends: 250 [2018-11-23 16:09:35,484 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 16:09:35,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 250 states. [2018-11-23 16:09:35,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 250 to 250. [2018-11-23 16:09:35,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2018-11-23 16:09:35,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 350 transitions. [2018-11-23 16:09:35,540 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 350 transitions. Word has length 135 [2018-11-23 16:09:35,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:35,542 INFO L480 AbstractCegarLoop]: Abstraction has 250 states and 350 transitions. [2018-11-23 16:09:35,542 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 16:09:35,542 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 350 transitions. [2018-11-23 16:09:35,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:35,545 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:35,546 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:35,546 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:35,546 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:35,546 INFO L82 PathProgramCache]: Analyzing trace with hash -594195670, now seen corresponding path program 1 times [2018-11-23 16:09:35,547 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:35,547 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:35,548 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:35,548 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:35,548 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:35,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:35,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:35,665 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:35,665 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:35,667 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:35,667 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:35,667 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:35,667 INFO L87 Difference]: Start difference. First operand 250 states and 350 transitions. Second operand 5 states. [2018-11-23 16:09:36,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:36,065 INFO L93 Difference]: Finished difference Result 517 states and 744 transitions. [2018-11-23 16:09:36,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 16:09:36,066 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:36,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:36,069 INFO L225 Difference]: With dead ends: 517 [2018-11-23 16:09:36,069 INFO L226 Difference]: Without dead ends: 290 [2018-11-23 16:09:36,070 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:36,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 290 states. [2018-11-23 16:09:36,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 290 to 250. [2018-11-23 16:09:36,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2018-11-23 16:09:36,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 349 transitions. [2018-11-23 16:09:36,089 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 349 transitions. Word has length 135 [2018-11-23 16:09:36,089 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:36,089 INFO L480 AbstractCegarLoop]: Abstraction has 250 states and 349 transitions. [2018-11-23 16:09:36,089 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:36,089 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 349 transitions. [2018-11-23 16:09:36,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:36,092 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:36,092 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:36,092 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:36,092 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:36,092 INFO L82 PathProgramCache]: Analyzing trace with hash 1569420904, now seen corresponding path program 1 times [2018-11-23 16:09:36,093 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:36,093 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:36,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:36,094 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:36,094 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:36,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:36,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:36,198 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:36,199 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:36,199 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:36,199 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:36,199 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:36,200 INFO L87 Difference]: Start difference. First operand 250 states and 349 transitions. Second operand 5 states. [2018-11-23 16:09:36,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:36,566 INFO L93 Difference]: Finished difference Result 517 states and 743 transitions. [2018-11-23 16:09:36,566 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 16:09:36,566 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:36,566 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:36,568 INFO L225 Difference]: With dead ends: 517 [2018-11-23 16:09:36,569 INFO L226 Difference]: Without dead ends: 290 [2018-11-23 16:09:36,570 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:36,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 290 states. [2018-11-23 16:09:36,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 290 to 250. [2018-11-23 16:09:36,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2018-11-23 16:09:36,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 348 transitions. [2018-11-23 16:09:36,589 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 348 transitions. Word has length 135 [2018-11-23 16:09:36,589 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:36,589 INFO L480 AbstractCegarLoop]: Abstraction has 250 states and 348 transitions. [2018-11-23 16:09:36,590 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:36,590 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 348 transitions. [2018-11-23 16:09:36,591 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:36,591 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:36,591 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:36,591 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:36,592 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:36,592 INFO L82 PathProgramCache]: Analyzing trace with hash 530836330, now seen corresponding path program 1 times [2018-11-23 16:09:36,592 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:36,592 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:36,593 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:36,593 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:36,593 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:36,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:36,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:36,679 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:36,680 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:36,681 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:36,681 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:36,682 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:36,682 INFO L87 Difference]: Start difference. First operand 250 states and 348 transitions. Second operand 5 states. [2018-11-23 16:09:36,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:36,978 INFO L93 Difference]: Finished difference Result 515 states and 737 transitions. [2018-11-23 16:09:36,978 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 16:09:36,978 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:36,979 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:36,980 INFO L225 Difference]: With dead ends: 515 [2018-11-23 16:09:36,981 INFO L226 Difference]: Without dead ends: 288 [2018-11-23 16:09:36,981 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:36,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states. [2018-11-23 16:09:36,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 250. [2018-11-23 16:09:36,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2018-11-23 16:09:36,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 347 transitions. [2018-11-23 16:09:36,999 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 347 transitions. Word has length 135 [2018-11-23 16:09:37,000 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:37,000 INFO L480 AbstractCegarLoop]: Abstraction has 250 states and 347 transitions. [2018-11-23 16:09:37,000 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:37,000 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 347 transitions. [2018-11-23 16:09:37,001 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:37,001 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:37,002 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:37,002 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:37,002 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:37,002 INFO L82 PathProgramCache]: Analyzing trace with hash -1442329048, now seen corresponding path program 1 times [2018-11-23 16:09:37,002 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:37,002 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:37,003 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:37,003 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:37,003 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:37,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:37,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:37,089 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:37,089 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:37,090 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:37,090 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:37,090 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:37,090 INFO L87 Difference]: Start difference. First operand 250 states and 347 transitions. Second operand 5 states. [2018-11-23 16:09:37,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:37,413 INFO L93 Difference]: Finished difference Result 513 states and 731 transitions. [2018-11-23 16:09:37,414 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 16:09:37,414 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:37,414 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:37,415 INFO L225 Difference]: With dead ends: 513 [2018-11-23 16:09:37,415 INFO L226 Difference]: Without dead ends: 286 [2018-11-23 16:09:37,416 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:37,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 286 states. [2018-11-23 16:09:37,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 286 to 250. [2018-11-23 16:09:37,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2018-11-23 16:09:37,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 346 transitions. [2018-11-23 16:09:37,438 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 346 transitions. Word has length 135 [2018-11-23 16:09:37,439 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:37,439 INFO L480 AbstractCegarLoop]: Abstraction has 250 states and 346 transitions. [2018-11-23 16:09:37,439 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:37,439 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 346 transitions. [2018-11-23 16:09:37,440 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:37,440 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:37,440 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:37,441 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:37,441 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:37,442 INFO L82 PathProgramCache]: Analyzing trace with hash 710777770, now seen corresponding path program 1 times [2018-11-23 16:09:37,442 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:37,442 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:37,443 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:37,443 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:37,443 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:37,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:37,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:37,503 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:37,503 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:37,503 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:37,504 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:37,504 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:37,504 INFO L87 Difference]: Start difference. First operand 250 states and 346 transitions. Second operand 5 states. [2018-11-23 16:09:37,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:37,782 INFO L93 Difference]: Finished difference Result 511 states and 725 transitions. [2018-11-23 16:09:37,783 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 16:09:37,783 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:37,783 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:37,784 INFO L225 Difference]: With dead ends: 511 [2018-11-23 16:09:37,784 INFO L226 Difference]: Without dead ends: 284 [2018-11-23 16:09:37,785 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:37,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states. [2018-11-23 16:09:37,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 250. [2018-11-23 16:09:37,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2018-11-23 16:09:37,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 345 transitions. [2018-11-23 16:09:37,797 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 345 transitions. Word has length 135 [2018-11-23 16:09:37,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:37,797 INFO L480 AbstractCegarLoop]: Abstraction has 250 states and 345 transitions. [2018-11-23 16:09:37,797 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:37,797 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 345 transitions. [2018-11-23 16:09:37,798 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:37,799 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:37,799 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:37,799 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:37,799 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:37,799 INFO L82 PathProgramCache]: Analyzing trace with hash 87496168, now seen corresponding path program 1 times [2018-11-23 16:09:37,799 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:37,799 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:37,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:37,800 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:37,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:37,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:37,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:37,853 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:37,853 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:37,854 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:37,854 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:37,854 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:37,854 INFO L87 Difference]: Start difference. First operand 250 states and 345 transitions. Second operand 5 states. [2018-11-23 16:09:38,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:38,203 INFO L93 Difference]: Finished difference Result 509 states and 719 transitions. [2018-11-23 16:09:38,203 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 16:09:38,203 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:38,204 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:38,205 INFO L225 Difference]: With dead ends: 509 [2018-11-23 16:09:38,206 INFO L226 Difference]: Without dead ends: 282 [2018-11-23 16:09:38,207 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:38,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states. [2018-11-23 16:09:38,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 250. [2018-11-23 16:09:38,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2018-11-23 16:09:38,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 344 transitions. [2018-11-23 16:09:38,225 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 344 transitions. Word has length 135 [2018-11-23 16:09:38,226 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:38,227 INFO L480 AbstractCegarLoop]: Abstraction has 250 states and 344 transitions. [2018-11-23 16:09:38,227 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:38,227 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 344 transitions. [2018-11-23 16:09:38,229 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:38,230 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:38,230 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:38,230 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:38,230 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:38,230 INFO L82 PathProgramCache]: Analyzing trace with hash 205937642, now seen corresponding path program 1 times [2018-11-23 16:09:38,230 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:38,231 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:38,231 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:38,231 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:38,231 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:38,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:38,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:38,301 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:38,301 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:38,302 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:38,302 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:38,302 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:38,302 INFO L87 Difference]: Start difference. First operand 250 states and 344 transitions. Second operand 5 states. [2018-11-23 16:09:38,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:38,669 INFO L93 Difference]: Finished difference Result 535 states and 763 transitions. [2018-11-23 16:09:38,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 16:09:38,670 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:38,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:38,671 INFO L225 Difference]: With dead ends: 535 [2018-11-23 16:09:38,671 INFO L226 Difference]: Without dead ends: 308 [2018-11-23 16:09:38,672 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:38,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states. [2018-11-23 16:09:38,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 250. [2018-11-23 16:09:38,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2018-11-23 16:09:38,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 343 transitions. [2018-11-23 16:09:38,696 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 343 transitions. Word has length 135 [2018-11-23 16:09:38,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:38,696 INFO L480 AbstractCegarLoop]: Abstraction has 250 states and 343 transitions. [2018-11-23 16:09:38,696 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:38,696 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 343 transitions. [2018-11-23 16:09:38,698 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:38,698 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:38,698 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:38,698 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:38,699 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:38,699 INFO L82 PathProgramCache]: Analyzing trace with hash 1595231656, now seen corresponding path program 1 times [2018-11-23 16:09:38,699 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:38,699 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:38,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:38,700 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:38,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:38,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:38,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:38,836 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:38,836 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:38,837 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:38,838 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:38,838 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:38,838 INFO L87 Difference]: Start difference. First operand 250 states and 343 transitions. Second operand 5 states. [2018-11-23 16:09:39,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:39,123 INFO L93 Difference]: Finished difference Result 531 states and 753 transitions. [2018-11-23 16:09:39,123 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 16:09:39,123 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:39,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:39,125 INFO L225 Difference]: With dead ends: 531 [2018-11-23 16:09:39,125 INFO L226 Difference]: Without dead ends: 304 [2018-11-23 16:09:39,126 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:39,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 304 states. [2018-11-23 16:09:39,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 304 to 250. [2018-11-23 16:09:39,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2018-11-23 16:09:39,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 342 transitions. [2018-11-23 16:09:39,141 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 342 transitions. Word has length 135 [2018-11-23 16:09:39,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:39,142 INFO L480 AbstractCegarLoop]: Abstraction has 250 states and 342 transitions. [2018-11-23 16:09:39,142 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:39,142 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 342 transitions. [2018-11-23 16:09:39,143 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:39,143 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:39,143 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:39,143 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:39,143 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:39,143 INFO L82 PathProgramCache]: Analyzing trace with hash -271477018, now seen corresponding path program 1 times [2018-11-23 16:09:39,143 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:39,143 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:39,144 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:39,144 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:39,144 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:39,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:39,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:39,206 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:39,206 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:39,206 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:39,206 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:39,207 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:39,207 INFO L87 Difference]: Start difference. First operand 250 states and 342 transitions. Second operand 5 states. [2018-11-23 16:09:39,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:39,477 INFO L93 Difference]: Finished difference Result 529 states and 747 transitions. [2018-11-23 16:09:39,477 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 16:09:39,478 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:39,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:39,479 INFO L225 Difference]: With dead ends: 529 [2018-11-23 16:09:39,479 INFO L226 Difference]: Without dead ends: 302 [2018-11-23 16:09:39,480 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:39,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 302 states. [2018-11-23 16:09:39,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 302 to 250. [2018-11-23 16:09:39,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2018-11-23 16:09:39,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 341 transitions. [2018-11-23 16:09:39,502 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 341 transitions. Word has length 135 [2018-11-23 16:09:39,502 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:39,503 INFO L480 AbstractCegarLoop]: Abstraction has 250 states and 341 transitions. [2018-11-23 16:09:39,503 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:39,503 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 341 transitions. [2018-11-23 16:09:39,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:39,503 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:39,504 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:39,504 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:39,504 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:39,504 INFO L82 PathProgramCache]: Analyzing trace with hash -1578619416, now seen corresponding path program 1 times [2018-11-23 16:09:39,504 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:39,504 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:39,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:39,505 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:39,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:39,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:39,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:39,557 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:39,557 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:39,557 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:39,558 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:39,558 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:39,558 INFO L87 Difference]: Start difference. First operand 250 states and 341 transitions. Second operand 5 states. [2018-11-23 16:09:39,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:39,888 INFO L93 Difference]: Finished difference Result 527 states and 741 transitions. [2018-11-23 16:09:39,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 16:09:39,889 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:39,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:39,891 INFO L225 Difference]: With dead ends: 527 [2018-11-23 16:09:39,891 INFO L226 Difference]: Without dead ends: 300 [2018-11-23 16:09:39,891 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:39,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 300 states. [2018-11-23 16:09:39,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 300 to 250. [2018-11-23 16:09:39,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2018-11-23 16:09:39,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 340 transitions. [2018-11-23 16:09:39,914 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 340 transitions. Word has length 135 [2018-11-23 16:09:39,914 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:39,914 INFO L480 AbstractCegarLoop]: Abstraction has 250 states and 340 transitions. [2018-11-23 16:09:39,914 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:39,914 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 340 transitions. [2018-11-23 16:09:39,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:39,915 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:39,915 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:39,916 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:39,916 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:39,916 INFO L82 PathProgramCache]: Analyzing trace with hash 318877350, now seen corresponding path program 1 times [2018-11-23 16:09:39,916 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:39,916 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:39,917 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:39,917 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:39,917 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:39,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:39,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:39,971 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:39,971 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 16:09:39,971 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 16:09:39,971 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 16:09:39,971 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 16:09:39,973 INFO L87 Difference]: Start difference. First operand 250 states and 340 transitions. Second operand 4 states. [2018-11-23 16:09:40,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:40,177 INFO L93 Difference]: Finished difference Result 694 states and 977 transitions. [2018-11-23 16:09:40,178 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 16:09:40,178 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 135 [2018-11-23 16:09:40,178 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:40,179 INFO L225 Difference]: With dead ends: 694 [2018-11-23 16:09:40,179 INFO L226 Difference]: Without dead ends: 468 [2018-11-23 16:09:40,180 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 16:09:40,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 468 states. [2018-11-23 16:09:40,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 468 to 463. [2018-11-23 16:09:40,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2018-11-23 16:09:40,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 630 transitions. [2018-11-23 16:09:40,206 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 630 transitions. Word has length 135 [2018-11-23 16:09:40,206 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:40,206 INFO L480 AbstractCegarLoop]: Abstraction has 463 states and 630 transitions. [2018-11-23 16:09:40,206 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 16:09:40,206 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 630 transitions. [2018-11-23 16:09:40,207 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:40,207 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:40,207 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:40,207 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:40,207 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:40,207 INFO L82 PathProgramCache]: Analyzing trace with hash 1436062311, now seen corresponding path program 1 times [2018-11-23 16:09:40,207 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:40,207 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:40,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:40,208 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:40,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:40,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:40,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:40,252 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:40,252 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 16:09:40,252 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 16:09:40,252 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 16:09:40,253 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:40,253 INFO L87 Difference]: Start difference. First operand 463 states and 630 transitions. Second operand 6 states. [2018-11-23 16:09:40,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:40,299 INFO L93 Difference]: Finished difference Result 924 states and 1291 transitions. [2018-11-23 16:09:40,300 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:09:40,300 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 135 [2018-11-23 16:09:40,300 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:40,302 INFO L225 Difference]: With dead ends: 924 [2018-11-23 16:09:40,302 INFO L226 Difference]: Without dead ends: 485 [2018-11-23 16:09:40,304 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 16:09:40,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 485 states. [2018-11-23 16:09:40,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 485 to 468. [2018-11-23 16:09:40,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 468 states. [2018-11-23 16:09:40,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 468 states and 634 transitions. [2018-11-23 16:09:40,331 INFO L78 Accepts]: Start accepts. Automaton has 468 states and 634 transitions. Word has length 135 [2018-11-23 16:09:40,331 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:40,331 INFO L480 AbstractCegarLoop]: Abstraction has 468 states and 634 transitions. [2018-11-23 16:09:40,331 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 16:09:40,331 INFO L276 IsEmpty]: Start isEmpty. Operand 468 states and 634 transitions. [2018-11-23 16:09:40,332 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:40,332 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:40,332 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:40,332 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:40,332 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:40,333 INFO L82 PathProgramCache]: Analyzing trace with hash 849786089, now seen corresponding path program 1 times [2018-11-23 16:09:40,333 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:40,333 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:40,334 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:40,334 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:40,334 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:40,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:40,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:40,394 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:40,394 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 16:09:40,394 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 16:09:40,394 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 16:09:40,394 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 16:09:40,395 INFO L87 Difference]: Start difference. First operand 468 states and 634 transitions. Second operand 4 states. [2018-11-23 16:09:40,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:40,570 INFO L93 Difference]: Finished difference Result 1343 states and 1882 transitions. [2018-11-23 16:09:40,571 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 16:09:40,571 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 135 [2018-11-23 16:09:40,571 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:40,574 INFO L225 Difference]: With dead ends: 1343 [2018-11-23 16:09:40,574 INFO L226 Difference]: Without dead ends: 899 [2018-11-23 16:09:40,575 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 16:09:40,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 899 states. [2018-11-23 16:09:40,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 899 to 892. [2018-11-23 16:09:40,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 892 states. [2018-11-23 16:09:40,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 892 states to 892 states and 1207 transitions. [2018-11-23 16:09:40,620 INFO L78 Accepts]: Start accepts. Automaton has 892 states and 1207 transitions. Word has length 135 [2018-11-23 16:09:40,621 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:40,621 INFO L480 AbstractCegarLoop]: Abstraction has 892 states and 1207 transitions. [2018-11-23 16:09:40,621 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 16:09:40,621 INFO L276 IsEmpty]: Start isEmpty. Operand 892 states and 1207 transitions. [2018-11-23 16:09:40,621 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:40,622 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:40,622 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:40,622 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:40,622 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:40,622 INFO L82 PathProgramCache]: Analyzing trace with hash 394880008, now seen corresponding path program 1 times [2018-11-23 16:09:40,622 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:40,622 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:40,623 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:40,623 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:40,623 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:40,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:40,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:40,669 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:40,669 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 16:09:40,669 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 16:09:40,670 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 16:09:40,670 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:40,670 INFO L87 Difference]: Start difference. First operand 892 states and 1207 transitions. Second operand 6 states. [2018-11-23 16:09:40,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:40,737 INFO L93 Difference]: Finished difference Result 1798 states and 2496 transitions. [2018-11-23 16:09:40,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:09:40,738 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 135 [2018-11-23 16:09:40,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:40,741 INFO L225 Difference]: With dead ends: 1798 [2018-11-23 16:09:40,741 INFO L226 Difference]: Without dead ends: 930 [2018-11-23 16:09:40,742 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 16:09:40,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 930 states. [2018-11-23 16:09:40,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 930 to 902. [2018-11-23 16:09:40,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 902 states. [2018-11-23 16:09:40,789 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 902 states to 902 states and 1215 transitions. [2018-11-23 16:09:40,790 INFO L78 Accepts]: Start accepts. Automaton has 902 states and 1215 transitions. Word has length 135 [2018-11-23 16:09:40,790 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:40,790 INFO L480 AbstractCegarLoop]: Abstraction has 902 states and 1215 transitions. [2018-11-23 16:09:40,790 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 16:09:40,790 INFO L276 IsEmpty]: Start isEmpty. Operand 902 states and 1215 transitions. [2018-11-23 16:09:40,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:40,791 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:40,791 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:40,791 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:40,791 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:40,791 INFO L82 PathProgramCache]: Analyzing trace with hash 1233913670, now seen corresponding path program 1 times [2018-11-23 16:09:40,792 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:40,792 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:40,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:40,793 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:40,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:40,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:40,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:40,853 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:40,853 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 16:09:40,854 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 16:09:40,854 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 16:09:40,854 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 16:09:40,854 INFO L87 Difference]: Start difference. First operand 902 states and 1215 transitions. Second operand 4 states. [2018-11-23 16:09:41,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:41,178 INFO L93 Difference]: Finished difference Result 2633 states and 3671 transitions. [2018-11-23 16:09:41,179 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 16:09:41,179 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 135 [2018-11-23 16:09:41,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:41,186 INFO L225 Difference]: With dead ends: 2633 [2018-11-23 16:09:41,186 INFO L226 Difference]: Without dead ends: 1755 [2018-11-23 16:09:41,189 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 16:09:41,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1755 states. [2018-11-23 16:09:41,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1755 to 1744. [2018-11-23 16:09:41,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1744 states. [2018-11-23 16:09:41,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1744 states to 1744 states and 2347 transitions. [2018-11-23 16:09:41,335 INFO L78 Accepts]: Start accepts. Automaton has 1744 states and 2347 transitions. Word has length 135 [2018-11-23 16:09:41,336 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:41,336 INFO L480 AbstractCegarLoop]: Abstraction has 1744 states and 2347 transitions. [2018-11-23 16:09:41,336 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 16:09:41,336 INFO L276 IsEmpty]: Start isEmpty. Operand 1744 states and 2347 transitions. [2018-11-23 16:09:41,336 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:41,337 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:41,337 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:41,337 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:41,338 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:41,338 INFO L82 PathProgramCache]: Analyzing trace with hash 1375013191, now seen corresponding path program 1 times [2018-11-23 16:09:41,338 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:41,338 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:41,338 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:41,339 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:41,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:41,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:41,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:41,397 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:41,397 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 16:09:41,397 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 16:09:41,397 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 16:09:41,398 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:41,398 INFO L87 Difference]: Start difference. First operand 1744 states and 2347 transitions. Second operand 6 states. [2018-11-23 16:09:41,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:41,571 INFO L93 Difference]: Finished difference Result 3528 states and 4870 transitions. [2018-11-23 16:09:41,571 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:09:41,571 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 135 [2018-11-23 16:09:41,572 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:41,576 INFO L225 Difference]: With dead ends: 3528 [2018-11-23 16:09:41,576 INFO L226 Difference]: Without dead ends: 1808 [2018-11-23 16:09:41,581 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 16:09:41,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1808 states. [2018-11-23 16:09:41,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1808 to 1764. [2018-11-23 16:09:41,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1764 states. [2018-11-23 16:09:41,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1764 states to 1764 states and 2363 transitions. [2018-11-23 16:09:41,736 INFO L78 Accepts]: Start accepts. Automaton has 1764 states and 2363 transitions. Word has length 135 [2018-11-23 16:09:41,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:41,737 INFO L480 AbstractCegarLoop]: Abstraction has 1764 states and 2363 transitions. [2018-11-23 16:09:41,737 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 16:09:41,737 INFO L276 IsEmpty]: Start isEmpty. Operand 1764 states and 2363 transitions. [2018-11-23 16:09:41,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:41,738 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:41,738 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:41,738 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:41,738 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:41,738 INFO L82 PathProgramCache]: Analyzing trace with hash 882387017, now seen corresponding path program 1 times [2018-11-23 16:09:41,738 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:41,738 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:41,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:41,739 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:41,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:41,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:41,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:41,782 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:41,782 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 16:09:41,782 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 16:09:41,782 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 16:09:41,782 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:41,783 INFO L87 Difference]: Start difference. First operand 1764 states and 2363 transitions. Second operand 6 states. [2018-11-23 16:09:41,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:41,974 INFO L93 Difference]: Finished difference Result 3608 states and 4963 transitions. [2018-11-23 16:09:41,974 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:09:41,974 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 135 [2018-11-23 16:09:41,975 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:41,980 INFO L225 Difference]: With dead ends: 3608 [2018-11-23 16:09:41,980 INFO L226 Difference]: Without dead ends: 1868 [2018-11-23 16:09:41,984 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 16:09:41,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1868 states. [2018-11-23 16:09:42,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1868 to 1804. [2018-11-23 16:09:42,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1804 states. [2018-11-23 16:09:42,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1804 states to 1804 states and 2403 transitions. [2018-11-23 16:09:42,135 INFO L78 Accepts]: Start accepts. Automaton has 1804 states and 2403 transitions. Word has length 135 [2018-11-23 16:09:42,135 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:42,136 INFO L480 AbstractCegarLoop]: Abstraction has 1804 states and 2403 transitions. [2018-11-23 16:09:42,136 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 16:09:42,136 INFO L276 IsEmpty]: Start isEmpty. Operand 1804 states and 2403 transitions. [2018-11-23 16:09:42,136 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:42,136 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:42,137 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:42,137 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:42,138 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:42,138 INFO L82 PathProgramCache]: Analyzing trace with hash 1084210951, now seen corresponding path program 1 times [2018-11-23 16:09:42,138 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:42,138 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:42,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:42,138 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:42,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:42,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:42,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:42,192 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:42,193 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 16:09:42,193 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 16:09:42,193 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 16:09:42,193 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:42,193 INFO L87 Difference]: Start difference. First operand 1804 states and 2403 transitions. Second operand 6 states. [2018-11-23 16:09:42,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:42,365 INFO L93 Difference]: Finished difference Result 3664 states and 5003 transitions. [2018-11-23 16:09:42,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:09:42,366 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 135 [2018-11-23 16:09:42,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:42,372 INFO L225 Difference]: With dead ends: 3664 [2018-11-23 16:09:42,372 INFO L226 Difference]: Without dead ends: 1884 [2018-11-23 16:09:42,376 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 16:09:42,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1884 states. [2018-11-23 16:09:42,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1884 to 1844. [2018-11-23 16:09:42,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1844 states. [2018-11-23 16:09:42,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1844 states to 1844 states and 2443 transitions. [2018-11-23 16:09:42,528 INFO L78 Accepts]: Start accepts. Automaton has 1844 states and 2443 transitions. Word has length 135 [2018-11-23 16:09:42,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:42,529 INFO L480 AbstractCegarLoop]: Abstraction has 1844 states and 2443 transitions. [2018-11-23 16:09:42,529 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 16:09:42,529 INFO L276 IsEmpty]: Start isEmpty. Operand 1844 states and 2443 transitions. [2018-11-23 16:09:42,530 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:42,530 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:42,530 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:42,530 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:42,530 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:42,530 INFO L82 PathProgramCache]: Analyzing trace with hash -944375159, now seen corresponding path program 1 times [2018-11-23 16:09:42,530 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:42,530 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:42,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:42,531 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:42,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:42,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:42,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:42,588 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:42,588 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 16:09:42,588 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 16:09:42,588 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 16:09:42,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:42,589 INFO L87 Difference]: Start difference. First operand 1844 states and 2443 transitions. Second operand 6 states. [2018-11-23 16:09:42,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:42,758 INFO L93 Difference]: Finished difference Result 3720 states and 5043 transitions. [2018-11-23 16:09:42,759 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:09:42,759 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 135 [2018-11-23 16:09:42,759 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:42,765 INFO L225 Difference]: With dead ends: 3720 [2018-11-23 16:09:42,765 INFO L226 Difference]: Without dead ends: 1900 [2018-11-23 16:09:42,769 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 16:09:42,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1900 states. [2018-11-23 16:09:42,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1900 to 1884. [2018-11-23 16:09:42,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1884 states. [2018-11-23 16:09:42,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1884 states to 1884 states and 2483 transitions. [2018-11-23 16:09:42,932 INFO L78 Accepts]: Start accepts. Automaton has 1884 states and 2483 transitions. Word has length 135 [2018-11-23 16:09:42,932 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:42,933 INFO L480 AbstractCegarLoop]: Abstraction has 1884 states and 2483 transitions. [2018-11-23 16:09:42,933 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 16:09:42,933 INFO L276 IsEmpty]: Start isEmpty. Operand 1884 states and 2483 transitions. [2018-11-23 16:09:42,934 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:42,934 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:42,934 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:42,934 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:42,934 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:42,934 INFO L82 PathProgramCache]: Analyzing trace with hash -696228665, now seen corresponding path program 1 times [2018-11-23 16:09:42,934 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:42,935 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:42,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:42,935 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:42,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:42,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:43,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:43,051 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:43,051 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:43,051 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:43,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:43,051 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:43,052 INFO L87 Difference]: Start difference. First operand 1884 states and 2483 transitions. Second operand 5 states. [2018-11-23 16:09:43,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:43,777 INFO L93 Difference]: Finished difference Result 4603 states and 6160 transitions. [2018-11-23 16:09:43,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 16:09:43,778 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:43,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:43,783 INFO L225 Difference]: With dead ends: 4603 [2018-11-23 16:09:43,784 INFO L226 Difference]: Without dead ends: 2744 [2018-11-23 16:09:43,787 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 16:09:43,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2744 states. [2018-11-23 16:09:43,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2744 to 2568. [2018-11-23 16:09:43,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2568 states. [2018-11-23 16:09:43,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2568 states to 2568 states and 3291 transitions. [2018-11-23 16:09:43,903 INFO L78 Accepts]: Start accepts. Automaton has 2568 states and 3291 transitions. Word has length 135 [2018-11-23 16:09:43,903 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:43,903 INFO L480 AbstractCegarLoop]: Abstraction has 2568 states and 3291 transitions. [2018-11-23 16:09:43,903 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:43,903 INFO L276 IsEmpty]: Start isEmpty. Operand 2568 states and 3291 transitions. [2018-11-23 16:09:43,904 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:43,904 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:43,904 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:43,904 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:43,904 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:43,904 INFO L82 PathProgramCache]: Analyzing trace with hash -1725587963, now seen corresponding path program 1 times [2018-11-23 16:09:43,904 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:43,904 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:43,905 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:43,905 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:43,905 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:43,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:43,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:43,959 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:43,959 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:43,959 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:43,960 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:43,960 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:43,960 INFO L87 Difference]: Start difference. First operand 2568 states and 3291 transitions. Second operand 5 states. [2018-11-23 16:09:44,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:44,328 INFO L93 Difference]: Finished difference Result 5111 states and 6573 transitions. [2018-11-23 16:09:44,330 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 16:09:44,330 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:44,330 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:44,337 INFO L225 Difference]: With dead ends: 5111 [2018-11-23 16:09:44,337 INFO L226 Difference]: Without dead ends: 2568 [2018-11-23 16:09:44,340 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:44,342 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2568 states. [2018-11-23 16:09:44,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2568 to 2568. [2018-11-23 16:09:44,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2568 states. [2018-11-23 16:09:44,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2568 states to 2568 states and 3271 transitions. [2018-11-23 16:09:44,479 INFO L78 Accepts]: Start accepts. Automaton has 2568 states and 3271 transitions. Word has length 135 [2018-11-23 16:09:44,479 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:44,480 INFO L480 AbstractCegarLoop]: Abstraction has 2568 states and 3271 transitions. [2018-11-23 16:09:44,480 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:44,480 INFO L276 IsEmpty]: Start isEmpty. Operand 2568 states and 3271 transitions. [2018-11-23 16:09:44,480 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:44,480 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:44,481 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:44,482 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:44,482 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:44,482 INFO L82 PathProgramCache]: Analyzing trace with hash -1066056441, now seen corresponding path program 1 times [2018-11-23 16:09:44,482 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:44,482 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:44,483 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:44,483 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:44,483 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:44,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:44,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:44,539 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:44,539 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:44,539 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:44,540 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:44,540 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:44,540 INFO L87 Difference]: Start difference. First operand 2568 states and 3271 transitions. Second operand 5 states. [2018-11-23 16:09:44,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:44,917 INFO L93 Difference]: Finished difference Result 5111 states and 6533 transitions. [2018-11-23 16:09:44,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 16:09:44,918 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:44,918 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:44,924 INFO L225 Difference]: With dead ends: 5111 [2018-11-23 16:09:44,924 INFO L226 Difference]: Without dead ends: 2568 [2018-11-23 16:09:44,927 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:44,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2568 states. [2018-11-23 16:09:45,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2568 to 2568. [2018-11-23 16:09:45,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2568 states. [2018-11-23 16:09:45,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2568 states to 2568 states and 3251 transitions. [2018-11-23 16:09:45,045 INFO L78 Accepts]: Start accepts. Automaton has 2568 states and 3251 transitions. Word has length 135 [2018-11-23 16:09:45,045 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:45,045 INFO L480 AbstractCegarLoop]: Abstraction has 2568 states and 3251 transitions. [2018-11-23 16:09:45,045 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:45,045 INFO L276 IsEmpty]: Start isEmpty. Operand 2568 states and 3251 transitions. [2018-11-23 16:09:45,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:45,046 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:45,046 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:45,047 INFO L423 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:45,047 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:45,047 INFO L82 PathProgramCache]: Analyzing trace with hash -1460423227, now seen corresponding path program 1 times [2018-11-23 16:09:45,047 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:45,047 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:45,047 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:45,048 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:45,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:45,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:45,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:45,103 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:45,103 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:45,103 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:45,103 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:45,103 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:45,103 INFO L87 Difference]: Start difference. First operand 2568 states and 3251 transitions. Second operand 5 states. [2018-11-23 16:09:45,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:45,508 INFO L93 Difference]: Finished difference Result 5111 states and 6493 transitions. [2018-11-23 16:09:45,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 16:09:45,509 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:45,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:45,515 INFO L225 Difference]: With dead ends: 5111 [2018-11-23 16:09:45,515 INFO L226 Difference]: Without dead ends: 2568 [2018-11-23 16:09:45,520 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:45,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2568 states. [2018-11-23 16:09:45,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2568 to 2568. [2018-11-23 16:09:45,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2568 states. [2018-11-23 16:09:45,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2568 states to 2568 states and 3231 transitions. [2018-11-23 16:09:45,732 INFO L78 Accepts]: Start accepts. Automaton has 2568 states and 3231 transitions. Word has length 135 [2018-11-23 16:09:45,733 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:45,733 INFO L480 AbstractCegarLoop]: Abstraction has 2568 states and 3231 transitions. [2018-11-23 16:09:45,733 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:45,734 INFO L276 IsEmpty]: Start isEmpty. Operand 2568 states and 3231 transitions. [2018-11-23 16:09:45,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:45,734 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:45,734 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:45,735 INFO L423 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:45,735 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:45,735 INFO L82 PathProgramCache]: Analyzing trace with hash 1990538567, now seen corresponding path program 1 times [2018-11-23 16:09:45,735 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:45,735 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:45,736 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:45,736 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:45,736 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:45,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:45,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:45,789 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:45,789 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:45,789 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:45,789 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:45,790 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:45,790 INFO L87 Difference]: Start difference. First operand 2568 states and 3231 transitions. Second operand 5 states. [2018-11-23 16:09:46,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:46,258 INFO L93 Difference]: Finished difference Result 5111 states and 6453 transitions. [2018-11-23 16:09:46,259 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 16:09:46,259 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:46,259 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:46,267 INFO L225 Difference]: With dead ends: 5111 [2018-11-23 16:09:46,267 INFO L226 Difference]: Without dead ends: 2568 [2018-11-23 16:09:46,271 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:09:46,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2568 states. [2018-11-23 16:09:46,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2568 to 2568. [2018-11-23 16:09:46,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2568 states. [2018-11-23 16:09:46,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2568 states to 2568 states and 3211 transitions. [2018-11-23 16:09:46,425 INFO L78 Accepts]: Start accepts. Automaton has 2568 states and 3211 transitions. Word has length 135 [2018-11-23 16:09:46,425 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:46,425 INFO L480 AbstractCegarLoop]: Abstraction has 2568 states and 3211 transitions. [2018-11-23 16:09:46,425 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:46,425 INFO L276 IsEmpty]: Start isEmpty. Operand 2568 states and 3211 transitions. [2018-11-23 16:09:46,426 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:46,426 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:46,426 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:46,426 INFO L423 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:46,426 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:46,426 INFO L82 PathProgramCache]: Analyzing trace with hash -253444731, now seen corresponding path program 1 times [2018-11-23 16:09:46,426 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:46,426 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:46,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:46,427 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:46,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:46,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:46,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:46,484 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:46,484 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:46,485 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:46,485 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:46,485 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:46,485 INFO L87 Difference]: Start difference. First operand 2568 states and 3211 transitions. Second operand 5 states. [2018-11-23 16:09:47,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:47,057 INFO L93 Difference]: Finished difference Result 5509 states and 6996 transitions. [2018-11-23 16:09:47,057 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:09:47,057 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:47,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:47,066 INFO L225 Difference]: With dead ends: 5509 [2018-11-23 16:09:47,066 INFO L226 Difference]: Without dead ends: 2966 [2018-11-23 16:09:47,071 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 16:09:47,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2966 states. [2018-11-23 16:09:47,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2966 to 2964. [2018-11-23 16:09:47,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2964 states. [2018-11-23 16:09:47,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2964 states to 2964 states and 3689 transitions. [2018-11-23 16:09:47,278 INFO L78 Accepts]: Start accepts. Automaton has 2964 states and 3689 transitions. Word has length 135 [2018-11-23 16:09:47,279 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:47,279 INFO L480 AbstractCegarLoop]: Abstraction has 2964 states and 3689 transitions. [2018-11-23 16:09:47,279 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:47,279 INFO L276 IsEmpty]: Start isEmpty. Operand 2964 states and 3689 transitions. [2018-11-23 16:09:47,280 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:47,280 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:47,280 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:47,280 INFO L423 AbstractCegarLoop]: === Iteration 27 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:47,280 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:47,280 INFO L82 PathProgramCache]: Analyzing trace with hash 21314883, now seen corresponding path program 1 times [2018-11-23 16:09:47,280 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:47,280 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:47,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:47,281 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:47,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:47,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:47,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:47,337 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:47,337 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:47,338 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:47,338 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:47,338 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:47,338 INFO L87 Difference]: Start difference. First operand 2964 states and 3689 transitions. Second operand 5 states. [2018-11-23 16:09:47,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:47,878 INFO L93 Difference]: Finished difference Result 6945 states and 8960 transitions. [2018-11-23 16:09:47,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 16:09:47,879 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:47,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:47,887 INFO L225 Difference]: With dead ends: 6945 [2018-11-23 16:09:47,887 INFO L226 Difference]: Without dead ends: 4006 [2018-11-23 16:09:47,892 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 16:09:47,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4006 states. [2018-11-23 16:09:48,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4006 to 3712. [2018-11-23 16:09:48,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3712 states. [2018-11-23 16:09:48,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3712 states to 3712 states and 4537 transitions. [2018-11-23 16:09:48,221 INFO L78 Accepts]: Start accepts. Automaton has 3712 states and 4537 transitions. Word has length 135 [2018-11-23 16:09:48,221 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:48,221 INFO L480 AbstractCegarLoop]: Abstraction has 3712 states and 4537 transitions. [2018-11-23 16:09:48,221 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:48,222 INFO L276 IsEmpty]: Start isEmpty. Operand 3712 states and 4537 transitions. [2018-11-23 16:09:48,223 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:48,223 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:48,223 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:48,223 INFO L423 AbstractCegarLoop]: === Iteration 28 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:48,223 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:48,223 INFO L82 PathProgramCache]: Analyzing trace with hash 722914757, now seen corresponding path program 1 times [2018-11-23 16:09:48,223 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:48,224 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:48,224 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:48,224 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:48,224 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:48,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:48,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:48,320 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:48,320 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:48,321 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:48,322 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:48,322 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:48,322 INFO L87 Difference]: Start difference. First operand 3712 states and 4537 transitions. Second operand 5 states. [2018-11-23 16:09:48,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:48,959 INFO L93 Difference]: Finished difference Result 7961 states and 10131 transitions. [2018-11-23 16:09:48,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:09:48,959 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:48,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:48,970 INFO L225 Difference]: With dead ends: 7961 [2018-11-23 16:09:48,970 INFO L226 Difference]: Without dead ends: 4274 [2018-11-23 16:09:48,979 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 16:09:48,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4274 states. [2018-11-23 16:09:49,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4274 to 3908. [2018-11-23 16:09:49,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3908 states. [2018-11-23 16:09:49,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3908 states to 3908 states and 4689 transitions. [2018-11-23 16:09:49,237 INFO L78 Accepts]: Start accepts. Automaton has 3908 states and 4689 transitions. Word has length 135 [2018-11-23 16:09:49,237 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:49,237 INFO L480 AbstractCegarLoop]: Abstraction has 3908 states and 4689 transitions. [2018-11-23 16:09:49,237 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:49,238 INFO L276 IsEmpty]: Start isEmpty. Operand 3908 states and 4689 transitions. [2018-11-23 16:09:49,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:49,239 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:49,239 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:49,239 INFO L423 AbstractCegarLoop]: === Iteration 29 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:49,239 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:49,239 INFO L82 PathProgramCache]: Analyzing trace with hash 745547011, now seen corresponding path program 1 times [2018-11-23 16:09:49,239 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:49,239 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:49,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:49,240 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:49,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:49,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:49,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:49,312 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:49,312 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:49,313 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:49,313 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:49,313 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:49,313 INFO L87 Difference]: Start difference. First operand 3908 states and 4689 transitions. Second operand 5 states. [2018-11-23 16:09:50,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:50,093 INFO L93 Difference]: Finished difference Result 8871 states and 11287 transitions. [2018-11-23 16:09:50,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:09:50,093 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:50,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:50,105 INFO L225 Difference]: With dead ends: 8871 [2018-11-23 16:09:50,105 INFO L226 Difference]: Without dead ends: 4988 [2018-11-23 16:09:50,112 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 16:09:50,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4988 states. [2018-11-23 16:09:50,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4988 to 4344. [2018-11-23 16:09:50,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4344 states. [2018-11-23 16:09:50,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4344 states to 4344 states and 5105 transitions. [2018-11-23 16:09:50,410 INFO L78 Accepts]: Start accepts. Automaton has 4344 states and 5105 transitions. Word has length 135 [2018-11-23 16:09:50,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:50,410 INFO L480 AbstractCegarLoop]: Abstraction has 4344 states and 5105 transitions. [2018-11-23 16:09:50,410 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:50,410 INFO L276 IsEmpty]: Start isEmpty. Operand 4344 states and 5105 transitions. [2018-11-23 16:09:50,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:50,411 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:50,411 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:50,411 INFO L423 AbstractCegarLoop]: === Iteration 30 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:50,411 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:50,412 INFO L82 PathProgramCache]: Analyzing trace with hash 2131750405, now seen corresponding path program 1 times [2018-11-23 16:09:50,412 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:50,412 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:50,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:50,412 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:50,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:50,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:50,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:50,477 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:50,477 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:09:50,477 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:09:50,477 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:09:50,477 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:09:50,477 INFO L87 Difference]: Start difference. First operand 4344 states and 5105 transitions. Second operand 5 states. [2018-11-23 16:09:51,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:51,233 INFO L93 Difference]: Finished difference Result 9535 states and 11879 transitions. [2018-11-23 16:09:51,234 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:09:51,234 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2018-11-23 16:09:51,234 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:51,248 INFO L225 Difference]: With dead ends: 9535 [2018-11-23 16:09:51,248 INFO L226 Difference]: Without dead ends: 5216 [2018-11-23 16:09:51,257 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 16:09:51,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5216 states. [2018-11-23 16:09:51,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5216 to 4692. [2018-11-23 16:09:51,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4692 states. [2018-11-23 16:09:51,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4692 states to 4692 states and 5393 transitions. [2018-11-23 16:09:51,605 INFO L78 Accepts]: Start accepts. Automaton has 4692 states and 5393 transitions. Word has length 135 [2018-11-23 16:09:51,606 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:51,606 INFO L480 AbstractCegarLoop]: Abstraction has 4692 states and 5393 transitions. [2018-11-23 16:09:51,606 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:09:51,606 INFO L276 IsEmpty]: Start isEmpty. Operand 4692 states and 5393 transitions. [2018-11-23 16:09:51,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-11-23 16:09:51,606 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:51,606 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:51,607 INFO L423 AbstractCegarLoop]: === Iteration 31 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:51,607 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:51,607 INFO L82 PathProgramCache]: Analyzing trace with hash 1622277315, now seen corresponding path program 1 times [2018-11-23 16:09:51,607 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:51,607 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:51,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:51,607 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:51,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:51,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:51,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:51,644 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:51,644 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:09:51,645 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:09:51,645 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:09:51,645 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:09:51,645 INFO L87 Difference]: Start difference. First operand 4692 states and 5393 transitions. Second operand 3 states. [2018-11-23 16:09:52,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:52,105 INFO L93 Difference]: Finished difference Result 13652 states and 15833 transitions. [2018-11-23 16:09:52,105 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:09:52,105 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 135 [2018-11-23 16:09:52,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:52,121 INFO L225 Difference]: With dead ends: 13652 [2018-11-23 16:09:52,122 INFO L226 Difference]: Without dead ends: 8987 [2018-11-23 16:09:52,130 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:09:52,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8987 states. [2018-11-23 16:09:52,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8987 to 8984. [2018-11-23 16:09:52,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8984 states. [2018-11-23 16:09:52,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8984 states to 8984 states and 10368 transitions. [2018-11-23 16:09:52,662 INFO L78 Accepts]: Start accepts. Automaton has 8984 states and 10368 transitions. Word has length 135 [2018-11-23 16:09:52,663 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:52,663 INFO L480 AbstractCegarLoop]: Abstraction has 8984 states and 10368 transitions. [2018-11-23 16:09:52,663 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:09:52,663 INFO L276 IsEmpty]: Start isEmpty. Operand 8984 states and 10368 transitions. [2018-11-23 16:09:52,664 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2018-11-23 16:09:52,664 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:52,664 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:52,664 INFO L423 AbstractCegarLoop]: === Iteration 32 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:52,664 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:52,665 INFO L82 PathProgramCache]: Analyzing trace with hash 1413801157, now seen corresponding path program 1 times [2018-11-23 16:09:52,665 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:52,665 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:52,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:52,665 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:52,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:52,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:52,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:09:52,714 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:52,714 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:09:52,714 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:09:52,714 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:09:52,714 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:09:52,715 INFO L87 Difference]: Start difference. First operand 8984 states and 10368 transitions. Second operand 3 states. [2018-11-23 16:09:53,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:53,697 INFO L93 Difference]: Finished difference Result 26543 states and 31838 transitions. [2018-11-23 16:09:53,697 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:09:53,697 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 136 [2018-11-23 16:09:53,697 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:53,733 INFO L225 Difference]: With dead ends: 26543 [2018-11-23 16:09:53,733 INFO L226 Difference]: Without dead ends: 17594 [2018-11-23 16:09:53,746 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:09:53,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17594 states. [2018-11-23 16:09:54,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17594 to 17580. [2018-11-23 16:09:54,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17580 states. [2018-11-23 16:09:54,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17580 states to 17580 states and 20744 transitions. [2018-11-23 16:09:54,713 INFO L78 Accepts]: Start accepts. Automaton has 17580 states and 20744 transitions. Word has length 136 [2018-11-23 16:09:54,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:54,713 INFO L480 AbstractCegarLoop]: Abstraction has 17580 states and 20744 transitions. [2018-11-23 16:09:54,713 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:09:54,713 INFO L276 IsEmpty]: Start isEmpty. Operand 17580 states and 20744 transitions. [2018-11-23 16:09:54,715 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 160 [2018-11-23 16:09:54,715 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:54,715 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:54,715 INFO L423 AbstractCegarLoop]: === Iteration 33 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:54,716 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:54,716 INFO L82 PathProgramCache]: Analyzing trace with hash -1579886078, now seen corresponding path program 1 times [2018-11-23 16:09:54,716 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:54,716 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:54,716 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:54,716 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:54,716 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:54,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:54,765 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-11-23 16:09:54,765 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:54,765 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 16:09:54,765 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 16:09:54,766 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 16:09:54,766 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 16:09:54,766 INFO L87 Difference]: Start difference. First operand 17580 states and 20744 transitions. Second operand 4 states. [2018-11-23 16:09:55,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:55,625 INFO L93 Difference]: Finished difference Result 31243 states and 36800 transitions. [2018-11-23 16:09:55,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 16:09:55,626 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 159 [2018-11-23 16:09:55,626 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:55,657 INFO L225 Difference]: With dead ends: 31243 [2018-11-23 16:09:55,657 INFO L226 Difference]: Without dead ends: 13690 [2018-11-23 16:09:55,680 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 16:09:55,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13690 states. [2018-11-23 16:09:56,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13690 to 13518. [2018-11-23 16:09:56,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13518 states. [2018-11-23 16:09:56,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13518 states to 13518 states and 15907 transitions. [2018-11-23 16:09:56,511 INFO L78 Accepts]: Start accepts. Automaton has 13518 states and 15907 transitions. Word has length 159 [2018-11-23 16:09:56,511 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:56,511 INFO L480 AbstractCegarLoop]: Abstraction has 13518 states and 15907 transitions. [2018-11-23 16:09:56,511 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 16:09:56,511 INFO L276 IsEmpty]: Start isEmpty. Operand 13518 states and 15907 transitions. [2018-11-23 16:09:56,512 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 160 [2018-11-23 16:09:56,512 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:56,512 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:56,512 INFO L423 AbstractCegarLoop]: === Iteration 34 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:56,512 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:56,513 INFO L82 PathProgramCache]: Analyzing trace with hash -2006440576, now seen corresponding path program 1 times [2018-11-23 16:09:56,513 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:56,513 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:56,513 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:56,513 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:56,513 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:56,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:56,563 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-23 16:09:56,563 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:56,563 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:09:56,564 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:09:56,564 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:09:56,564 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:09:56,564 INFO L87 Difference]: Start difference. First operand 13518 states and 15907 transitions. Second operand 3 states. [2018-11-23 16:09:58,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:09:58,081 INFO L93 Difference]: Finished difference Result 40328 states and 48278 transitions. [2018-11-23 16:09:58,082 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:09:58,082 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 159 [2018-11-23 16:09:58,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:09:58,117 INFO L225 Difference]: With dead ends: 40328 [2018-11-23 16:09:58,117 INFO L226 Difference]: Without dead ends: 20209 [2018-11-23 16:09:58,141 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:09:58,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20209 states. [2018-11-23 16:09:59,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20209 to 20209. [2018-11-23 16:09:59,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20209 states. [2018-11-23 16:09:59,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20209 states to 20209 states and 23786 transitions. [2018-11-23 16:09:59,387 INFO L78 Accepts]: Start accepts. Automaton has 20209 states and 23786 transitions. Word has length 159 [2018-11-23 16:09:59,388 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:09:59,388 INFO L480 AbstractCegarLoop]: Abstraction has 20209 states and 23786 transitions. [2018-11-23 16:09:59,388 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:09:59,388 INFO L276 IsEmpty]: Start isEmpty. Operand 20209 states and 23786 transitions. [2018-11-23 16:09:59,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 231 [2018-11-23 16:09:59,393 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:09:59,393 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:09:59,393 INFO L423 AbstractCegarLoop]: === Iteration 35 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:09:59,393 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:09:59,393 INFO L82 PathProgramCache]: Analyzing trace with hash 912039244, now seen corresponding path program 1 times [2018-11-23 16:09:59,393 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:09:59,393 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:09:59,394 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:59,394 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:09:59,394 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:09:59,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:09:59,436 INFO L134 CoverageAnalysis]: Checked inductivity of 75 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2018-11-23 16:09:59,437 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:09:59,437 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:09:59,437 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:09:59,437 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:09:59,437 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:09:59,437 INFO L87 Difference]: Start difference. First operand 20209 states and 23786 transitions. Second operand 3 states. [2018-11-23 16:10:01,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:10:01,624 INFO L93 Difference]: Finished difference Result 57833 states and 70645 transitions. [2018-11-23 16:10:01,624 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:10:01,624 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 230 [2018-11-23 16:10:01,624 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:10:01,698 INFO L225 Difference]: With dead ends: 57833 [2018-11-23 16:10:01,698 INFO L226 Difference]: Without dead ends: 37651 [2018-11-23 16:10:01,732 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:10:01,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37651 states. [2018-11-23 16:10:04,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37651 to 37648. [2018-11-23 16:10:04,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37648 states. [2018-11-23 16:10:04,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37648 states to 37648 states and 45629 transitions. [2018-11-23 16:10:04,179 INFO L78 Accepts]: Start accepts. Automaton has 37648 states and 45629 transitions. Word has length 230 [2018-11-23 16:10:04,179 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:10:04,180 INFO L480 AbstractCegarLoop]: Abstraction has 37648 states and 45629 transitions. [2018-11-23 16:10:04,180 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:10:04,180 INFO L276 IsEmpty]: Start isEmpty. Operand 37648 states and 45629 transitions. [2018-11-23 16:10:04,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 232 [2018-11-23 16:10:04,189 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:10:04,190 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:10:04,190 INFO L423 AbstractCegarLoop]: === Iteration 36 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:10:04,190 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:10:04,190 INFO L82 PathProgramCache]: Analyzing trace with hash 1403120970, now seen corresponding path program 1 times [2018-11-23 16:10:04,190 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:10:04,190 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:10:04,190 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:10:04,191 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:10:04,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:10:04,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:10:04,257 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2018-11-23 16:10:04,258 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:10:04,258 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:10:04,266 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:10:04,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:10:04,369 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:10:04,420 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 60 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 16:10:04,436 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 16:10:04,437 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [6] total 7 [2018-11-23 16:10:04,437 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 16:10:04,437 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 16:10:04,437 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-11-23 16:10:04,438 INFO L87 Difference]: Start difference. First operand 37648 states and 45629 transitions. Second operand 7 states. [2018-11-23 16:10:09,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:10:09,340 INFO L93 Difference]: Finished difference Result 100337 states and 129946 transitions. [2018-11-23 16:10:09,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 16:10:09,341 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 231 [2018-11-23 16:10:09,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:10:09,434 INFO L225 Difference]: With dead ends: 100337 [2018-11-23 16:10:09,434 INFO L226 Difference]: Without dead ends: 51360 [2018-11-23 16:10:09,512 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 239 GetRequests, 233 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-11-23 16:10:09,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51360 states. [2018-11-23 16:10:12,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51360 to 51348. [2018-11-23 16:10:12,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51348 states. [2018-11-23 16:10:12,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51348 states to 51348 states and 63158 transitions. [2018-11-23 16:10:12,792 INFO L78 Accepts]: Start accepts. Automaton has 51348 states and 63158 transitions. Word has length 231 [2018-11-23 16:10:12,792 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:10:12,792 INFO L480 AbstractCegarLoop]: Abstraction has 51348 states and 63158 transitions. [2018-11-23 16:10:12,792 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 16:10:12,792 INFO L276 IsEmpty]: Start isEmpty. Operand 51348 states and 63158 transitions. [2018-11-23 16:10:12,829 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 458 [2018-11-23 16:10:12,829 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:10:12,830 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:10:12,830 INFO L423 AbstractCegarLoop]: === Iteration 37 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:10:12,830 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:10:12,830 INFO L82 PathProgramCache]: Analyzing trace with hash 1576097428, now seen corresponding path program 1 times [2018-11-23 16:10:12,830 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:10:12,830 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:10:12,831 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:10:12,831 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:10:12,831 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:10:12,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:10:12,946 INFO L134 CoverageAnalysis]: Checked inductivity of 507 backedges. 39 proven. 26 refuted. 0 times theorem prover too weak. 442 trivial. 0 not checked. [2018-11-23 16:10:12,946 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:10:12,946 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:10:12,953 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:10:13,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:10:13,084 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:10:13,150 INFO L134 CoverageAnalysis]: Checked inductivity of 507 backedges. 273 proven. 0 refuted. 0 times theorem prover too weak. 234 trivial. 0 not checked. [2018-11-23 16:10:13,165 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 16:10:13,165 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [8] total 9 [2018-11-23 16:10:13,166 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 16:10:13,166 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 16:10:13,167 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-11-23 16:10:13,167 INFO L87 Difference]: Start difference. First operand 51348 states and 63158 transitions. Second operand 9 states. [2018-11-23 16:10:16,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:10:16,611 INFO L93 Difference]: Finished difference Result 94825 states and 119170 transitions. [2018-11-23 16:10:16,612 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-23 16:10:16,612 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 457 [2018-11-23 16:10:16,612 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:10:16,695 INFO L225 Difference]: With dead ends: 94825 [2018-11-23 16:10:16,695 INFO L226 Difference]: Without dead ends: 43504 [2018-11-23 16:10:16,773 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 480 GetRequests, 461 SyntacticMatches, 2 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=81, Invalid=261, Unknown=0, NotChecked=0, Total=342 [2018-11-23 16:10:16,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43504 states. [2018-11-23 16:10:20,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43504 to 41149. [2018-11-23 16:10:20,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41149 states. [2018-11-23 16:10:20,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41149 states to 41149 states and 47380 transitions. [2018-11-23 16:10:20,761 INFO L78 Accepts]: Start accepts. Automaton has 41149 states and 47380 transitions. Word has length 457 [2018-11-23 16:10:20,762 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:10:20,762 INFO L480 AbstractCegarLoop]: Abstraction has 41149 states and 47380 transitions. [2018-11-23 16:10:20,762 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 16:10:20,762 INFO L276 IsEmpty]: Start isEmpty. Operand 41149 states and 47380 transitions. [2018-11-23 16:10:20,785 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 314 [2018-11-23 16:10:20,785 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:10:20,785 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:10:20,785 INFO L423 AbstractCegarLoop]: === Iteration 38 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:10:20,785 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:10:20,785 INFO L82 PathProgramCache]: Analyzing trace with hash -2115810817, now seen corresponding path program 1 times [2018-11-23 16:10:20,785 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:10:20,785 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:10:20,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:10:20,786 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:10:20,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:10:20,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:10:20,896 INFO L134 CoverageAnalysis]: Checked inductivity of 201 backedges. 1 proven. 30 refuted. 0 times theorem prover too weak. 170 trivial. 0 not checked. [2018-11-23 16:10:20,896 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:10:20,896 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:10:20,903 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:10:20,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:10:21,003 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:10:21,083 INFO L134 CoverageAnalysis]: Checked inductivity of 201 backedges. 62 proven. 0 refuted. 0 times theorem prover too weak. 139 trivial. 0 not checked. [2018-11-23 16:10:21,099 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 16:10:21,099 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-11-23 16:10:21,100 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:10:21,100 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:10:21,100 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:10:21,100 INFO L87 Difference]: Start difference. First operand 41149 states and 47380 transitions. Second operand 5 states. [2018-11-23 16:10:24,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:10:24,712 INFO L93 Difference]: Finished difference Result 71643 states and 82184 transitions. [2018-11-23 16:10:24,712 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 16:10:24,713 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 313 [2018-11-23 16:10:24,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:10:24,804 INFO L225 Difference]: With dead ends: 71643 [2018-11-23 16:10:24,804 INFO L226 Difference]: Without dead ends: 41159 [2018-11-23 16:10:24,854 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 318 GetRequests, 312 SyntacticMatches, 3 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:10:24,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41159 states. [2018-11-23 16:10:27,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41159 to 41007. [2018-11-23 16:10:27,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41007 states. [2018-11-23 16:10:27,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41007 states to 41007 states and 46564 transitions. [2018-11-23 16:10:27,684 INFO L78 Accepts]: Start accepts. Automaton has 41007 states and 46564 transitions. Word has length 313 [2018-11-23 16:10:27,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:10:27,685 INFO L480 AbstractCegarLoop]: Abstraction has 41007 states and 46564 transitions. [2018-11-23 16:10:27,685 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:10:27,685 INFO L276 IsEmpty]: Start isEmpty. Operand 41007 states and 46564 transitions. [2018-11-23 16:10:27,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 320 [2018-11-23 16:10:27,710 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:10:27,710 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:10:27,710 INFO L423 AbstractCegarLoop]: === Iteration 39 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:10:27,710 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:10:27,710 INFO L82 PathProgramCache]: Analyzing trace with hash 1256616, now seen corresponding path program 1 times [2018-11-23 16:10:27,710 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:10:27,710 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:10:27,711 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:10:27,711 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:10:27,711 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:10:27,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:10:27,798 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 18 proven. 7 refuted. 0 times theorem prover too weak. 181 trivial. 0 not checked. [2018-11-23 16:10:27,798 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:10:27,798 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:10:27,815 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:10:27,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:10:27,952 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:10:28,025 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 145 proven. 0 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2018-11-23 16:10:28,050 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 16:10:28,050 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2018-11-23 16:10:28,051 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 16:10:28,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 16:10:28,051 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:10:28,051 INFO L87 Difference]: Start difference. First operand 41007 states and 46564 transitions. Second operand 6 states. [2018-11-23 16:10:33,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:10:33,738 INFO L93 Difference]: Finished difference Result 115967 states and 132554 transitions. [2018-11-23 16:10:33,739 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 16:10:33,739 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 319 [2018-11-23 16:10:33,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:10:33,865 INFO L225 Difference]: With dead ends: 115967 [2018-11-23 16:10:33,865 INFO L226 Difference]: Without dead ends: 54592 [2018-11-23 16:10:33,946 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 327 GetRequests, 321 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2018-11-23 16:10:33,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54592 states. [2018-11-23 16:10:37,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54592 to 54169. [2018-11-23 16:10:37,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54169 states. [2018-11-23 16:10:37,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54169 states to 54169 states and 61846 transitions. [2018-11-23 16:10:37,598 INFO L78 Accepts]: Start accepts. Automaton has 54169 states and 61846 transitions. Word has length 319 [2018-11-23 16:10:37,598 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:10:37,598 INFO L480 AbstractCegarLoop]: Abstraction has 54169 states and 61846 transitions. [2018-11-23 16:10:37,598 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 16:10:37,598 INFO L276 IsEmpty]: Start isEmpty. Operand 54169 states and 61846 transitions. [2018-11-23 16:10:37,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 403 [2018-11-23 16:10:37,629 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:10:37,630 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:10:37,630 INFO L423 AbstractCegarLoop]: === Iteration 40 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:10:37,630 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:10:37,630 INFO L82 PathProgramCache]: Analyzing trace with hash 313816314, now seen corresponding path program 1 times [2018-11-23 16:10:37,630 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:10:37,630 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:10:37,630 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:10:37,630 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:10:37,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:10:37,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:10:37,738 INFO L134 CoverageAnalysis]: Checked inductivity of 394 backedges. 20 proven. 12 refuted. 0 times theorem prover too weak. 362 trivial. 0 not checked. [2018-11-23 16:10:37,738 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:10:37,738 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:10:37,752 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:10:37,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:10:37,916 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:10:37,992 INFO L134 CoverageAnalysis]: Checked inductivity of 394 backedges. 208 proven. 0 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-11-23 16:10:38,019 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 16:10:38,019 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2018-11-23 16:10:38,020 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 16:10:38,020 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 16:10:38,020 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:10:38,020 INFO L87 Difference]: Start difference. First operand 54169 states and 61846 transitions. Second operand 6 states. [2018-11-23 16:10:44,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:10:44,995 INFO L93 Difference]: Finished difference Result 148306 states and 171907 transitions. [2018-11-23 16:10:44,995 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 16:10:44,995 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 402 [2018-11-23 16:10:44,995 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:10:45,196 INFO L225 Difference]: With dead ends: 148306 [2018-11-23 16:10:45,196 INFO L226 Difference]: Without dead ends: 87811 [2018-11-23 16:10:45,284 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 412 GetRequests, 406 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2018-11-23 16:10:45,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87811 states. [2018-11-23 16:10:50,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87811 to 86246. [2018-11-23 16:10:50,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86246 states. [2018-11-23 16:10:50,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86246 states to 86246 states and 99648 transitions. [2018-11-23 16:10:50,987 INFO L78 Accepts]: Start accepts. Automaton has 86246 states and 99648 transitions. Word has length 402 [2018-11-23 16:10:50,987 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:10:50,987 INFO L480 AbstractCegarLoop]: Abstraction has 86246 states and 99648 transitions. [2018-11-23 16:10:50,987 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 16:10:50,987 INFO L276 IsEmpty]: Start isEmpty. Operand 86246 states and 99648 transitions. [2018-11-23 16:10:51,023 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 488 [2018-11-23 16:10:51,024 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:10:51,024 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:10:51,024 INFO L423 AbstractCegarLoop]: === Iteration 41 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:10:51,024 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:10:51,024 INFO L82 PathProgramCache]: Analyzing trace with hash 1104071115, now seen corresponding path program 1 times [2018-11-23 16:10:51,024 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:10:51,024 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:10:51,025 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:10:51,025 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:10:51,025 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:10:51,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:10:51,149 INFO L134 CoverageAnalysis]: Checked inductivity of 649 backedges. 22 proven. 17 refuted. 0 times theorem prover too weak. 610 trivial. 0 not checked. [2018-11-23 16:10:51,149 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:10:51,149 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:10:51,156 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:10:51,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:10:51,286 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:10:51,394 INFO L134 CoverageAnalysis]: Checked inductivity of 649 backedges. 271 proven. 0 refuted. 0 times theorem prover too weak. 378 trivial. 0 not checked. [2018-11-23 16:10:51,416 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 16:10:51,416 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2018-11-23 16:10:51,416 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 16:10:51,417 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 16:10:51,417 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:10:51,417 INFO L87 Difference]: Start difference. First operand 86246 states and 99648 transitions. Second operand 6 states. [2018-11-23 16:10:57,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:10:57,168 INFO L93 Difference]: Finished difference Result 152619 states and 178434 transitions. [2018-11-23 16:10:57,168 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 16:10:57,168 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 487 [2018-11-23 16:10:57,169 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:10:57,321 INFO L225 Difference]: With dead ends: 152619 [2018-11-23 16:10:57,321 INFO L226 Difference]: Without dead ends: 66564 [2018-11-23 16:10:57,541 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 499 GetRequests, 493 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2018-11-23 16:10:57,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66564 states. [2018-11-23 16:11:03,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66564 to 66395. [2018-11-23 16:11:03,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66395 states. [2018-11-23 16:11:03,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66395 states to 66395 states and 74780 transitions. [2018-11-23 16:11:03,696 INFO L78 Accepts]: Start accepts. Automaton has 66395 states and 74780 transitions. Word has length 487 [2018-11-23 16:11:03,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:11:03,696 INFO L480 AbstractCegarLoop]: Abstraction has 66395 states and 74780 transitions. [2018-11-23 16:11:03,696 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 16:11:03,696 INFO L276 IsEmpty]: Start isEmpty. Operand 66395 states and 74780 transitions. [2018-11-23 16:11:03,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 566 [2018-11-23 16:11:03,732 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:11:03,732 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:11:03,733 INFO L423 AbstractCegarLoop]: === Iteration 42 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 16:11:03,733 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:11:03,733 INFO L82 PathProgramCache]: Analyzing trace with hash 1277419665, now seen corresponding path program 1 times [2018-11-23 16:11:03,733 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:11:03,733 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:11:03,733 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:11:03,733 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:11:03,734 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:11:03,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:11:03,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:11:03,915 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] CALL call ULTIMATE.init(); VAL [|old(~E_1~0)|=29, |old(~E_2~0)|=21, |old(~E_3~0)|=20, |old(~E_4~0)|=8, |old(~E_5~0)|=4, |old(~M_E~0)|=13, |old(~m_i~0)|=7, |old(~m_pc~0)|=25, |old(~m_st~0)|=12, |old(~T1_E~0)|=3, |old(~t1_i~0)|=26, |old(~t1_pc~0)|=24, |old(~t1_st~0)|=5, |old(~T2_E~0)|=27, |old(~t2_i~0)|=6, |old(~t2_pc~0)|=23, |old(~t2_st~0)|=10, |old(~T3_E~0)|=19, |old(~t3_i~0)|=30, |old(~t3_pc~0)|=22, |old(~t3_st~0)|=11, |old(~T4_E~0)|=31, |old(~t4_i~0)|=14, |old(~t4_pc~0)|=18, |old(~t4_st~0)|=9, |old(~T5_E~0)|=17, |old(~t5_i~0)|=28, |old(~t5_pc~0)|=15, |old(~t5_st~0)|=16, ~E_1~0=29, ~E_2~0=21, ~E_3~0=20, ~E_4~0=8, ~E_5~0=4, ~M_E~0=13, ~m_i~0=7, ~m_pc~0=25, ~m_st~0=12, ~T1_E~0=3, ~t1_i~0=26, ~t1_pc~0=24, ~t1_st~0=5, ~T2_E~0=27, ~t2_i~0=6, ~t2_pc~0=23, ~t2_st~0=10, ~T3_E~0=19, ~t3_i~0=30, ~t3_pc~0=22, ~t3_st~0=11, ~T4_E~0=31, ~t4_i~0=14, ~t4_pc~0=18, ~t4_st~0=9, ~T5_E~0=17, ~t5_i~0=28, ~t5_pc~0=15, ~t5_st~0=16] [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; VAL [|old(~E_1~0)|=29, |old(~E_2~0)|=21, |old(~E_3~0)|=20, |old(~E_4~0)|=8, |old(~E_5~0)|=4, |old(~M_E~0)|=13, |old(~m_i~0)|=7, |old(~m_pc~0)|=25, |old(~m_st~0)|=12, |old(~T1_E~0)|=3, |old(~t1_i~0)|=26, |old(~t1_pc~0)|=24, |old(~t1_st~0)|=5, |old(~T2_E~0)|=27, |old(~t2_i~0)|=6, |old(~t2_pc~0)|=23, |old(~t2_st~0)|=10, |old(~T3_E~0)|=19, |old(~t3_i~0)|=30, |old(~t3_pc~0)|=22, |old(~t3_st~0)|=11, |old(~T4_E~0)|=31, |old(~t4_i~0)|=14, |old(~t4_pc~0)|=18, |old(~t4_st~0)|=9, |old(~T5_E~0)|=17, |old(~t5_i~0)|=28, |old(~t5_pc~0)|=15, |old(~t5_st~0)|=16, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=29, |old(~E_2~0)|=21, |old(~E_3~0)|=20, |old(~E_4~0)|=8, |old(~E_5~0)|=4, |old(~M_E~0)|=13, |old(~m_i~0)|=7, |old(~m_pc~0)|=25, |old(~m_st~0)|=12, |old(~T1_E~0)|=3, |old(~t1_i~0)|=26, |old(~t1_pc~0)|=24, |old(~t1_st~0)|=5, |old(~T2_E~0)|=27, |old(~t2_i~0)|=6, |old(~t2_pc~0)|=23, |old(~t2_st~0)|=10, |old(~T3_E~0)|=19, |old(~t3_i~0)|=30, |old(~t3_pc~0)|=22, |old(~t3_st~0)|=11, |old(~T4_E~0)|=31, |old(~t4_i~0)|=14, |old(~t4_pc~0)|=18, |old(~t4_st~0)|=9, |old(~T5_E~0)|=17, |old(~t5_i~0)|=28, |old(~t5_pc~0)|=15, |old(~t5_st~0)|=16, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #858#return; VAL [~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call #t~ret16 := main(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0] [?] havoc ~__retres1~7; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call init_model(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0] [?] ~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #792#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call start_simulation(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] havoc ~kernel_st~0;havoc ~tmp~3;havoc ~tmp___0~1;~kernel_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call update_channels(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #828#return; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call init_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 1 == ~m_i~0;~m_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #830#return; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call fire_delta_events(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 == ~T1_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 == ~T2_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 == ~T3_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 == ~T4_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 == ~T5_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 == ~E_5~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #832#return; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0;havoc ~tmp___4~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call #t~ret7 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~m_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #798#return; VAL [|activate_threads_#t~ret7|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647;~tmp~1 := #t~ret7;havoc #t~ret7; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call #t~ret8 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~t1_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] ~__retres1~1 := 0; VAL [is_transmit1_triggered_~__retres1~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #800#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret8|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp___0~0 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 != ~tmp___0~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call #t~ret9 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~t2_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] ~__retres1~2 := 0; VAL [is_transmit2_triggered_~__retres1~2=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #802#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___1~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 != ~tmp___1~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call #t~ret10 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~t3_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] ~__retres1~3 := 0; VAL [is_transmit3_triggered_~__retres1~3=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #804#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___2~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 != ~tmp___2~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call #t~ret11 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~t4_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] ~__retres1~4 := 0; VAL [is_transmit4_triggered_~__retres1~4=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #806#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret11|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647;~tmp___3~0 := #t~ret11;havoc #t~ret11; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 != ~tmp___3~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call #t~ret12 := is_transmit5_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] havoc ~__retres1~5; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~t5_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] ~__retres1~5 := 0; VAL [is_transmit5_triggered_~__retres1~5=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] #res := ~__retres1~5; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #808#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret12|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647;~tmp___4~0 := #t~ret12;havoc #t~ret12; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 != ~tmp___4~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #834#return; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call reset_delta_events(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~T1_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~T2_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~T3_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~T4_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~T5_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(1 == ~E_5~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #836#return; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !false; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] ~kernel_st~0 := 1; VAL [start_simulation_~kernel_st~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call eval(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] havoc ~tmp~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call #t~ret0 := exists_runnable_thread(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] havoc ~__retres1~6; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 == ~m_st~0;~__retres1~6 := 1; VAL [exists_runnable_thread_~__retres1~6=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] #res := ~__retres1~6; VAL [exists_runnable_thread_~__retres1~6=1, |exists_runnable_thread_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [exists_runnable_thread_~__retres1~6=1, |exists_runnable_thread_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #814#return; VAL [|eval_#t~ret0|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647;~tmp~0 := #t~ret0;havoc #t~ret0; VAL [eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 != ~tmp~0; VAL [eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 == ~m_st~0;havoc ~tmp_ndt_1~0;assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647;~tmp_ndt_1~0 := #t~nondet1;havoc #t~nondet1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !(0 != ~tmp_ndt_1~0); VAL [eval_~tmp_ndt_1~0=0, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 == ~t1_st~0;havoc ~tmp_ndt_2~0;assume -2147483648 <= #t~nondet2 && #t~nondet2 <= 2147483647;~tmp_ndt_2~0 := #t~nondet2;havoc #t~nondet2; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 != ~tmp_ndt_2~0;~t1_st~0 := 1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call transmit1(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] ~t1_pc~0 := 1;~t1_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #818#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 == ~t2_st~0;havoc ~tmp_ndt_3~0;assume -2147483648 <= #t~nondet3 && #t~nondet3 <= 2147483647;~tmp_ndt_3~0 := #t~nondet3;havoc #t~nondet3; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 != ~tmp_ndt_3~0;~t2_st~0 := 1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call transmit2(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] ~t2_pc~0 := 1;~t2_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #820#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 == ~t3_st~0;havoc ~tmp_ndt_4~0;assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647;~tmp_ndt_4~0 := #t~nondet4;havoc #t~nondet4; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 != ~tmp_ndt_4~0;~t3_st~0 := 1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call transmit3(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] ~t3_pc~0 := 1;~t3_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #822#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 == ~t4_st~0;havoc ~tmp_ndt_5~0;assume -2147483648 <= #t~nondet5 && #t~nondet5 <= 2147483647;~tmp_ndt_5~0 := #t~nondet5;havoc #t~nondet5; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 != ~tmp_ndt_5~0;~t4_st~0 := 1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call transmit4(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] ~t4_pc~0 := 1;~t4_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] RET #824#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 == ~t5_st~0;havoc ~tmp_ndt_6~0;assume -2147483648 <= #t~nondet6 && #t~nondet6 <= 2147483647;~tmp_ndt_6~0 := #t~nondet6;havoc #t~nondet6; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [?] assume 0 != ~tmp_ndt_6~0;~t5_st~0 := 1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=1] [?] CALL call transmit5(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=1] [?] assume 0 == ~t5_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=1] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=1] [?] ~t5_pc~0 := 1;~t5_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #826#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !false; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret0 := exists_runnable_thread(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~6; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 == ~m_st~0;~__retres1~6 := 1; VAL [exists_runnable_thread_~__retres1~6=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~6; VAL [exists_runnable_thread_~__retres1~6=1, |exists_runnable_thread_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [exists_runnable_thread_~__retres1~6=1, |exists_runnable_thread_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #814#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |eval_#t~ret0|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647;~tmp~0 := #t~ret0;havoc #t~ret0; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 != ~tmp~0; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 == ~m_st~0;havoc ~tmp_ndt_1~0;assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647;~tmp_ndt_1~0 := #t~nondet1;havoc #t~nondet1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 != ~tmp_ndt_1~0;~m_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call master(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 == ~m_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~E_1~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call immediate_notify(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0;havoc ~tmp___4~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret7 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~m_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #798#return; VAL [|activate_threads_#t~ret7|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647;~tmp~1 := #t~ret7;havoc #t~ret7; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret8 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~E_1~0;~__retres1~1 := 1; VAL [is_transmit1_triggered_~__retres1~1=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=1, |is_transmit1_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=1, |is_transmit1_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #800#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret8|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp___0~0 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 != ~tmp___0~0;~t1_st~0 := 0; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret9 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~2 := 0; VAL [is_transmit2_triggered_~__retres1~2=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #802#return; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___1~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___1~0); VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret10 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~3 := 0; VAL [is_transmit3_triggered_~__retres1~3=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #804#return; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___2~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___2~0); VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret11 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~4 := 0; VAL [is_transmit4_triggered_~__retres1~4=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #806#return; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret11|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647;~tmp___3~0 := #t~ret11;havoc #t~ret11; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___3~0); VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret12 := is_transmit5_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~5; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t5_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_5~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~5 := 0; VAL [is_transmit5_triggered_~__retres1~5=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~5; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #808#return; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret12|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647;~tmp___4~0 := #t~ret12;havoc #t~ret12; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___4~0); VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #810#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #812#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~E_1~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~m_pc~0 := 1;~m_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #816#return; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 == ~t1_st~0;havoc ~tmp_ndt_2~0;assume -2147483648 <= #t~nondet2 && #t~nondet2 <= 2147483647;~tmp_ndt_2~0 := #t~nondet2;havoc #t~nondet2; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 != ~tmp_ndt_2~0;~t1_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call transmit1(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 == ~t1_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~E_2~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call immediate_notify(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0;havoc ~tmp___4~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret7 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~m_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #798#return; VAL [|activate_threads_#t~ret7|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647;~tmp~1 := #t~ret7;havoc #t~ret7; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret8 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~1 := 0; VAL [is_transmit1_triggered_~__retres1~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #800#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret8|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp___0~0 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___0~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret9 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~E_2~0;~__retres1~2 := 1; VAL [is_transmit2_triggered_~__retres1~2=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=1, |is_transmit2_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=1, |is_transmit2_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #802#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___1~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 != ~tmp___1~0;~t2_st~0 := 0; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret10 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~3 := 0; VAL [is_transmit3_triggered_~__retres1~3=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #804#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___2~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___2~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret11 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~4 := 0; VAL [is_transmit4_triggered_~__retres1~4=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #806#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret11|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647;~tmp___3~0 := #t~ret11;havoc #t~ret11; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___3~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret12 := is_transmit5_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~5; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t5_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_5~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~5 := 0; VAL [is_transmit5_triggered_~__retres1~5=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~5; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #808#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret12|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647;~tmp___4~0 := #t~ret12;havoc #t~ret12; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___4~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #810#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #782#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~E_2~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~t1_pc~0 := 1;~t1_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #818#return; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 == ~t2_st~0;havoc ~tmp_ndt_3~0;assume -2147483648 <= #t~nondet3 && #t~nondet3 <= 2147483647;~tmp_ndt_3~0 := #t~nondet3;havoc #t~nondet3; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 != ~tmp_ndt_3~0;~t2_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call transmit2(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 == ~t2_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~E_3~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call immediate_notify(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0;havoc ~tmp___4~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret7 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~m_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #798#return; VAL [|activate_threads_#t~ret7|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647;~tmp~1 := #t~ret7;havoc #t~ret7; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret8 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~1 := 0; VAL [is_transmit1_triggered_~__retres1~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #800#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret8|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp___0~0 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___0~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret9 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~2 := 0; VAL [is_transmit2_triggered_~__retres1~2=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #802#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___1~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___1~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret10 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~E_3~0;~__retres1~3 := 1; VAL [is_transmit3_triggered_~__retres1~3=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=1, |is_transmit3_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=1, |is_transmit3_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #804#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___2~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 != ~tmp___2~0;~t3_st~0 := 0; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret11 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~4 := 0; VAL [is_transmit4_triggered_~__retres1~4=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #806#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp~1=0, |activate_threads_#t~ret11|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647;~tmp___3~0 := #t~ret11;havoc #t~ret11; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___3~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret12 := is_transmit5_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~5; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t5_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_5~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~5 := 0; VAL [is_transmit5_triggered_~__retres1~5=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~5; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #808#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret12|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647;~tmp___4~0 := #t~ret12;havoc #t~ret12; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___4~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #810#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #786#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~E_3~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~t2_pc~0 := 1;~t2_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #820#return; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 == ~t3_st~0;havoc ~tmp_ndt_4~0;assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647;~tmp_ndt_4~0 := #t~nondet4;havoc #t~nondet4; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 != ~tmp_ndt_4~0;~t3_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call transmit3(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 == ~t3_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~E_4~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call immediate_notify(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0;havoc ~tmp___4~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret7 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~m_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #798#return; VAL [|activate_threads_#t~ret7|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647;~tmp~1 := #t~ret7;havoc #t~ret7; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret8 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~1 := 0; VAL [is_transmit1_triggered_~__retres1~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #800#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret8|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp___0~0 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___0~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret9 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~2 := 0; VAL [is_transmit2_triggered_~__retres1~2=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #802#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___1~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___1~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret10 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~3 := 0; VAL [is_transmit3_triggered_~__retres1~3=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #804#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___2~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___2~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret11 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~E_4~0;~__retres1~4 := 1; VAL [is_transmit4_triggered_~__retres1~4=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=1, |is_transmit4_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=1, |is_transmit4_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #806#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret11|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647;~tmp___3~0 := #t~ret11;havoc #t~ret11; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 != ~tmp___3~0;~t4_st~0 := 0; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret12 := is_transmit5_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~5; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t5_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_5~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~5 := 0; VAL [is_transmit5_triggered_~__retres1~5=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~5; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #808#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp~1=0, |activate_threads_#t~ret12|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647;~tmp___4~0 := #t~ret12;havoc #t~ret12; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___4~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #810#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #784#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~E_4~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~t3_pc~0 := 1;~t3_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #822#return; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 == ~t4_st~0;havoc ~tmp_ndt_5~0;assume -2147483648 <= #t~nondet5 && #t~nondet5 <= 2147483647;~tmp_ndt_5~0 := #t~nondet5;havoc #t~nondet5; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 != ~tmp_ndt_5~0;~t4_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call transmit4(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 == ~t4_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~E_5~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call immediate_notify(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0;havoc ~tmp___4~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret7 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~m_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #798#return; VAL [|activate_threads_#t~ret7|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647;~tmp~1 := #t~ret7;havoc #t~ret7; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret8 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~1 := 0; VAL [is_transmit1_triggered_~__retres1~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #800#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret8|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp___0~0 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___0~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret9 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~2 := 0; VAL [is_transmit2_triggered_~__retres1~2=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #802#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___1~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___1~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret10 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~3 := 0; VAL [is_transmit3_triggered_~__retres1~3=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #804#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___2~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___2~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret11 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(1 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] ~__retres1~4 := 0; VAL [is_transmit4_triggered_~__retres1~4=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #806#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret11|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647;~tmp___3~0 := #t~ret11;havoc #t~ret11; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume !(0 != ~tmp___3~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] CALL call #t~ret12 := is_transmit5_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] havoc ~__retres1~5; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~t5_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 1 == ~E_5~0;~__retres1~5 := 1; VAL [is_transmit5_triggered_~__retres1~5=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] #res := ~__retres1~5; VAL [is_transmit5_triggered_~__retres1~5=1, |is_transmit5_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume true; VAL [is_transmit5_triggered_~__retres1~5=1, |is_transmit5_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] RET #808#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret12|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647;~tmp___4~0 := #t~ret12;havoc #t~ret12; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [?] assume 0 != ~tmp___4~0;~t5_st~0 := 0; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0] [?] assume true; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0] [?] RET #810#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0] [?] RET #790#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0] [?] ~E_5~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0] [?] ~t4_pc~0 := 1;~t4_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0] [?] RET #824#return; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0] [?] assume 0 == ~t5_st~0;havoc ~tmp_ndt_6~0;assume -2147483648 <= #t~nondet6 && #t~nondet6 <= 2147483647;~tmp_ndt_6~0 := #t~nondet6;havoc #t~nondet6; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0] [?] assume 0 != ~tmp_ndt_6~0;~t5_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1] [?] CALL call transmit5(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=1, |old(~t5_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1] [?] assume !(0 == ~t5_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=1, |old(~t5_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1] [?] assume 1 == ~t5_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=1, |old(~t5_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1] [?] CALL call error(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=1, |old(~t5_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=1, |old(~t5_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1] [?] CALL call ULTIMATE.init(); VAL [old(~E_1~0)=29, old(~E_2~0)=21, old(~E_3~0)=20, old(~E_4~0)=8, old(~E_5~0)=4, old(~M_E~0)=13, old(~m_i~0)=7, old(~m_pc~0)=25, old(~m_st~0)=12, old(~T1_E~0)=3, old(~t1_i~0)=26, old(~t1_pc~0)=24, old(~t1_st~0)=5, old(~T2_E~0)=27, old(~t2_i~0)=6, old(~t2_pc~0)=23, old(~t2_st~0)=10, old(~T3_E~0)=19, old(~t3_i~0)=30, old(~t3_pc~0)=22, old(~t3_st~0)=11, old(~T4_E~0)=31, old(~t4_i~0)=14, old(~t4_pc~0)=18, old(~t4_st~0)=9, old(~T5_E~0)=17, old(~t5_i~0)=28, old(~t5_pc~0)=15, old(~t5_st~0)=16, ~E_1~0=29, ~E_2~0=21, ~E_3~0=20, ~E_4~0=8, ~E_5~0=4, ~M_E~0=13, ~m_i~0=7, ~m_pc~0=25, ~m_st~0=12, ~T1_E~0=3, ~t1_i~0=26, ~t1_pc~0=24, ~t1_st~0=5, ~T2_E~0=27, ~t2_i~0=6, ~t2_pc~0=23, ~t2_st~0=10, ~T3_E~0=19, ~t3_i~0=30, ~t3_pc~0=22, ~t3_st~0=11, ~T4_E~0=31, ~t4_i~0=14, ~t4_pc~0=18, ~t4_st~0=9, ~T5_E~0=17, ~t5_i~0=28, ~t5_pc~0=15, ~t5_st~0=16] [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~m_i~0 := 0; [L28] ~t1_i~0 := 0; [L29] ~t2_i~0 := 0; [L30] ~t3_i~0 := 0; [L31] ~t4_i~0 := 0; [L32] ~t5_i~0 := 0; [L33] ~M_E~0 := 2; [L34] ~T1_E~0 := 2; [L35] ~T2_E~0 := 2; [L36] ~T3_E~0 := 2; [L37] ~T4_E~0 := 2; [L38] ~T5_E~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; VAL [old(~E_1~0)=29, old(~E_2~0)=21, old(~E_3~0)=20, old(~E_4~0)=8, old(~E_5~0)=4, old(~M_E~0)=13, old(~m_i~0)=7, old(~m_pc~0)=25, old(~m_st~0)=12, old(~T1_E~0)=3, old(~t1_i~0)=26, old(~t1_pc~0)=24, old(~t1_st~0)=5, old(~T2_E~0)=27, old(~t2_i~0)=6, old(~t2_pc~0)=23, old(~t2_st~0)=10, old(~T3_E~0)=19, old(~t3_i~0)=30, old(~t3_pc~0)=22, old(~t3_st~0)=11, old(~T4_E~0)=31, old(~t4_i~0)=14, old(~t4_pc~0)=18, old(~t4_st~0)=9, old(~T5_E~0)=17, old(~t5_i~0)=28, old(~t5_pc~0)=15, old(~t5_st~0)=16, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0] [?] ensures true; VAL [old(~E_1~0)=29, old(~E_2~0)=21, old(~E_3~0)=20, old(~E_4~0)=8, old(~E_5~0)=4, old(~M_E~0)=13, old(~m_i~0)=7, old(~m_pc~0)=25, old(~m_st~0)=12, old(~T1_E~0)=3, old(~t1_i~0)=26, old(~t1_pc~0)=24, old(~t1_st~0)=5, old(~T2_E~0)=27, old(~t2_i~0)=6, old(~t2_pc~0)=23, old(~t2_st~0)=10, old(~T3_E~0)=19, old(~t3_i~0)=30, old(~t3_pc~0)=22, old(~t3_st~0)=11, old(~T4_E~0)=31, old(~t4_i~0)=14, old(~t4_pc~0)=18, old(~t4_st~0)=9, old(~T5_E~0)=17, old(~t5_i~0)=28, old(~t5_pc~0)=15, old(~t5_st~0)=16, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0] [?] RET call ULTIMATE.init(); VAL [~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0] [?] CALL call #t~ret16 := main(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0] [L935] havoc ~__retres1~7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0] [L939] CALL call init_model(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0] [L846] ~m_i~0 := 1; [L847] ~t1_i~0 := 1; [L848] ~t2_i~0 := 1; [L849] ~t3_i~0 := 1; [L850] ~t4_i~0 := 1; [L851] ~t5_i~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L842-L855] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L939] RET call init_model(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L940] CALL call start_simulation(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L876] havoc ~kernel_st~0; [L877] havoc ~tmp~3; [L878] havoc ~tmp___0~1; [L882] ~kernel_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L883] CALL call update_channels(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L379-L386] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L883] RET call update_channels(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L884] CALL call init_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L391-L395] assume 1 == ~m_i~0; [L392] ~m_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L396-L400] assume 1 == ~t1_i~0; [L397] ~t1_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L401-L405] assume 1 == ~t2_i~0; [L402] ~t2_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L406-L410] assume 1 == ~t3_i~0; [L407] ~t3_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L411-L415] assume 1 == ~t4_i~0; [L412] ~t4_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L416-L420] assume 1 == ~t5_i~0; [L417] ~t5_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L387-L424] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L884] RET call init_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L885] CALL call fire_delta_events(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L576-L580] assume !(0 == ~M_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L581-L585] assume !(0 == ~T1_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L586-L590] assume !(0 == ~T2_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L591-L595] assume !(0 == ~T3_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L596-L600] assume !(0 == ~T4_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L601-L605] assume !(0 == ~T5_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L606-L610] assume !(0 == ~E_1~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L611-L615] assume !(0 == ~E_2~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L616-L620] assume !(0 == ~E_3~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L621-L625] assume !(0 == ~E_4~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L626-L630] assume !(0 == ~E_5~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L572-L634] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L885] RET call fire_delta_events(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L886] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L699] havoc ~tmp~1; [L700] havoc ~tmp___0~0; [L701] havoc ~tmp___1~0; [L702] havoc ~tmp___2~0; [L703] havoc ~tmp___3~0; [L704] havoc ~tmp___4~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L708] CALL call #t~ret7 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L266] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L269-L278] assume !(1 == ~m_pc~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L279] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L281] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L44] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L708] RET call #t~ret7 := is_master_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L708] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L708] ~tmp~1 := #t~ret7; [L708] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp~1=0] [L710-L714] assume !(0 != ~tmp~1); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp~1=0] [L716] CALL call #t~ret8 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L285] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L288-L297] assume !(1 == ~t1_pc~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L298] ~__retres1~1 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L300] #res := ~__retres1~1; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L45] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L716] RET call #t~ret8 := is_transmit1_triggered(); VAL [#t~ret8=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp~1=0] [L716] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L716] ~tmp___0~0 := #t~ret8; [L716] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp___0~0=0, ~tmp~1=0] [L718-L722] assume !(0 != ~tmp___0~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp___0~0=0, ~tmp~1=0] [L724] CALL call #t~ret9 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L304] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L307-L316] assume !(1 == ~t2_pc~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L317] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L319] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L46] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L724] RET call #t~ret9 := is_transmit2_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp___0~0=0, ~tmp~1=0] [L724] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L724] ~tmp___1~0 := #t~ret9; [L724] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L726-L730] assume !(0 != ~tmp___1~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L732] CALL call #t~ret10 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L323] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L326-L335] assume !(1 == ~t3_pc~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L336] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L338] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L47] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L732] RET call #t~ret10 := is_transmit3_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L732] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L732] ~tmp___2~0 := #t~ret10; [L732] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L734-L738] assume !(0 != ~tmp___2~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L740] CALL call #t~ret11 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L342] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L345-L354] assume !(1 == ~t4_pc~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L355] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L357] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L48] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L740] RET call #t~ret11 := is_transmit4_triggered(); VAL [#t~ret11=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L740] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647; [L740] ~tmp___3~0 := #t~ret11; [L740] havoc #t~ret11; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L742-L746] assume !(0 != ~tmp___3~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L748] CALL call #t~ret12 := is_transmit5_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L361] havoc ~__retres1~5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L364-L373] assume !(1 == ~t5_pc~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L374] ~__retres1~5 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~5=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L376] #res := ~__retres1~5; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~5=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L49] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~5=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L748] RET call #t~ret12 := is_transmit5_triggered(); VAL [#t~ret12=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L748] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647; [L748] ~tmp___4~0 := #t~ret12; [L748] havoc #t~ret12; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp___4~0=0, ~tmp~1=0] [L750-L754] assume !(0 != ~tmp___4~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp___4~0=0, ~tmp~1=0] [L698-L758] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp___4~0=0, ~tmp~1=0] [L886] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L887] CALL call reset_delta_events(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L639-L643] assume !(1 == ~M_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L644-L648] assume !(1 == ~T1_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L649-L653] assume !(1 == ~T2_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L654-L658] assume !(1 == ~T3_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L659-L663] assume !(1 == ~T4_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L664-L668] assume !(1 == ~T5_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L669-L673] assume !(1 == ~E_1~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L674-L678] assume !(1 == ~E_2~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L679-L683] assume !(1 == ~E_3~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L684-L688] assume !(1 == ~E_4~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L689-L693] assume !(1 == ~E_5~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L635-L697] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L887] RET call reset_delta_events(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L890-L927] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L893] ~kernel_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~kernel_st~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L894] CALL call eval(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L467] havoc ~tmp~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L471-L565] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L474] CALL call #t~ret0 := exists_runnable_thread(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L426] havoc ~__retres1~6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L429-L459] assume 0 == ~m_st~0; [L430] ~__retres1~6 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~6=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L462] #res := ~__retres1~6; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~6=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L425-L464] ensures true; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~6=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L474] RET call #t~ret0 := exists_runnable_thread(); VAL [#t~ret0=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L474] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647; [L474] ~tmp~0 := #t~ret0; [L474] havoc #t~ret0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp~0=1] [L476-L480] assume 0 != ~tmp~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp~0=1] [L481-L494] assume 0 == ~m_st~0; [L482] havoc ~tmp_ndt_1~0; [L483] assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647; [L483] ~tmp_ndt_1~0 := #t~nondet1; [L483] havoc #t~nondet1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp~0=1] [L484-L491] assume !(0 != ~tmp_ndt_1~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp~0=1] [L495-L508] assume 0 == ~t1_st~0; [L496] havoc ~tmp_ndt_2~0; [L497] assume -2147483648 <= #t~nondet2 && #t~nondet2 <= 2147483647; [L497] ~tmp_ndt_2~0 := #t~nondet2; [L497] havoc #t~nondet2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp~0=1] [L498-L505] assume 0 != ~tmp_ndt_2~0; [L500] ~t1_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp~0=1] [L501] CALL call transmit1(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L96-L104] assume 0 == ~t1_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L107-L119] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L109] ~t1_pc~0 := 1; [L110] ~t1_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L92-L126] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L501] RET call transmit1(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp~0=1] [L509-L522] assume 0 == ~t2_st~0; [L510] havoc ~tmp_ndt_3~0; [L511] assume -2147483648 <= #t~nondet3 && #t~nondet3 <= 2147483647; [L511] ~tmp_ndt_3~0 := #t~nondet3; [L511] havoc #t~nondet3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp~0=1] [L512-L519] assume 0 != ~tmp_ndt_3~0; [L514] ~t2_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp~0=1] [L515] CALL call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L131-L139] assume 0 == ~t2_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L142-L154] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L144] ~t2_pc~0 := 1; [L145] ~t2_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L127-L161] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L515] RET call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp~0=1] [L523-L536] assume 0 == ~t3_st~0; [L524] havoc ~tmp_ndt_4~0; [L525] assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647; [L525] ~tmp_ndt_4~0 := #t~nondet4; [L525] havoc #t~nondet4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp~0=1] [L526-L533] assume 0 != ~tmp_ndt_4~0; [L528] ~t3_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp~0=1] [L529] CALL call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L166-L174] assume 0 == ~t3_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L177-L189] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L179] ~t3_pc~0 := 1; [L180] ~t3_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L162-L196] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L529] RET call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp~0=1] [L537-L550] assume 0 == ~t4_st~0; [L538] havoc ~tmp_ndt_5~0; [L539] assume -2147483648 <= #t~nondet5 && #t~nondet5 <= 2147483647; [L539] ~tmp_ndt_5~0 := #t~nondet5; [L539] havoc #t~nondet5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L540-L547] assume 0 != ~tmp_ndt_5~0; [L542] ~t4_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L543] CALL call transmit4(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L201-L209] assume 0 == ~t4_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L212-L224] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L214] ~t4_pc~0 := 1; [L215] ~t4_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L197-L231] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L543] RET call transmit4(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L551-L564] assume 0 == ~t5_st~0; [L552] havoc ~tmp_ndt_6~0; [L553] assume -2147483648 <= #t~nondet6 && #t~nondet6 <= 2147483647; [L553] ~tmp_ndt_6~0 := #t~nondet6; [L553] havoc #t~nondet6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L554-L561] assume 0 != ~tmp_ndt_6~0; [L556] ~t5_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=1, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L557] CALL call transmit5(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=1] [L236-L244] assume 0 == ~t5_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=1] [L247-L257] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=1] [L249] ~t5_pc~0 := 1; [L250] ~t5_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L232-L264] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L557] RET call transmit5(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L471-L565] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L474] CALL call #t~ret0 := exists_runnable_thread(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L426] havoc ~__retres1~6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L429-L459] assume 0 == ~m_st~0; [L430] ~__retres1~6 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~6=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L462] #res := ~__retres1~6; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~6=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L425-L464] ensures true; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~6=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L474] RET call #t~ret0 := exists_runnable_thread(); VAL [#t~ret0=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L474] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647; [L474] ~tmp~0 := #t~ret0; [L474] havoc #t~ret0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L476-L480] assume 0 != ~tmp~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L481-L494] assume 0 == ~m_st~0; [L482] havoc ~tmp_ndt_1~0; [L483] assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647; [L483] ~tmp_ndt_1~0 := #t~nondet1; [L483] havoc #t~nondet1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L484-L491] assume 0 != ~tmp_ndt_1~0; [L486] ~m_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L487] CALL call master(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L55-L63] assume 0 == ~m_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L66-L84] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L69] ~E_1~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L70] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L764] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L699] havoc ~tmp~1; [L700] havoc ~tmp___0~0; [L701] havoc ~tmp___1~0; [L702] havoc ~tmp___2~0; [L703] havoc ~tmp___3~0; [L704] havoc ~tmp___4~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] CALL call #t~ret7 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L266] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L269-L278] assume !(1 == ~m_pc~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L279] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~0=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L281] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~0=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L44] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~0=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] RET call #t~ret7 := is_master_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L708] ~tmp~1 := #t~ret7; [L708] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L710-L714] assume !(0 != ~tmp~1); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L716] CALL call #t~ret8 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L285] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L288-L297] assume 1 == ~t1_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L289-L294] assume 1 == ~E_1~0; [L290] ~__retres1~1 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~1=1, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L300] #res := ~__retres1~1; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~1=1, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L45] ensures true; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~1=1, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L716] RET call #t~ret8 := is_transmit1_triggered(); VAL [#t~ret8=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L716] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L716] ~tmp___0~0 := #t~ret8; [L716] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp~1=0] [L718-L722] assume 0 != ~tmp___0~0; [L719] ~t1_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp~1=0] [L724] CALL call #t~ret9 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L304] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L307-L316] assume 1 == ~t2_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L308-L313] assume !(1 == ~E_2~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L317] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~2=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L319] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~2=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L46] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~2=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L724] RET call #t~ret9 := is_transmit2_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp~1=0] [L724] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L724] ~tmp___1~0 := #t~ret9; [L724] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp~1=0] [L726-L730] assume !(0 != ~tmp___1~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp~1=0] [L732] CALL call #t~ret10 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L323] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L326-L335] assume 1 == ~t3_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L327-L332] assume !(1 == ~E_3~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L336] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~3=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L338] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~3=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L47] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~3=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L732] RET call #t~ret10 := is_transmit3_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp~1=0] [L732] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L732] ~tmp___2~0 := #t~ret10; [L732] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L734-L738] assume !(0 != ~tmp___2~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L740] CALL call #t~ret11 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L342] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L345-L354] assume 1 == ~t4_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L346-L351] assume !(1 == ~E_4~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L355] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~4=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L357] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~4=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L48] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~4=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L740] RET call #t~ret11 := is_transmit4_triggered(); VAL [#t~ret11=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L740] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647; [L740] ~tmp___3~0 := #t~ret11; [L740] havoc #t~ret11; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L742-L746] assume !(0 != ~tmp___3~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L748] CALL call #t~ret12 := is_transmit5_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L361] havoc ~__retres1~5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L364-L373] assume 1 == ~t5_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] WARNING: YOUR LOGFILE WAS TOO LONG, SOME LINES IN THE MIDDLE WERE REMOVED. [L145] ~t2_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L515] RET call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp~0=1] [L523] COND TRUE 0 == ~t3_st~0 [L524] havoc ~tmp_ndt_4~0; [L525] assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647; [L525] ~tmp_ndt_4~0 := #t~nondet4; [L525] havoc #t~nondet4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp~0=1] [L526-L533] COND TRUE 0 != ~tmp_ndt_4~0 [L528] ~t3_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp~0=1] [L529] CALL call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L166] COND TRUE 0 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L177-L189] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L179] ~t3_pc~0 := 1; [L180] ~t3_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L529] RET call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp~0=1] [L537] COND TRUE 0 == ~t4_st~0 [L538] havoc ~tmp_ndt_5~0; [L539] assume -2147483648 <= #t~nondet5 && #t~nondet5 <= 2147483647; [L539] ~tmp_ndt_5~0 := #t~nondet5; [L539] havoc #t~nondet5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L540-L547] COND TRUE 0 != ~tmp_ndt_5~0 [L542] ~t4_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L543] CALL call transmit4(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L201] COND TRUE 0 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L212-L224] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L214] ~t4_pc~0 := 1; [L215] ~t4_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0] [L543] RET call transmit4(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L551] COND TRUE 0 == ~t5_st~0 [L552] havoc ~tmp_ndt_6~0; [L553] assume -2147483648 <= #t~nondet6 && #t~nondet6 <= 2147483647; [L553] ~tmp_ndt_6~0 := #t~nondet6; [L553] havoc #t~nondet6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L554-L561] COND TRUE 0 != ~tmp_ndt_6~0 [L556] ~t5_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=1, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L557] CALL call transmit5(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=1] [L236] COND TRUE 0 == ~t5_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=1] [L247-L257] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=1] [L249] ~t5_pc~0 := 1; [L250] ~t5_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L557] RET call transmit5(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L471-L565] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L474] CALL call #t~ret0 := exists_runnable_thread(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L426] havoc ~__retres1~6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L429] COND TRUE 0 == ~m_st~0 [L430] ~__retres1~6 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~6=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L462] #res := ~__retres1~6; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~__retres1~6=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L474] RET call #t~ret0 := exists_runnable_thread(); VAL [#t~ret0=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L474] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647; [L474] ~tmp~0 := #t~ret0; [L474] havoc #t~ret0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L476-L480] COND TRUE 0 != ~tmp~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L481] COND TRUE 0 == ~m_st~0 [L482] havoc ~tmp_ndt_1~0; [L483] assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647; [L483] ~tmp_ndt_1~0 := #t~nondet1; [L483] havoc #t~nondet1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L484-L491] COND TRUE 0 != ~tmp_ndt_1~0 [L486] ~m_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L487] CALL call master(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L55] COND TRUE 0 == ~m_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L66-L84] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L69] ~E_1~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L70] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L764] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L699] havoc ~tmp~1; [L700] havoc ~tmp___0~0; [L701] havoc ~tmp___1~0; [L702] havoc ~tmp___2~0; [L703] havoc ~tmp___3~0; [L704] havoc ~tmp___4~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] CALL call #t~ret7 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L266] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L269] COND FALSE !(1 == ~m_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L279] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~0=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L281] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~0=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] RET call #t~ret7 := is_master_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L708] ~tmp~1 := #t~ret7; [L708] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L710-L714] COND FALSE !(0 != ~tmp~1) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L716] CALL call #t~ret8 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L285] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L288] COND TRUE 1 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L289] COND TRUE 1 == ~E_1~0 [L290] ~__retres1~1 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~1=1, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L300] #res := ~__retres1~1; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~1=1, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L716] RET call #t~ret8 := is_transmit1_triggered(); VAL [#t~ret8=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L716] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L716] ~tmp___0~0 := #t~ret8; [L716] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp~1=0] [L718-L722] COND TRUE 0 != ~tmp___0~0 [L719] ~t1_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp~1=0] [L724] CALL call #t~ret9 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L304] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L307] COND TRUE 1 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L308] COND FALSE !(1 == ~E_2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L317] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~2=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L319] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~2=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L724] RET call #t~ret9 := is_transmit2_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp~1=0] [L724] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L724] ~tmp___1~0 := #t~ret9; [L724] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp~1=0] [L726-L730] COND FALSE !(0 != ~tmp___1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp~1=0] [L732] CALL call #t~ret10 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L323] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L326] COND TRUE 1 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L327] COND FALSE !(1 == ~E_3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L336] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~3=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L338] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~3=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L732] RET call #t~ret10 := is_transmit3_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp~1=0] [L732] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L732] ~tmp___2~0 := #t~ret10; [L732] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L734-L738] COND FALSE !(0 != ~tmp___2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L740] CALL call #t~ret11 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L342] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L345] COND TRUE 1 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L346] COND FALSE !(1 == ~E_4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L355] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~4=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L357] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~4=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L740] RET call #t~ret11 := is_transmit4_triggered(); VAL [#t~ret11=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L740] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647; [L740] ~tmp___3~0 := #t~ret11; [L740] havoc #t~ret11; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L742-L746] COND FALSE !(0 != ~tmp___3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L748] CALL call #t~ret12 := is_transmit5_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L361] havoc ~__retres1~5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L364] COND TRUE 1 == ~t5_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L365] COND FALSE !(1 == ~E_5~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L374] ~__retres1~5 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~5=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L376] #res := ~__retres1~5; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~5=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L748] RET call #t~ret12 := is_transmit5_triggered(); VAL [#t~ret12=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L748] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647; [L748] ~tmp___4~0 := #t~ret12; [L748] havoc #t~ret12; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp___4~0=0, ~tmp~1=0] [L750-L754] COND FALSE !(0 != ~tmp___4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp___4~0=0, ~tmp~1=0] [L764] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L70] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L71] ~E_1~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L74-L81] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L76] ~m_pc~0 := 1; [L77] ~m_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L487] RET call master(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L495] COND TRUE 0 == ~t1_st~0 [L496] havoc ~tmp_ndt_2~0; [L497] assume -2147483648 <= #t~nondet2 && #t~nondet2 <= 2147483647; [L497] ~tmp_ndt_2~0 := #t~nondet2; [L497] havoc #t~nondet2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L498-L505] COND TRUE 0 != ~tmp_ndt_2~0 [L500] ~t1_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L501] CALL call transmit1(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L96] COND FALSE !(0 == ~t1_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L99] COND TRUE 1 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L115] ~E_2~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L116] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L764] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L699] havoc ~tmp~1; [L700] havoc ~tmp___0~0; [L701] havoc ~tmp___1~0; [L702] havoc ~tmp___2~0; [L703] havoc ~tmp___3~0; [L704] havoc ~tmp___4~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] CALL call #t~ret7 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L266] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L269] COND TRUE 1 == ~m_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L270] COND FALSE !(1 == ~M_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L279] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L281] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] RET call #t~ret7 := is_master_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L708] ~tmp~1 := #t~ret7; [L708] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L710-L714] COND FALSE !(0 != ~tmp~1) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L716] CALL call #t~ret8 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L285] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L288] COND TRUE 1 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L289] COND FALSE !(1 == ~E_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L298] ~__retres1~1 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L300] #res := ~__retres1~1; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L716] RET call #t~ret8 := is_transmit1_triggered(); VAL [#t~ret8=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L716] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L716] ~tmp___0~0 := #t~ret8; [L716] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L718-L722] COND FALSE !(0 != ~tmp___0~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L724] CALL call #t~ret9 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L304] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L307] COND TRUE 1 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L308] COND TRUE 1 == ~E_2~0 [L309] ~__retres1~2 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~2=1, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L319] #res := ~__retres1~2; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~2=1, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L724] RET call #t~ret9 := is_transmit2_triggered(); VAL [#t~ret9=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L724] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L724] ~tmp___1~0 := #t~ret9; [L724] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp~1=0] [L726-L730] COND TRUE 0 != ~tmp___1~0 [L727] ~t2_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp~1=0] [L732] CALL call #t~ret10 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L323] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L326] COND TRUE 1 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L327] COND FALSE !(1 == ~E_3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L336] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L338] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L732] RET call #t~ret10 := is_transmit3_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp~1=0] [L732] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L732] ~tmp___2~0 := #t~ret10; [L732] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp~1=0] [L734-L738] COND FALSE !(0 != ~tmp___2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp~1=0] [L740] CALL call #t~ret11 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L342] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L345] COND TRUE 1 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L346] COND FALSE !(1 == ~E_4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L355] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L357] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L740] RET call #t~ret11 := is_transmit4_triggered(); VAL [#t~ret11=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp~1=0] [L740] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647; [L740] ~tmp___3~0 := #t~ret11; [L740] havoc #t~ret11; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L742-L746] COND FALSE !(0 != ~tmp___3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L748] CALL call #t~ret12 := is_transmit5_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L361] havoc ~__retres1~5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L364] COND TRUE 1 == ~t5_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L365] COND FALSE !(1 == ~E_5~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L374] ~__retres1~5 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~5=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L376] #res := ~__retres1~5; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~5=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L748] RET call #t~ret12 := is_transmit5_triggered(); VAL [#t~ret12=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L748] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647; [L748] ~tmp___4~0 := #t~ret12; [L748] havoc #t~ret12; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp___4~0=0, ~tmp~1=0] [L750-L754] COND FALSE !(0 != ~tmp___4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp___4~0=0, ~tmp~1=0] [L764] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L116] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L117] ~E_2~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L107-L119] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L109] ~t1_pc~0 := 1; [L110] ~t1_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L501] RET call transmit1(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L509] COND TRUE 0 == ~t2_st~0 [L510] havoc ~tmp_ndt_3~0; [L511] assume -2147483648 <= #t~nondet3 && #t~nondet3 <= 2147483647; [L511] ~tmp_ndt_3~0 := #t~nondet3; [L511] havoc #t~nondet3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L512-L519] COND TRUE 0 != ~tmp_ndt_3~0 [L514] ~t2_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L515] CALL call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L131] COND FALSE !(0 == ~t2_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L134] COND TRUE 1 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L150] ~E_3~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L151] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L764] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L699] havoc ~tmp~1; [L700] havoc ~tmp___0~0; [L701] havoc ~tmp___1~0; [L702] havoc ~tmp___2~0; [L703] havoc ~tmp___3~0; [L704] havoc ~tmp___4~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] CALL call #t~ret7 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L266] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L269] COND TRUE 1 == ~m_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L270] COND FALSE !(1 == ~M_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L279] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L281] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] RET call #t~ret7 := is_master_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L708] ~tmp~1 := #t~ret7; [L708] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L710-L714] COND FALSE !(0 != ~tmp~1) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L716] CALL call #t~ret8 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L285] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L288] COND TRUE 1 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L289] COND FALSE !(1 == ~E_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L298] ~__retres1~1 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L300] #res := ~__retres1~1; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L716] RET call #t~ret8 := is_transmit1_triggered(); VAL [#t~ret8=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L716] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L716] ~tmp___0~0 := #t~ret8; [L716] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L718-L722] COND FALSE !(0 != ~tmp___0~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L724] CALL call #t~ret9 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L304] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L307] COND TRUE 1 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L308] COND FALSE !(1 == ~E_2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L317] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L319] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L724] RET call #t~ret9 := is_transmit2_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L724] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L724] ~tmp___1~0 := #t~ret9; [L724] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L726-L730] COND FALSE !(0 != ~tmp___1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L732] CALL call #t~ret10 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L323] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L326] COND TRUE 1 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L327] COND TRUE 1 == ~E_3~0 [L328] ~__retres1~3 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~3=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L338] #res := ~__retres1~3; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~3=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L732] RET call #t~ret10 := is_transmit3_triggered(); VAL [#t~ret10=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L732] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L732] ~tmp___2~0 := #t~ret10; [L732] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp~1=0] [L734-L738] COND TRUE 0 != ~tmp___2~0 [L735] ~t3_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp~1=0] [L740] CALL call #t~ret11 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L342] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L345] COND TRUE 1 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L346] COND FALSE !(1 == ~E_4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L355] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L357] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L740] RET call #t~ret11 := is_transmit4_triggered(); VAL [#t~ret11=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp~1=0] [L740] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647; [L740] ~tmp___3~0 := #t~ret11; [L740] havoc #t~ret11; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp___3~0=0, ~tmp~1=0] [L742-L746] COND FALSE !(0 != ~tmp___3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp___3~0=0, ~tmp~1=0] [L748] CALL call #t~ret12 := is_transmit5_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L361] havoc ~__retres1~5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L364] COND TRUE 1 == ~t5_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L365] COND FALSE !(1 == ~E_5~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L374] ~__retres1~5 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~5=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L376] #res := ~__retres1~5; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~5=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L748] RET call #t~ret12 := is_transmit5_triggered(); VAL [#t~ret12=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp___3~0=0, ~tmp~1=0] [L748] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647; [L748] ~tmp___4~0 := #t~ret12; [L748] havoc #t~ret12; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp___3~0=0, ~tmp___4~0=0, ~tmp~1=0] [L750-L754] COND FALSE !(0 != ~tmp___4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp___3~0=0, ~tmp___4~0=0, ~tmp~1=0] [L764] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L151] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L152] ~E_3~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L142-L154] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L144] ~t2_pc~0 := 1; [L145] ~t2_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L515] RET call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L523] COND TRUE 0 == ~t3_st~0 [L524] havoc ~tmp_ndt_4~0; [L525] assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647; [L525] ~tmp_ndt_4~0 := #t~nondet4; [L525] havoc #t~nondet4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L526-L533] COND TRUE 0 != ~tmp_ndt_4~0 [L528] ~t3_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L529] CALL call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L166] COND FALSE !(0 == ~t3_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L169] COND TRUE 1 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L185] ~E_4~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L186] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L764] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L699] havoc ~tmp~1; [L700] havoc ~tmp___0~0; [L701] havoc ~tmp___1~0; [L702] havoc ~tmp___2~0; [L703] havoc ~tmp___3~0; [L704] havoc ~tmp___4~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] CALL call #t~ret7 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L266] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L269] COND TRUE 1 == ~m_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L270] COND FALSE !(1 == ~M_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L279] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L281] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] RET call #t~ret7 := is_master_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L708] ~tmp~1 := #t~ret7; [L708] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L710-L714] COND FALSE !(0 != ~tmp~1) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L716] CALL call #t~ret8 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L285] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L288] COND TRUE 1 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L289] COND FALSE !(1 == ~E_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L298] ~__retres1~1 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L300] #res := ~__retres1~1; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L716] RET call #t~ret8 := is_transmit1_triggered(); VAL [#t~ret8=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L716] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L716] ~tmp___0~0 := #t~ret8; [L716] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L718-L722] COND FALSE !(0 != ~tmp___0~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L724] CALL call #t~ret9 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L304] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L307] COND TRUE 1 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L308] COND FALSE !(1 == ~E_2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L317] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L319] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L724] RET call #t~ret9 := is_transmit2_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L724] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L724] ~tmp___1~0 := #t~ret9; [L724] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L726-L730] COND FALSE !(0 != ~tmp___1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L732] CALL call #t~ret10 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L323] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L326] COND TRUE 1 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L327] COND FALSE !(1 == ~E_3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L336] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L338] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L732] RET call #t~ret10 := is_transmit3_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L732] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L732] ~tmp___2~0 := #t~ret10; [L732] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L734-L738] COND FALSE !(0 != ~tmp___2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L740] CALL call #t~ret11 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L342] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L345] COND TRUE 1 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L346] COND TRUE 1 == ~E_4~0 [L347] ~__retres1~4 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~4=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L357] #res := ~__retres1~4; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~4=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L740] RET call #t~ret11 := is_transmit4_triggered(); VAL [#t~ret11=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L740] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647; [L740] ~tmp___3~0 := #t~ret11; [L740] havoc #t~ret11; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=1, ~tmp~1=0] [L742-L746] COND TRUE 0 != ~tmp___3~0 [L743] ~t4_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=1, ~tmp~1=0] [L748] CALL call #t~ret12 := is_transmit5_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L361] havoc ~__retres1~5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L364] COND TRUE 1 == ~t5_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L365] COND FALSE !(1 == ~E_5~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L374] ~__retres1~5 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~5=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L376] #res := ~__retres1~5; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~5=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L748] RET call #t~ret12 := is_transmit5_triggered(); VAL [#t~ret12=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=1, ~tmp~1=0] [L748] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647; [L748] ~tmp___4~0 := #t~ret12; [L748] havoc #t~ret12; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=1, ~tmp___4~0=0, ~tmp~1=0] [L750-L754] COND FALSE !(0 != ~tmp___4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=1, ~tmp___4~0=0, ~tmp~1=0] [L764] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L186] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L187] ~E_4~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L177-L189] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L179] ~t3_pc~0 := 1; [L180] ~t3_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L529] RET call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L537] COND TRUE 0 == ~t4_st~0 [L538] havoc ~tmp_ndt_5~0; [L539] assume -2147483648 <= #t~nondet5 && #t~nondet5 <= 2147483647; [L539] ~tmp_ndt_5~0 := #t~nondet5; [L539] havoc #t~nondet5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L540-L547] COND TRUE 0 != ~tmp_ndt_5~0 [L542] ~t4_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L543] CALL call transmit4(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L201] COND FALSE !(0 == ~t4_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L204] COND TRUE 1 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L220] ~E_5~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L221] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L764] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L699] havoc ~tmp~1; [L700] havoc ~tmp___0~0; [L701] havoc ~tmp___1~0; [L702] havoc ~tmp___2~0; [L703] havoc ~tmp___3~0; [L704] havoc ~tmp___4~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] CALL call #t~ret7 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L266] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L269] COND TRUE 1 == ~m_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L270] COND FALSE !(1 == ~M_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L279] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L281] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] RET call #t~ret7 := is_master_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L708] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L708] ~tmp~1 := #t~ret7; [L708] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L710-L714] COND FALSE !(0 != ~tmp~1) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L716] CALL call #t~ret8 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L285] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L288] COND TRUE 1 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L289] COND FALSE !(1 == ~E_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L298] ~__retres1~1 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L300] #res := ~__retres1~1; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L716] RET call #t~ret8 := is_transmit1_triggered(); VAL [#t~ret8=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp~1=0] [L716] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L716] ~tmp___0~0 := #t~ret8; [L716] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L718-L722] COND FALSE !(0 != ~tmp___0~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L724] CALL call #t~ret9 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L304] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L307] COND TRUE 1 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L308] COND FALSE !(1 == ~E_2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L317] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L319] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L724] RET call #t~ret9 := is_transmit2_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L724] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L724] ~tmp___1~0 := #t~ret9; [L724] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L726-L730] COND FALSE !(0 != ~tmp___1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L732] CALL call #t~ret10 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L323] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L326] COND TRUE 1 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L327] COND FALSE !(1 == ~E_3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L336] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L338] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L732] RET call #t~ret10 := is_transmit3_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L732] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L732] ~tmp___2~0 := #t~ret10; [L732] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L734-L738] COND FALSE !(0 != ~tmp___2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L740] CALL call #t~ret11 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L342] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L345] COND TRUE 1 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L346] COND FALSE !(1 == ~E_4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L355] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L357] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L740] RET call #t~ret11 := is_transmit4_triggered(); VAL [#t~ret11=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L740] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647; [L740] ~tmp___3~0 := #t~ret11; [L740] havoc #t~ret11; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L742-L746] COND FALSE !(0 != ~tmp___3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L748] CALL call #t~ret12 := is_transmit5_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L361] havoc ~__retres1~5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L364] COND TRUE 1 == ~t5_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L365] COND TRUE 1 == ~E_5~0 [L366] ~__retres1~5 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L376] #res := ~__retres1~5; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2] [L748] RET call #t~ret12 := is_transmit5_triggered(); VAL [#t~ret12=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L748] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647; [L748] ~tmp___4~0 := #t~ret12; [L748] havoc #t~ret12; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp___4~0=1, ~tmp~1=0] [L750-L754] COND TRUE 0 != ~tmp___4~0 [L751] ~t5_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp___4~0=1, ~tmp~1=0] [L764] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0] [L221] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0] [L222] ~E_5~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0] [L212-L224] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0] [L214] ~t4_pc~0 := 1; [L215] ~t4_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0] [L543] RET call transmit4(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L551] COND TRUE 0 == ~t5_st~0 [L552] havoc ~tmp_ndt_6~0; [L553] assume -2147483648 <= #t~nondet6 && #t~nondet6 <= 2147483647; [L553] ~tmp_ndt_6~0 := #t~nondet6; [L553] havoc #t~nondet6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L554-L561] COND TRUE 0 != ~tmp_ndt_6~0 [L556] ~t5_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp~0=1] [L557] CALL call transmit5(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1] [L236] COND FALSE !(0 == ~t5_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1] [L239] COND TRUE 1 == ~t5_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1] [L255] CALL call error(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1] [L11] assert false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1] [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int m_i ; [L28] int t1_i ; [L29] int t2_i ; [L30] int t3_i ; [L31] int t4_i ; [L32] int t5_i ; [L33] int M_E = 2; [L34] int T1_E = 2; [L35] int T2_E = 2; [L36] int T3_E = 2; [L37] int T4_E = 2; [L38] int T5_E = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; VAL [\old(E_1)=29, \old(E_2)=21, \old(E_3)=20, \old(E_4)=8, \old(E_5)=4, \old(M_E)=13, \old(m_i)=7, \old(m_pc)=25, \old(m_st)=12, \old(T1_E)=3, \old(t1_i)=26, \old(t1_pc)=24, \old(t1_st)=5, \old(T2_E)=27, \old(t2_i)=6, \old(t2_pc)=23, \old(t2_st)=10, \old(T3_E)=19, \old(t3_i)=30, \old(t3_pc)=22, \old(t3_st)=11, \old(T4_E)=31, \old(t4_i)=14, \old(t4_pc)=18, \old(t4_st)=9, \old(T5_E)=17, \old(t5_i)=28, \old(t5_pc)=15, \old(t5_st)=16, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0] [L935] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0] [L939] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0] [L846] m_i = 1 [L847] t1_i = 1 [L848] t2_i = 1 [L849] t3_i = 1 [L850] t4_i = 1 [L851] t5_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L939] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L940] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L876] int kernel_st ; [L877] int tmp ; [L878] int tmp___0 ; [L882] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L883] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L884] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L391] COND TRUE m_i == 1 [L392] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L396] COND TRUE t1_i == 1 [L397] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L401] COND TRUE t2_i == 1 [L402] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L406] COND TRUE t3_i == 1 [L407] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L411] COND TRUE t4_i == 1 [L412] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L416] COND TRUE t5_i == 1 [L417] t5_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L884] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L885] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L576] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L581] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L586] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L591] COND FALSE !(T3_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L596] COND FALSE !(T4_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L601] COND FALSE !(T5_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L606] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L611] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L616] COND FALSE !(E_3 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L621] COND FALSE !(E_4 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L626] COND FALSE !(E_5 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L885] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L886] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L269] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L288] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L298] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L307] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L317] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L326] COND FALSE !(t3_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L336] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L345] COND FALSE !(t4_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L355] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L364] COND FALSE !(t5_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L374] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L886] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L887] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L639] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L644] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L649] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L654] COND FALSE !(T3_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L659] COND FALSE !(T4_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L664] COND FALSE !(T5_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L669] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L674] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L679] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L684] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L689] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L887] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L890] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L893] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L894] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L467] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L471] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L474] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L426] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L429] COND TRUE m_st == 0 [L430] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L462] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L474] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L474] tmp = exists_runnable_thread() [L476] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1] [L481] COND TRUE m_st == 0 [L482] int tmp_ndt_1; [L483] tmp_ndt_1 = __VERIFIER_nondet_int() [L484] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0] [L495] COND TRUE t1_st == 0 [L496] int tmp_ndt_2; [L497] tmp_ndt_2 = __VERIFIER_nondet_int() [L498] COND TRUE \read(tmp_ndt_2) [L500] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L501] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L96] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L107] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L109] t1_pc = 1 [L110] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L501] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L509] COND TRUE t2_st == 0 [L510] int tmp_ndt_3; [L511] tmp_ndt_3 = __VERIFIER_nondet_int() [L512] COND TRUE \read(tmp_ndt_3) [L514] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L515] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L131] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L142] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L144] t2_pc = 1 [L145] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L515] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L523] COND TRUE t3_st == 0 [L524] int tmp_ndt_4; [L525] tmp_ndt_4 = __VERIFIER_nondet_int() [L526] COND TRUE \read(tmp_ndt_4) [L528] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L529] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L166] COND TRUE t3_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L177] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L179] t3_pc = 1 [L180] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L529] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L537] COND TRUE t4_st == 0 [L538] int tmp_ndt_5; [L539] tmp_ndt_5 = __VERIFIER_nondet_int() [L540] COND TRUE \read(tmp_ndt_5) [L542] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L543] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L201] COND TRUE t4_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L212] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L214] t4_pc = 1 [L215] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L543] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L551] COND TRUE t5_st == 0 [L552] int tmp_ndt_6; [L553] tmp_ndt_6 = __VERIFIER_nondet_int() [L554] COND TRUE \read(tmp_ndt_6) [L556] t5_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L557] CALL transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1] [L236] COND TRUE t5_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1] [L247] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1] [L249] t5_pc = 1 [L250] t5_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L557] RET transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L471] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L474] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L426] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L429] COND TRUE m_st == 0 [L430] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L462] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L474] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L474] tmp = exists_runnable_thread() [L476] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L481] COND TRUE m_st == 0 [L482] int tmp_ndt_1; [L483] tmp_ndt_1 = __VERIFIER_nondet_int() [L484] COND TRUE \read(tmp_ndt_1) [L486] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L487] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L55] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L66] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L69] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L70] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L764] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND TRUE E_1 == 1 [L290] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND TRUE \read(tmp___0) [L719] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L317] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L336] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L355] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L374] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L764] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L70] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L71] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L74] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L76] m_pc = 1 [L77] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L487] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L495] COND TRUE t1_st == 0 [L496] int tmp_ndt_2; [L497] tmp_ndt_2 = __VERIFIER_nondet_int() [L498] COND TRUE \read(tmp_ndt_2) [L500] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L501] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L96] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L99] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L115] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L116] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L764] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L270] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L298] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND TRUE E_2 == 1 [L309] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] tmp___1 = is_transmit2_triggered() [L726] COND TRUE \read(tmp___1) [L727] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L336] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L355] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L374] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0, tmp___4=0] [L764] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L116] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L117] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L107] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L109] t1_pc = 1 [L110] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L501] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L509] COND TRUE t2_st == 0 [L510] int tmp_ndt_3; [L511] tmp_ndt_3 = __VERIFIER_nondet_int() [L512] COND TRUE \read(tmp_ndt_3) [L514] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L515] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L131] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L134] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L150] E_3 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L151] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L764] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L270] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L298] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L317] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND TRUE E_3 == 1 [L328] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_transmit3_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] tmp___2 = is_transmit3_triggered() [L734] COND TRUE \read(tmp___2) [L735] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L355] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L374] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0, tmp___4=0] [L764] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L151] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L152] E_3 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L142] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L144] t2_pc = 1 [L145] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L515] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L523] COND TRUE t3_st == 0 [L524] int tmp_ndt_4; [L525] tmp_ndt_4 = __VERIFIER_nondet_int() [L526] COND TRUE \read(tmp_ndt_4) [L528] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L529] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L166] COND FALSE !(t3_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L169] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L185] E_4 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L186] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L764] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L270] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L298] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L317] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L336] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND TRUE E_4 == 1 [L347] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_transmit4_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] tmp___3 = is_transmit4_triggered() [L742] COND TRUE \read(tmp___3) [L743] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L374] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1, tmp___4=0] [L764] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L186] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L187] E_4 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L177] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L179] t3_pc = 1 [L180] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L529] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L537] COND TRUE t4_st == 0 [L538] int tmp_ndt_5; [L539] tmp_ndt_5 = __VERIFIER_nondet_int() [L540] COND TRUE \read(tmp_ndt_5) [L542] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L543] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L201] COND FALSE !(t4_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L204] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L220] E_5 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L221] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L764] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L270] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L298] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L317] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L336] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L355] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND TRUE E_5 == 1 [L366] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_transmit5_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L748] tmp___4 = is_transmit5_triggered() [L750] COND TRUE \read(tmp___4) [L751] t5_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=1] [L764] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L221] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L222] E_5 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L212] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L214] t4_pc = 1 [L215] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L543] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L551] COND TRUE t5_st == 0 [L552] int tmp_ndt_6; [L553] tmp_ndt_6 = __VERIFIER_nondet_int() [L554] COND TRUE \read(tmp_ndt_6) [L556] t5_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L557] CALL transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] [L236] COND FALSE !(t5_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] [L239] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] [L255] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] ----- [2018-11-23 16:12:55,917 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_4b3cb404-9a2f-4442-8e45-c96afebce76c/bin-2019/uautomizer/witness.graphml [2018-11-23 16:12:55,918 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 16:12:55,918 INFO L168 Benchmark]: Toolchain (without parser) took 201858.72 ms. Allocated memory was 1.0 GB in the beginning and 6.2 GB in the end (delta: 5.2 GB). Free memory was 959.1 MB in the beginning and 3.1 GB in the end (delta: -2.2 GB). Peak memory consumption was 3.0 GB. Max. memory is 11.5 GB. [2018-11-23 16:12:55,919 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 16:12:55,920 INFO L168 Benchmark]: CACSL2BoogieTranslator took 256.88 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 940.1 MB in the end (delta: 19.0 MB). Peak memory consumption was 19.0 MB. Max. memory is 11.5 GB. [2018-11-23 16:12:55,920 INFO L168 Benchmark]: Boogie Procedure Inliner took 55.66 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 168.3 MB). Free memory was 940.1 MB in the beginning and 1.2 GB in the end (delta: -223.4 MB). Peak memory consumption was 17.5 MB. Max. memory is 11.5 GB. [2018-11-23 16:12:55,920 INFO L168 Benchmark]: Boogie Preprocessor took 39.60 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 3.2 MB). Peak memory consumption was 3.2 MB. Max. memory is 11.5 GB. [2018-11-23 16:12:55,926 INFO L168 Benchmark]: RCFGBuilder took 522.69 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 65.1 MB). Peak memory consumption was 65.1 MB. Max. memory is 11.5 GB. [2018-11-23 16:12:55,926 INFO L168 Benchmark]: TraceAbstraction took 118786.14 ms. Allocated memory was 1.2 GB in the beginning and 6.2 GB in the end (delta: 5.0 GB). Free memory was 1.1 GB in the beginning and 3.8 GB in the end (delta: -2.7 GB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. [2018-11-23 16:12:55,927 INFO L168 Benchmark]: Witness Printer took 82194.38 ms. Allocated memory is still 6.2 GB. Free memory was 3.8 GB in the beginning and 3.1 GB in the end (delta: 699.5 MB). Peak memory consumption was 699.5 MB. Max. memory is 11.5 GB. [2018-11-23 16:12:55,928 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 256.88 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 940.1 MB in the end (delta: 19.0 MB). Peak memory consumption was 19.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 55.66 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 168.3 MB). Free memory was 940.1 MB in the beginning and 1.2 GB in the end (delta: -223.4 MB). Peak memory consumption was 17.5 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 39.60 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 3.2 MB). Peak memory consumption was 3.2 MB. Max. memory is 11.5 GB. * RCFGBuilder took 522.69 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 65.1 MB). Peak memory consumption was 65.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 118786.14 ms. Allocated memory was 1.2 GB in the beginning and 6.2 GB in the end (delta: 5.0 GB). Free memory was 1.1 GB in the beginning and 3.8 GB in the end (delta: -2.7 GB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. * Witness Printer took 82194.38 ms. Allocated memory is still 6.2 GB. Free memory was 3.8 GB in the beginning and 3.1 GB in the end (delta: 699.5 MB). Peak memory consumption was 699.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int m_i ; [L28] int t1_i ; [L29] int t2_i ; [L30] int t3_i ; [L31] int t4_i ; [L32] int t5_i ; [L33] int M_E = 2; [L34] int T1_E = 2; [L35] int T2_E = 2; [L36] int T3_E = 2; [L37] int T4_E = 2; [L38] int T5_E = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; VAL [\old(E_1)=29, \old(E_2)=21, \old(E_3)=20, \old(E_4)=8, \old(E_5)=4, \old(M_E)=13, \old(m_i)=7, \old(m_pc)=25, \old(m_st)=12, \old(T1_E)=3, \old(t1_i)=26, \old(t1_pc)=24, \old(t1_st)=5, \old(T2_E)=27, \old(t2_i)=6, \old(t2_pc)=23, \old(t2_st)=10, \old(T3_E)=19, \old(t3_i)=30, \old(t3_pc)=22, \old(t3_st)=11, \old(T4_E)=31, \old(t4_i)=14, \old(t4_pc)=18, \old(t4_st)=9, \old(T5_E)=17, \old(t5_i)=28, \old(t5_pc)=15, \old(t5_st)=16, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0] [L935] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0] [L939] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0] [L846] m_i = 1 [L847] t1_i = 1 [L848] t2_i = 1 [L849] t3_i = 1 [L850] t4_i = 1 [L851] t5_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L939] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L940] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L876] int kernel_st ; [L877] int tmp ; [L878] int tmp___0 ; [L882] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L883] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L884] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L391] COND TRUE m_i == 1 [L392] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L396] COND TRUE t1_i == 1 [L397] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L401] COND TRUE t2_i == 1 [L402] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L406] COND TRUE t3_i == 1 [L407] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L411] COND TRUE t4_i == 1 [L412] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L416] COND TRUE t5_i == 1 [L417] t5_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L884] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L885] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L576] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L581] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L586] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L591] COND FALSE !(T3_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L596] COND FALSE !(T4_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L601] COND FALSE !(T5_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L606] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L611] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L616] COND FALSE !(E_3 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L621] COND FALSE !(E_4 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L626] COND FALSE !(E_5 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L885] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L886] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L269] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L288] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L298] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L307] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L317] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L326] COND FALSE !(t3_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L336] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L345] COND FALSE !(t4_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L355] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L364] COND FALSE !(t5_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L374] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L886] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L887] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L639] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L644] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L649] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L654] COND FALSE !(T3_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L659] COND FALSE !(T4_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L664] COND FALSE !(T5_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L669] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L674] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L679] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L684] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L689] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L887] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L890] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L893] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L894] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L467] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L471] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L474] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L426] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L429] COND TRUE m_st == 0 [L430] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L462] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L474] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L474] tmp = exists_runnable_thread() [L476] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1] [L481] COND TRUE m_st == 0 [L482] int tmp_ndt_1; [L483] tmp_ndt_1 = __VERIFIER_nondet_int() [L484] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0] [L495] COND TRUE t1_st == 0 [L496] int tmp_ndt_2; [L497] tmp_ndt_2 = __VERIFIER_nondet_int() [L498] COND TRUE \read(tmp_ndt_2) [L500] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L501] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L96] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L107] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L109] t1_pc = 1 [L110] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L501] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L509] COND TRUE t2_st == 0 [L510] int tmp_ndt_3; [L511] tmp_ndt_3 = __VERIFIER_nondet_int() [L512] COND TRUE \read(tmp_ndt_3) [L514] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L515] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L131] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L142] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L144] t2_pc = 1 [L145] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L515] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L523] COND TRUE t3_st == 0 [L524] int tmp_ndt_4; [L525] tmp_ndt_4 = __VERIFIER_nondet_int() [L526] COND TRUE \read(tmp_ndt_4) [L528] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L529] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L166] COND TRUE t3_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L177] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L179] t3_pc = 1 [L180] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L529] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L537] COND TRUE t4_st == 0 [L538] int tmp_ndt_5; [L539] tmp_ndt_5 = __VERIFIER_nondet_int() [L540] COND TRUE \read(tmp_ndt_5) [L542] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L543] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L201] COND TRUE t4_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L212] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L214] t4_pc = 1 [L215] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L543] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L551] COND TRUE t5_st == 0 [L552] int tmp_ndt_6; [L553] tmp_ndt_6 = __VERIFIER_nondet_int() [L554] COND TRUE \read(tmp_ndt_6) [L556] t5_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L557] CALL transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1] [L236] COND TRUE t5_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1] [L247] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1] [L249] t5_pc = 1 [L250] t5_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L557] RET transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L471] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L474] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L426] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L429] COND TRUE m_st == 0 [L430] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L462] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L474] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L474] tmp = exists_runnable_thread() [L476] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L481] COND TRUE m_st == 0 [L482] int tmp_ndt_1; [L483] tmp_ndt_1 = __VERIFIER_nondet_int() [L484] COND TRUE \read(tmp_ndt_1) [L486] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L487] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L55] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L66] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L69] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L70] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L764] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND TRUE E_1 == 1 [L290] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND TRUE \read(tmp___0) [L719] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L317] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L336] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L355] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L374] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L764] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L70] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L71] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L74] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L76] m_pc = 1 [L77] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L487] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L495] COND TRUE t1_st == 0 [L496] int tmp_ndt_2; [L497] tmp_ndt_2 = __VERIFIER_nondet_int() [L498] COND TRUE \read(tmp_ndt_2) [L500] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L501] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L96] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L99] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L115] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L116] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L764] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L270] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L298] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND TRUE E_2 == 1 [L309] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] tmp___1 = is_transmit2_triggered() [L726] COND TRUE \read(tmp___1) [L727] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L336] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L355] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L374] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0, tmp___4=0] [L764] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L116] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L117] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L107] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L109] t1_pc = 1 [L110] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L501] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L509] COND TRUE t2_st == 0 [L510] int tmp_ndt_3; [L511] tmp_ndt_3 = __VERIFIER_nondet_int() [L512] COND TRUE \read(tmp_ndt_3) [L514] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L515] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L131] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L134] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L150] E_3 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L151] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L764] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L270] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L298] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L317] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND TRUE E_3 == 1 [L328] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_transmit3_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] tmp___2 = is_transmit3_triggered() [L734] COND TRUE \read(tmp___2) [L735] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L355] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L374] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0, tmp___4=0] [L764] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L151] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L152] E_3 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L142] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L144] t2_pc = 1 [L145] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L515] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L523] COND TRUE t3_st == 0 [L524] int tmp_ndt_4; [L525] tmp_ndt_4 = __VERIFIER_nondet_int() [L526] COND TRUE \read(tmp_ndt_4) [L528] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L529] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L166] COND FALSE !(t3_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L169] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L185] E_4 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L186] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L764] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L270] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L298] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L317] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L336] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND TRUE E_4 == 1 [L347] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_transmit4_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] tmp___3 = is_transmit4_triggered() [L742] COND TRUE \read(tmp___3) [L743] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L374] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1, tmp___4=0] [L764] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L186] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L187] E_4 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L177] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L179] t3_pc = 1 [L180] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L529] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L537] COND TRUE t4_st == 0 [L538] int tmp_ndt_5; [L539] tmp_ndt_5 = __VERIFIER_nondet_int() [L540] COND TRUE \read(tmp_ndt_5) [L542] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L543] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L201] COND FALSE !(t4_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L204] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L220] E_5 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L221] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L764] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L270] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L298] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L317] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L336] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L355] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND TRUE E_5 == 1 [L366] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_transmit5_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L748] tmp___4 = is_transmit5_triggered() [L750] COND TRUE \read(tmp___4) [L751] t5_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=1] [L764] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L221] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L222] E_5 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L212] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L214] t4_pc = 1 [L215] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L543] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L551] COND TRUE t5_st == 0 [L552] int tmp_ndt_6; [L553] tmp_ndt_6 = __VERIFIER_nondet_int() [L554] COND TRUE \read(tmp_ndt_6) [L556] t5_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L557] CALL transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] [L236] COND FALSE !(t5_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] [L239] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] [L255] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 29 procedures, 259 locations, 1 error locations. UNSAFE Result, 118.7s OverallTime, 42 OverallIterations, 6 TraceHistogramMax, 48.9s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 16511 SDtfs, 19730 SDslu, 19217 SDs, 0 SdLazy, 11665 SolverSat, 4425 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 9.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2571 GetRequests, 2334 SyntacticMatches, 61 SemanticMatches, 176 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 59 ImplicationChecksByTransitivity, 1.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=86246occurred in iteration=40, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 34.8s AutomataMinimizationTime, 41 MinimizatonAttempts, 7540 StatesRemovedByMinimization, 35 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.3s SsaConstructionTime, 0.8s SatisfiabilityAnalysisTime, 2.5s InterpolantComputationTime, 9852 NumberOfCodeBlocks, 9852 NumberOfCodeBlocksAsserted, 48 NumberOfCheckSat, 9240 ConstructedInterpolants, 0 QuantifiedInterpolants, 3004680 SizeOfPredicates, 5 NumberOfNonLiveVariables, 9743 ConjunctsInSsa, 30 ConjunctsInUnsatCore, 47 InterpolantComputations, 41 PerfectInterpolantSequences, 4076/4179 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...