./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.06_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.06_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 7b5159bbdd5292a1bc0941c897062f30a665bf67 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 00:56:07,013 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 00:56:07,014 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 00:56:07,023 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 00:56:07,023 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 00:56:07,023 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 00:56:07,024 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 00:56:07,026 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 00:56:07,027 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 00:56:07,029 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 00:56:07,030 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 00:56:07,030 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 00:56:07,031 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 00:56:07,031 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 00:56:07,032 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 00:56:07,033 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 00:56:07,034 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 00:56:07,035 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 00:56:07,036 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 00:56:07,037 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 00:56:07,038 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 00:56:07,039 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 00:56:07,041 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 00:56:07,041 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 00:56:07,041 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 00:56:07,042 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 00:56:07,043 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 00:56:07,043 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 00:56:07,044 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 00:56:07,044 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 00:56:07,045 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 00:56:07,045 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 00:56:07,045 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 00:56:07,045 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 00:56:07,046 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 00:56:07,047 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 00:56:07,047 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-23 00:56:07,057 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 00:56:07,057 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 00:56:07,058 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 00:56:07,058 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 00:56:07,059 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 00:56:07,059 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 00:56:07,059 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 00:56:07,059 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 00:56:07,059 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 00:56:07,059 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 00:56:07,059 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 00:56:07,060 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 00:56:07,060 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 00:56:07,060 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 00:56:07,060 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 00:56:07,060 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 00:56:07,060 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 00:56:07,060 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 00:56:07,061 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 00:56:07,061 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 00:56:07,061 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 00:56:07,061 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 00:56:07,061 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 00:56:07,061 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 00:56:07,062 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 00:56:07,062 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 00:56:07,062 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 00:56:07,062 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 00:56:07,062 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 00:56:07,062 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 00:56:07,062 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 7b5159bbdd5292a1bc0941c897062f30a665bf67 [2018-11-23 00:56:07,082 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 00:56:07,090 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 00:56:07,093 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 00:56:07,094 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 00:56:07,094 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 00:56:07,095 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.06_false-unreach-call_false-termination.cil.c [2018-11-23 00:56:07,130 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/data/baf76657f/a84abefd5639436a878e8ae02c9fc9c6/FLAG83dfb37a7 [2018-11-23 00:56:07,463 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 00:56:07,464 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/sv-benchmarks/c/systemc/transmitter.06_false-unreach-call_false-termination.cil.c [2018-11-23 00:56:07,471 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/data/baf76657f/a84abefd5639436a878e8ae02c9fc9c6/FLAG83dfb37a7 [2018-11-23 00:56:07,482 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/data/baf76657f/a84abefd5639436a878e8ae02c9fc9c6 [2018-11-23 00:56:07,484 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 00:56:07,486 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 00:56:07,486 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 00:56:07,486 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 00:56:07,489 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 00:56:07,489 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 12:56:07" (1/1) ... [2018-11-23 00:56:07,491 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@51ac0340 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:56:07, skipping insertion in model container [2018-11-23 00:56:07,491 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 12:56:07" (1/1) ... [2018-11-23 00:56:07,497 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 00:56:07,525 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 00:56:07,676 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 00:56:07,680 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 00:56:07,712 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 00:56:07,725 INFO L195 MainTranslator]: Completed translation [2018-11-23 00:56:07,725 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:56:07 WrapperNode [2018-11-23 00:56:07,725 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 00:56:07,725 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 00:56:07,726 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 00:56:07,726 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 00:56:07,775 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:56:07" (1/1) ... [2018-11-23 00:56:07,783 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:56:07" (1/1) ... [2018-11-23 00:56:07,791 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 00:56:07,791 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 00:56:07,791 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 00:56:07,791 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 00:56:07,800 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:56:07" (1/1) ... [2018-11-23 00:56:07,800 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:56:07" (1/1) ... [2018-11-23 00:56:07,803 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:56:07" (1/1) ... [2018-11-23 00:56:07,803 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:56:07" (1/1) ... [2018-11-23 00:56:07,814 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:56:07" (1/1) ... [2018-11-23 00:56:07,826 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:56:07" (1/1) ... [2018-11-23 00:56:07,829 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:56:07" (1/1) ... [2018-11-23 00:56:07,832 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 00:56:07,832 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 00:56:07,832 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 00:56:07,832 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 00:56:07,833 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:56:07" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 00:56:07,878 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2018-11-23 00:56:07,878 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2018-11-23 00:56:07,878 INFO L130 BoogieDeclarations]: Found specification of procedure transmit3 [2018-11-23 00:56:07,878 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit3 [2018-11-23 00:56:07,878 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2018-11-23 00:56:07,878 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2018-11-23 00:56:07,878 INFO L130 BoogieDeclarations]: Found specification of procedure transmit5 [2018-11-23 00:56:07,878 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit5 [2018-11-23 00:56:07,879 INFO L130 BoogieDeclarations]: Found specification of procedure transmit4 [2018-11-23 00:56:07,879 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit4 [2018-11-23 00:56:07,879 INFO L130 BoogieDeclarations]: Found specification of procedure transmit6 [2018-11-23 00:56:07,879 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit6 [2018-11-23 00:56:07,879 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 00:56:07,879 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 00:56:07,879 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-11-23 00:56:07,880 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-11-23 00:56:07,880 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-11-23 00:56:07,880 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-11-23 00:56:07,880 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2018-11-23 00:56:07,880 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2018-11-23 00:56:07,880 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-11-23 00:56:07,880 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-11-23 00:56:07,880 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2018-11-23 00:56:07,881 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2018-11-23 00:56:07,881 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-11-23 00:56:07,881 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-11-23 00:56:07,881 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit4_triggered [2018-11-23 00:56:07,881 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit4_triggered [2018-11-23 00:56:07,881 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-11-23 00:56:07,881 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-11-23 00:56:07,881 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-11-23 00:56:07,881 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-11-23 00:56:07,882 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-11-23 00:56:07,882 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-11-23 00:56:07,882 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-11-23 00:56:07,882 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-11-23 00:56:07,882 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2018-11-23 00:56:07,882 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2018-11-23 00:56:07,882 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-11-23 00:56:07,882 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-11-23 00:56:07,882 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit6_triggered [2018-11-23 00:56:07,883 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit6_triggered [2018-11-23 00:56:07,883 INFO L130 BoogieDeclarations]: Found specification of procedure master [2018-11-23 00:56:07,883 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2018-11-23 00:56:07,883 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-11-23 00:56:07,883 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-11-23 00:56:07,883 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 00:56:07,883 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 00:56:07,883 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-11-23 00:56:07,884 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-11-23 00:56:07,884 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit3_triggered [2018-11-23 00:56:07,884 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit3_triggered [2018-11-23 00:56:07,884 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit5_triggered [2018-11-23 00:56:07,884 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit5_triggered [2018-11-23 00:56:07,884 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-11-23 00:56:07,884 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-11-23 00:56:07,884 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-11-23 00:56:07,884 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-11-23 00:56:07,885 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 00:56:07,885 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 00:56:07,885 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-11-23 00:56:07,885 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-11-23 00:56:08,469 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 00:56:08,469 INFO L280 CfgBuilder]: Removed 10 assue(true) statements. [2018-11-23 00:56:08,470 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 12:56:08 BoogieIcfgContainer [2018-11-23 00:56:08,470 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 00:56:08,470 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 00:56:08,470 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 00:56:08,473 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 00:56:08,473 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 12:56:07" (1/3) ... [2018-11-23 00:56:08,474 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5374f24c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 12:56:08, skipping insertion in model container [2018-11-23 00:56:08,474 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:56:07" (2/3) ... [2018-11-23 00:56:08,475 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5374f24c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 12:56:08, skipping insertion in model container [2018-11-23 00:56:08,475 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 12:56:08" (3/3) ... [2018-11-23 00:56:08,476 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.06_false-unreach-call_false-termination.cil.c [2018-11-23 00:56:08,485 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 00:56:08,492 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 00:56:08,506 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 00:56:08,535 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 00:56:08,536 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 00:56:08,536 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 00:56:08,536 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 00:56:08,536 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 00:56:08,536 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 00:56:08,536 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 00:56:08,537 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 00:56:08,537 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 00:56:08,559 INFO L276 IsEmpty]: Start isEmpty. Operand 289 states. [2018-11-23 00:56:08,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:08,571 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:08,571 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:08,573 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:08,578 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:08,578 INFO L82 PathProgramCache]: Analyzing trace with hash 1949535280, now seen corresponding path program 1 times [2018-11-23 00:56:08,580 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:08,580 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:08,622 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:08,622 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:08,622 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:08,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:08,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:08,854 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:08,855 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 00:56:08,859 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 00:56:08,870 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 00:56:08,870 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 00:56:08,873 INFO L87 Difference]: Start difference. First operand 289 states. Second operand 4 states. [2018-11-23 00:56:09,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:09,138 INFO L93 Difference]: Finished difference Result 556 states and 834 transitions. [2018-11-23 00:56:09,138 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 00:56:09,139 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 150 [2018-11-23 00:56:09,140 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:09,150 INFO L225 Difference]: With dead ends: 556 [2018-11-23 00:56:09,150 INFO L226 Difference]: Without dead ends: 280 [2018-11-23 00:56:09,154 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 00:56:09,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 280 states. [2018-11-23 00:56:09,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 280 to 280. [2018-11-23 00:56:09,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-11-23 00:56:09,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 396 transitions. [2018-11-23 00:56:09,217 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 396 transitions. Word has length 150 [2018-11-23 00:56:09,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:09,219 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 396 transitions. [2018-11-23 00:56:09,219 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 00:56:09,219 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 396 transitions. [2018-11-23 00:56:09,223 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:09,223 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:09,223 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:09,224 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:09,224 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:09,224 INFO L82 PathProgramCache]: Analyzing trace with hash -1397380050, now seen corresponding path program 1 times [2018-11-23 00:56:09,224 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:09,225 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:09,226 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:09,226 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:09,226 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:09,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:09,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:09,390 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:09,390 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:09,392 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:09,392 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:09,392 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:09,392 INFO L87 Difference]: Start difference. First operand 280 states and 396 transitions. Second operand 5 states. [2018-11-23 00:56:09,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:09,884 INFO L93 Difference]: Finished difference Result 580 states and 842 transitions. [2018-11-23 00:56:09,885 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 00:56:09,885 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:09,885 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:09,888 INFO L225 Difference]: With dead ends: 580 [2018-11-23 00:56:09,888 INFO L226 Difference]: Without dead ends: 324 [2018-11-23 00:56:09,890 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:09,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 324 states. [2018-11-23 00:56:09,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 324 to 280. [2018-11-23 00:56:09,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-11-23 00:56:09,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 395 transitions. [2018-11-23 00:56:09,920 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 395 transitions. Word has length 150 [2018-11-23 00:56:09,920 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:09,921 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 395 transitions. [2018-11-23 00:56:09,921 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:09,921 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 395 transitions. [2018-11-23 00:56:09,923 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:09,923 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:09,924 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:09,927 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:09,927 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:09,927 INFO L82 PathProgramCache]: Analyzing trace with hash -450342164, now seen corresponding path program 1 times [2018-11-23 00:56:09,927 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:09,927 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:09,928 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:09,928 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:09,929 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:09,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:10,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:10,050 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:10,050 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:10,050 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:10,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:10,051 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:10,051 INFO L87 Difference]: Start difference. First operand 280 states and 395 transitions. Second operand 5 states. [2018-11-23 00:56:10,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:10,440 INFO L93 Difference]: Finished difference Result 580 states and 841 transitions. [2018-11-23 00:56:10,440 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 00:56:10,440 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:10,441 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:10,442 INFO L225 Difference]: With dead ends: 580 [2018-11-23 00:56:10,442 INFO L226 Difference]: Without dead ends: 324 [2018-11-23 00:56:10,443 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:10,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 324 states. [2018-11-23 00:56:10,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 324 to 280. [2018-11-23 00:56:10,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-11-23 00:56:10,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 394 transitions. [2018-11-23 00:56:10,461 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 394 transitions. Word has length 150 [2018-11-23 00:56:10,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:10,461 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 394 transitions. [2018-11-23 00:56:10,461 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:10,462 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 394 transitions. [2018-11-23 00:56:10,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:10,463 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:10,464 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:10,464 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:10,464 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:10,464 INFO L82 PathProgramCache]: Analyzing trace with hash 411491438, now seen corresponding path program 1 times [2018-11-23 00:56:10,464 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:10,464 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:10,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:10,465 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:10,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:10,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:10,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:10,552 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:10,552 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:10,553 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:10,553 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:10,553 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:10,553 INFO L87 Difference]: Start difference. First operand 280 states and 394 transitions. Second operand 5 states. [2018-11-23 00:56:11,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:11,036 INFO L93 Difference]: Finished difference Result 578 states and 835 transitions. [2018-11-23 00:56:11,036 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 00:56:11,036 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:11,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:11,039 INFO L225 Difference]: With dead ends: 578 [2018-11-23 00:56:11,039 INFO L226 Difference]: Without dead ends: 322 [2018-11-23 00:56:11,040 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:11,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states. [2018-11-23 00:56:11,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 280. [2018-11-23 00:56:11,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-11-23 00:56:11,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 393 transitions. [2018-11-23 00:56:11,062 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 393 transitions. Word has length 150 [2018-11-23 00:56:11,062 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:11,062 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 393 transitions. [2018-11-23 00:56:11,062 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:11,063 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 393 transitions. [2018-11-23 00:56:11,064 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:11,064 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:11,064 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:11,065 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:11,065 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:11,065 INFO L82 PathProgramCache]: Analyzing trace with hash -1638917460, now seen corresponding path program 1 times [2018-11-23 00:56:11,066 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:11,066 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:11,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:11,067 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:11,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:11,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:11,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:11,147 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:11,147 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:11,147 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:11,147 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:11,148 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:11,149 INFO L87 Difference]: Start difference. First operand 280 states and 393 transitions. Second operand 5 states. [2018-11-23 00:56:11,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:11,538 INFO L93 Difference]: Finished difference Result 576 states and 829 transitions. [2018-11-23 00:56:11,538 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 00:56:11,539 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:11,539 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:11,540 INFO L225 Difference]: With dead ends: 576 [2018-11-23 00:56:11,540 INFO L226 Difference]: Without dead ends: 320 [2018-11-23 00:56:11,541 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:11,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 320 states. [2018-11-23 00:56:11,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 320 to 280. [2018-11-23 00:56:11,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-11-23 00:56:11,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 392 transitions. [2018-11-23 00:56:11,557 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 392 transitions. Word has length 150 [2018-11-23 00:56:11,557 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:11,557 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 392 transitions. [2018-11-23 00:56:11,558 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:11,558 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 392 transitions. [2018-11-23 00:56:11,559 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:11,559 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:11,560 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:11,560 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:11,560 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:11,560 INFO L82 PathProgramCache]: Analyzing trace with hash -1150870354, now seen corresponding path program 1 times [2018-11-23 00:56:11,560 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:11,561 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:11,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:11,561 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:11,562 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:11,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:11,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:11,628 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:11,628 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:11,628 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:11,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:11,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:11,629 INFO L87 Difference]: Start difference. First operand 280 states and 392 transitions. Second operand 5 states. [2018-11-23 00:56:12,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:12,066 INFO L93 Difference]: Finished difference Result 574 states and 823 transitions. [2018-11-23 00:56:12,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 00:56:12,067 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:12,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:12,068 INFO L225 Difference]: With dead ends: 574 [2018-11-23 00:56:12,069 INFO L226 Difference]: Without dead ends: 318 [2018-11-23 00:56:12,070 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:12,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 318 states. [2018-11-23 00:56:12,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 318 to 280. [2018-11-23 00:56:12,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-11-23 00:56:12,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 391 transitions. [2018-11-23 00:56:12,091 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 391 transitions. Word has length 150 [2018-11-23 00:56:12,091 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:12,091 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 391 transitions. [2018-11-23 00:56:12,091 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:12,091 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 391 transitions. [2018-11-23 00:56:12,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:12,093 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:12,093 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:12,093 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:12,093 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:12,093 INFO L82 PathProgramCache]: Analyzing trace with hash 2051461740, now seen corresponding path program 1 times [2018-11-23 00:56:12,093 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:12,093 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:12,094 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:12,094 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:12,094 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:12,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:12,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:12,158 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:12,158 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:12,158 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:12,158 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:12,159 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:12,159 INFO L87 Difference]: Start difference. First operand 280 states and 391 transitions. Second operand 5 states. [2018-11-23 00:56:12,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:12,591 INFO L93 Difference]: Finished difference Result 570 states and 813 transitions. [2018-11-23 00:56:12,592 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 00:56:12,592 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:12,592 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:12,593 INFO L225 Difference]: With dead ends: 570 [2018-11-23 00:56:12,593 INFO L226 Difference]: Without dead ends: 314 [2018-11-23 00:56:12,594 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:12,595 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 314 states. [2018-11-23 00:56:12,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 314 to 280. [2018-11-23 00:56:12,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-11-23 00:56:12,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 390 transitions. [2018-11-23 00:56:12,608 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 390 transitions. Word has length 150 [2018-11-23 00:56:12,608 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:12,608 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 390 transitions. [2018-11-23 00:56:12,608 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:12,609 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 390 transitions. [2018-11-23 00:56:12,610 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:12,610 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:12,610 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:12,610 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:12,611 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:12,611 INFO L82 PathProgramCache]: Analyzing trace with hash 208986026, now seen corresponding path program 1 times [2018-11-23 00:56:12,611 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:12,611 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:12,611 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:12,612 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:12,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:12,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:12,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:12,660 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:12,660 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:12,661 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:12,661 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:12,661 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:12,661 INFO L87 Difference]: Start difference. First operand 280 states and 390 transitions. Second operand 5 states. [2018-11-23 00:56:13,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:13,111 INFO L93 Difference]: Finished difference Result 599 states and 863 transitions. [2018-11-23 00:56:13,111 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 00:56:13,111 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:13,112 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:13,113 INFO L225 Difference]: With dead ends: 599 [2018-11-23 00:56:13,114 INFO L226 Difference]: Without dead ends: 343 [2018-11-23 00:56:13,115 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:13,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 343 states. [2018-11-23 00:56:13,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 343 to 280. [2018-11-23 00:56:13,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-11-23 00:56:13,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 389 transitions. [2018-11-23 00:56:13,141 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 389 transitions. Word has length 150 [2018-11-23 00:56:13,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:13,141 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 389 transitions. [2018-11-23 00:56:13,141 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:13,141 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 389 transitions. [2018-11-23 00:56:13,143 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:13,143 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:13,143 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:13,143 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:13,144 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:13,144 INFO L82 PathProgramCache]: Analyzing trace with hash -1513016660, now seen corresponding path program 1 times [2018-11-23 00:56:13,144 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:13,144 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:13,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:13,145 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:13,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:13,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:13,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:13,216 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:13,217 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:13,217 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:13,217 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:13,217 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:13,217 INFO L87 Difference]: Start difference. First operand 280 states and 389 transitions. Second operand 5 states. [2018-11-23 00:56:13,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:13,648 INFO L93 Difference]: Finished difference Result 597 states and 857 transitions. [2018-11-23 00:56:13,650 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 00:56:13,651 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:13,651 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:13,653 INFO L225 Difference]: With dead ends: 597 [2018-11-23 00:56:13,653 INFO L226 Difference]: Without dead ends: 341 [2018-11-23 00:56:13,654 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:13,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 341 states. [2018-11-23 00:56:13,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 341 to 280. [2018-11-23 00:56:13,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-11-23 00:56:13,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 388 transitions. [2018-11-23 00:56:13,676 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 388 transitions. Word has length 150 [2018-11-23 00:56:13,677 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:13,677 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 388 transitions. [2018-11-23 00:56:13,677 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:13,677 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 388 transitions. [2018-11-23 00:56:13,678 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:13,678 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:13,678 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:13,679 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:13,679 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:13,679 INFO L82 PathProgramCache]: Analyzing trace with hash -1845659798, now seen corresponding path program 1 times [2018-11-23 00:56:13,679 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:13,679 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:13,680 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:13,680 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:13,680 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:13,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:13,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:13,754 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:13,754 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:13,754 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:13,754 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:13,755 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:13,755 INFO L87 Difference]: Start difference. First operand 280 states and 388 transitions. Second operand 5 states. [2018-11-23 00:56:14,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:14,148 INFO L93 Difference]: Finished difference Result 595 states and 851 transitions. [2018-11-23 00:56:14,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 00:56:14,148 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:14,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:14,149 INFO L225 Difference]: With dead ends: 595 [2018-11-23 00:56:14,149 INFO L226 Difference]: Without dead ends: 339 [2018-11-23 00:56:14,150 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:14,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 339 states. [2018-11-23 00:56:14,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 339 to 280. [2018-11-23 00:56:14,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-11-23 00:56:14,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 387 transitions. [2018-11-23 00:56:14,165 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 387 transitions. Word has length 150 [2018-11-23 00:56:14,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:14,165 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 387 transitions. [2018-11-23 00:56:14,165 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:14,165 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 387 transitions. [2018-11-23 00:56:14,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:14,166 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:14,167 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:14,167 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:14,167 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:14,167 INFO L82 PathProgramCache]: Analyzing trace with hash 83272428, now seen corresponding path program 1 times [2018-11-23 00:56:14,167 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:14,167 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:14,167 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:14,168 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:14,168 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:14,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:14,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:14,209 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:14,210 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:14,210 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:14,210 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:14,210 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:14,210 INFO L87 Difference]: Start difference. First operand 280 states and 387 transitions. Second operand 5 states. [2018-11-23 00:56:14,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:14,614 INFO L93 Difference]: Finished difference Result 593 states and 845 transitions. [2018-11-23 00:56:14,615 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 00:56:14,615 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:14,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:14,617 INFO L225 Difference]: With dead ends: 593 [2018-11-23 00:56:14,617 INFO L226 Difference]: Without dead ends: 337 [2018-11-23 00:56:14,617 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:14,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 337 states. [2018-11-23 00:56:14,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 337 to 280. [2018-11-23 00:56:14,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-11-23 00:56:14,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 386 transitions. [2018-11-23 00:56:14,641 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 386 transitions. Word has length 150 [2018-11-23 00:56:14,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:14,641 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 386 transitions. [2018-11-23 00:56:14,641 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:14,642 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 386 transitions. [2018-11-23 00:56:14,643 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:14,643 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:14,643 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:14,643 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:14,643 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:14,644 INFO L82 PathProgramCache]: Analyzing trace with hash 2085158698, now seen corresponding path program 1 times [2018-11-23 00:56:14,644 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:14,644 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:14,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:14,644 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:14,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:14,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:14,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:14,698 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:14,698 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:14,699 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:14,699 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:14,699 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:14,699 INFO L87 Difference]: Start difference. First operand 280 states and 386 transitions. Second operand 5 states. [2018-11-23 00:56:15,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:15,104 INFO L93 Difference]: Finished difference Result 591 states and 839 transitions. [2018-11-23 00:56:15,105 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 00:56:15,105 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:15,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:15,107 INFO L225 Difference]: With dead ends: 591 [2018-11-23 00:56:15,107 INFO L226 Difference]: Without dead ends: 335 [2018-11-23 00:56:15,108 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:15,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 335 states. [2018-11-23 00:56:15,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 335 to 280. [2018-11-23 00:56:15,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-11-23 00:56:15,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 385 transitions. [2018-11-23 00:56:15,136 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 385 transitions. Word has length 150 [2018-11-23 00:56:15,136 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:15,136 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 385 transitions. [2018-11-23 00:56:15,136 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:15,137 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 385 transitions. [2018-11-23 00:56:15,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:15,137 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:15,138 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:15,138 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:15,138 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:15,138 INFO L82 PathProgramCache]: Analyzing trace with hash -482663636, now seen corresponding path program 1 times [2018-11-23 00:56:15,138 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:15,138 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:15,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:15,139 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:15,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:15,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:15,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:15,196 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:15,196 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:15,196 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:15,197 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:15,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:15,197 INFO L87 Difference]: Start difference. First operand 280 states and 385 transitions. Second operand 5 states. [2018-11-23 00:56:15,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:15,723 INFO L93 Difference]: Finished difference Result 589 states and 833 transitions. [2018-11-23 00:56:15,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 00:56:15,724 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:15,724 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:15,726 INFO L225 Difference]: With dead ends: 589 [2018-11-23 00:56:15,726 INFO L226 Difference]: Without dead ends: 333 [2018-11-23 00:56:15,727 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:15,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 333 states. [2018-11-23 00:56:15,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 333 to 280. [2018-11-23 00:56:15,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-11-23 00:56:15,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 384 transitions. [2018-11-23 00:56:15,756 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 384 transitions. Word has length 150 [2018-11-23 00:56:15,756 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:15,756 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 384 transitions. [2018-11-23 00:56:15,756 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:15,756 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 384 transitions. [2018-11-23 00:56:15,757 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:15,757 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:15,757 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:15,758 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:15,758 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:15,758 INFO L82 PathProgramCache]: Analyzing trace with hash -11307286, now seen corresponding path program 1 times [2018-11-23 00:56:15,758 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:15,758 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:15,759 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:15,759 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:15,759 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:15,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:15,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:15,829 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:15,829 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 00:56:15,829 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 00:56:15,829 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 00:56:15,829 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 00:56:15,830 INFO L87 Difference]: Start difference. First operand 280 states and 384 transitions. Second operand 4 states. [2018-11-23 00:56:16,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:16,177 INFO L93 Difference]: Finished difference Result 782 states and 1109 transitions. [2018-11-23 00:56:16,178 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 00:56:16,178 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 150 [2018-11-23 00:56:16,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:16,180 INFO L225 Difference]: With dead ends: 782 [2018-11-23 00:56:16,181 INFO L226 Difference]: Without dead ends: 527 [2018-11-23 00:56:16,182 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 00:56:16,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states. [2018-11-23 00:56:16,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 522. [2018-11-23 00:56:16,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 522 states. [2018-11-23 00:56:16,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 522 states to 522 states and 716 transitions. [2018-11-23 00:56:16,239 INFO L78 Accepts]: Start accepts. Automaton has 522 states and 716 transitions. Word has length 150 [2018-11-23 00:56:16,240 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:16,240 INFO L480 AbstractCegarLoop]: Abstraction has 522 states and 716 transitions. [2018-11-23 00:56:16,240 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 00:56:16,240 INFO L276 IsEmpty]: Start isEmpty. Operand 522 states and 716 transitions. [2018-11-23 00:56:16,240 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:16,241 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:16,241 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:16,241 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:16,241 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:16,241 INFO L82 PathProgramCache]: Analyzing trace with hash 276152619, now seen corresponding path program 1 times [2018-11-23 00:56:16,241 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:16,241 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:16,242 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:16,242 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:16,242 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:16,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:16,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:16,310 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:16,310 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 00:56:16,310 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 00:56:16,310 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 00:56:16,311 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:16,311 INFO L87 Difference]: Start difference. First operand 522 states and 716 transitions. Second operand 6 states. [2018-11-23 00:56:16,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:16,428 INFO L93 Difference]: Finished difference Result 1044 states and 1470 transitions. [2018-11-23 00:56:16,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 00:56:16,428 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 150 [2018-11-23 00:56:16,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:16,431 INFO L225 Difference]: With dead ends: 1044 [2018-11-23 00:56:16,431 INFO L226 Difference]: Without dead ends: 547 [2018-11-23 00:56:16,433 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 00:56:16,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547 states. [2018-11-23 00:56:16,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547 to 527. [2018-11-23 00:56:16,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2018-11-23 00:56:16,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 720 transitions. [2018-11-23 00:56:16,517 INFO L78 Accepts]: Start accepts. Automaton has 527 states and 720 transitions. Word has length 150 [2018-11-23 00:56:16,518 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:16,518 INFO L480 AbstractCegarLoop]: Abstraction has 527 states and 720 transitions. [2018-11-23 00:56:16,518 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 00:56:16,518 INFO L276 IsEmpty]: Start isEmpty. Operand 527 states and 720 transitions. [2018-11-23 00:56:16,519 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:16,519 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:16,519 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:16,519 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:16,519 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:16,519 INFO L82 PathProgramCache]: Analyzing trace with hash 1307193517, now seen corresponding path program 1 times [2018-11-23 00:56:16,519 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:16,519 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:16,520 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:16,520 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:16,520 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:16,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:16,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:16,582 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:16,582 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 00:56:16,583 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 00:56:16,583 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 00:56:16,583 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 00:56:16,583 INFO L87 Difference]: Start difference. First operand 527 states and 720 transitions. Second operand 4 states. [2018-11-23 00:56:16,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:16,997 INFO L93 Difference]: Finished difference Result 1518 states and 2144 transitions. [2018-11-23 00:56:16,997 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 00:56:16,997 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 150 [2018-11-23 00:56:16,997 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:17,001 INFO L225 Difference]: With dead ends: 1518 [2018-11-23 00:56:17,001 INFO L226 Difference]: Without dead ends: 1016 [2018-11-23 00:56:17,004 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 00:56:17,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1016 states. [2018-11-23 00:56:17,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1016 to 1009. [2018-11-23 00:56:17,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1009 states. [2018-11-23 00:56:17,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1009 states to 1009 states and 1377 transitions. [2018-11-23 00:56:17,111 INFO L78 Accepts]: Start accepts. Automaton has 1009 states and 1377 transitions. Word has length 150 [2018-11-23 00:56:17,111 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:17,111 INFO L480 AbstractCegarLoop]: Abstraction has 1009 states and 1377 transitions. [2018-11-23 00:56:17,111 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 00:56:17,111 INFO L276 IsEmpty]: Start isEmpty. Operand 1009 states and 1377 transitions. [2018-11-23 00:56:17,112 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:17,112 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:17,112 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:17,112 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:17,113 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:17,113 INFO L82 PathProgramCache]: Analyzing trace with hash 1662789964, now seen corresponding path program 1 times [2018-11-23 00:56:17,113 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:17,113 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:17,113 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:17,113 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:17,114 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:17,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:17,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:17,164 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:17,164 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 00:56:17,164 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 00:56:17,165 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 00:56:17,165 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:17,165 INFO L87 Difference]: Start difference. First operand 1009 states and 1377 transitions. Second operand 6 states. [2018-11-23 00:56:17,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:17,320 INFO L93 Difference]: Finished difference Result 2037 states and 2852 transitions. [2018-11-23 00:56:17,321 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 00:56:17,321 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 150 [2018-11-23 00:56:17,321 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:17,325 INFO L225 Difference]: With dead ends: 2037 [2018-11-23 00:56:17,325 INFO L226 Difference]: Without dead ends: 1053 [2018-11-23 00:56:17,328 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 00:56:17,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1053 states. [2018-11-23 00:56:17,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1053 to 1019. [2018-11-23 00:56:17,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1019 states. [2018-11-23 00:56:17,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1019 states to 1019 states and 1385 transitions. [2018-11-23 00:56:17,432 INFO L78 Accepts]: Start accepts. Automaton has 1019 states and 1385 transitions. Word has length 150 [2018-11-23 00:56:17,433 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:17,433 INFO L480 AbstractCegarLoop]: Abstraction has 1019 states and 1385 transitions. [2018-11-23 00:56:17,433 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 00:56:17,433 INFO L276 IsEmpty]: Start isEmpty. Operand 1019 states and 1385 transitions. [2018-11-23 00:56:17,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:17,434 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:17,434 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:17,434 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:17,434 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:17,434 INFO L82 PathProgramCache]: Analyzing trace with hash -755114102, now seen corresponding path program 1 times [2018-11-23 00:56:17,434 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:17,434 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:17,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:17,435 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:17,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:17,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:17,492 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:17,493 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:17,493 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 00:56:17,493 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 00:56:17,493 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 00:56:17,493 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 00:56:17,493 INFO L87 Difference]: Start difference. First operand 1019 states and 1385 transitions. Second operand 4 states. [2018-11-23 00:56:17,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:17,967 INFO L93 Difference]: Finished difference Result 2982 states and 4193 transitions. [2018-11-23 00:56:17,967 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 00:56:17,967 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 150 [2018-11-23 00:56:17,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:17,998 INFO L225 Difference]: With dead ends: 2982 [2018-11-23 00:56:17,998 INFO L226 Difference]: Without dead ends: 1988 [2018-11-23 00:56:18,002 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 00:56:18,004 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states. [2018-11-23 00:56:18,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1977. [2018-11-23 00:56:18,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1977 states. [2018-11-23 00:56:18,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1977 states to 1977 states and 2685 transitions. [2018-11-23 00:56:18,202 INFO L78 Accepts]: Start accepts. Automaton has 1977 states and 2685 transitions. Word has length 150 [2018-11-23 00:56:18,202 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:18,202 INFO L480 AbstractCegarLoop]: Abstraction has 1977 states and 2685 transitions. [2018-11-23 00:56:18,202 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 00:56:18,202 INFO L276 IsEmpty]: Start isEmpty. Operand 1977 states and 2685 transitions. [2018-11-23 00:56:18,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:18,203 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:18,204 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:18,204 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:18,204 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:18,204 INFO L82 PathProgramCache]: Analyzing trace with hash 2054613003, now seen corresponding path program 1 times [2018-11-23 00:56:18,204 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:18,204 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:18,205 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:18,205 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:18,205 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:18,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:18,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:18,278 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:18,278 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 00:56:18,278 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 00:56:18,279 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 00:56:18,279 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:18,279 INFO L87 Difference]: Start difference. First operand 1977 states and 2685 transitions. Second operand 6 states. [2018-11-23 00:56:18,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:18,521 INFO L93 Difference]: Finished difference Result 4005 states and 5580 transitions. [2018-11-23 00:56:18,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 00:56:18,522 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 150 [2018-11-23 00:56:18,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:18,533 INFO L225 Difference]: With dead ends: 4005 [2018-11-23 00:56:18,533 INFO L226 Difference]: Without dead ends: 2053 [2018-11-23 00:56:18,540 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 00:56:18,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2053 states. [2018-11-23 00:56:18,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2053 to 1997. [2018-11-23 00:56:18,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1997 states. [2018-11-23 00:56:18,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1997 states to 1997 states and 2701 transitions. [2018-11-23 00:56:18,745 INFO L78 Accepts]: Start accepts. Automaton has 1997 states and 2701 transitions. Word has length 150 [2018-11-23 00:56:18,745 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:18,745 INFO L480 AbstractCegarLoop]: Abstraction has 1997 states and 2701 transitions. [2018-11-23 00:56:18,745 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 00:56:18,745 INFO L276 IsEmpty]: Start isEmpty. Operand 1997 states and 2701 transitions. [2018-11-23 00:56:18,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:18,746 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:18,746 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:18,746 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:18,747 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:18,747 INFO L82 PathProgramCache]: Analyzing trace with hash 996774925, now seen corresponding path program 1 times [2018-11-23 00:56:18,747 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:18,747 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:18,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:18,748 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:18,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:18,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:18,805 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:18,805 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:18,806 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 00:56:18,806 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 00:56:18,806 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 00:56:18,806 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:18,807 INFO L87 Difference]: Start difference. First operand 1997 states and 2701 transitions. Second operand 6 states. [2018-11-23 00:56:19,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:19,000 INFO L93 Difference]: Finished difference Result 4097 states and 5693 transitions. [2018-11-23 00:56:19,000 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 00:56:19,000 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 150 [2018-11-23 00:56:19,001 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:19,006 INFO L225 Difference]: With dead ends: 4097 [2018-11-23 00:56:19,006 INFO L226 Difference]: Without dead ends: 2125 [2018-11-23 00:56:19,011 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 00:56:19,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2125 states. [2018-11-23 00:56:19,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2125 to 2037. [2018-11-23 00:56:19,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2037 states. [2018-11-23 00:56:19,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 2741 transitions. [2018-11-23 00:56:19,161 INFO L78 Accepts]: Start accepts. Automaton has 2037 states and 2741 transitions. Word has length 150 [2018-11-23 00:56:19,161 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:19,161 INFO L480 AbstractCegarLoop]: Abstraction has 2037 states and 2741 transitions. [2018-11-23 00:56:19,161 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 00:56:19,161 INFO L276 IsEmpty]: Start isEmpty. Operand 2037 states and 2741 transitions. [2018-11-23 00:56:19,163 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:19,163 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:19,163 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:19,163 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:19,163 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:19,163 INFO L82 PathProgramCache]: Analyzing trace with hash 1073675723, now seen corresponding path program 1 times [2018-11-23 00:56:19,164 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:19,164 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:19,164 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:19,165 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:19,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:19,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:19,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:19,236 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:19,236 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 00:56:19,237 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 00:56:19,237 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 00:56:19,237 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 00:56:19,237 INFO L87 Difference]: Start difference. First operand 2037 states and 2741 transitions. Second operand 4 states. [2018-11-23 00:56:19,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:19,699 INFO L93 Difference]: Finished difference Result 6012 states and 8379 transitions. [2018-11-23 00:56:19,700 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 00:56:19,700 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 150 [2018-11-23 00:56:19,700 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:19,710 INFO L225 Difference]: With dead ends: 6012 [2018-11-23 00:56:19,710 INFO L226 Difference]: Without dead ends: 4000 [2018-11-23 00:56:19,716 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 00:56:19,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4000 states. [2018-11-23 00:56:19,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4000 to 3981. [2018-11-23 00:56:19,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3981 states. [2018-11-23 00:56:19,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3981 states to 3981 states and 5359 transitions. [2018-11-23 00:56:19,961 INFO L78 Accepts]: Start accepts. Automaton has 3981 states and 5359 transitions. Word has length 150 [2018-11-23 00:56:19,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:19,961 INFO L480 AbstractCegarLoop]: Abstraction has 3981 states and 5359 transitions. [2018-11-23 00:56:19,961 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 00:56:19,962 INFO L276 IsEmpty]: Start isEmpty. Operand 3981 states and 5359 transitions. [2018-11-23 00:56:19,963 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:19,963 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:19,963 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:19,963 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:19,963 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:19,963 INFO L82 PathProgramCache]: Analyzing trace with hash -2083662708, now seen corresponding path program 1 times [2018-11-23 00:56:19,964 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:19,964 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:19,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:19,965 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:19,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:19,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:20,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:20,016 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:20,016 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 00:56:20,016 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 00:56:20,016 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 00:56:20,016 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:20,017 INFO L87 Difference]: Start difference. First operand 3981 states and 5359 transitions. Second operand 6 states. [2018-11-23 00:56:20,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:20,321 INFO L93 Difference]: Finished difference Result 8041 states and 11102 transitions. [2018-11-23 00:56:20,322 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 00:56:20,322 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 150 [2018-11-23 00:56:20,322 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:20,334 INFO L225 Difference]: With dead ends: 8041 [2018-11-23 00:56:20,334 INFO L226 Difference]: Without dead ends: 4085 [2018-11-23 00:56:20,345 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 00:56:20,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4085 states. [2018-11-23 00:56:20,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4085 to 4021. [2018-11-23 00:56:20,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4021 states. [2018-11-23 00:56:20,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4021 states to 4021 states and 5391 transitions. [2018-11-23 00:56:20,660 INFO L78 Accepts]: Start accepts. Automaton has 4021 states and 5391 transitions. Word has length 150 [2018-11-23 00:56:20,660 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:20,660 INFO L480 AbstractCegarLoop]: Abstraction has 4021 states and 5391 transitions. [2018-11-23 00:56:20,660 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 00:56:20,660 INFO L276 IsEmpty]: Start isEmpty. Operand 4021 states and 5391 transitions. [2018-11-23 00:56:20,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:20,661 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:20,661 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:20,661 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:20,662 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:20,662 INFO L82 PathProgramCache]: Analyzing trace with hash 1793907982, now seen corresponding path program 1 times [2018-11-23 00:56:20,662 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:20,662 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:20,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:20,663 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:20,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:20,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:20,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:20,726 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:20,726 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 00:56:20,727 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 00:56:20,727 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 00:56:20,727 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:20,727 INFO L87 Difference]: Start difference. First operand 4021 states and 5391 transitions. Second operand 6 states. [2018-11-23 00:56:21,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:21,017 INFO L93 Difference]: Finished difference Result 8177 states and 11247 transitions. [2018-11-23 00:56:21,017 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 00:56:21,018 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 150 [2018-11-23 00:56:21,018 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:21,029 INFO L225 Difference]: With dead ends: 8177 [2018-11-23 00:56:21,029 INFO L226 Difference]: Without dead ends: 4181 [2018-11-23 00:56:21,039 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 00:56:21,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4181 states. [2018-11-23 00:56:21,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4181 to 4101. [2018-11-23 00:56:21,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4101 states. [2018-11-23 00:56:21,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4101 states to 4101 states and 5471 transitions. [2018-11-23 00:56:21,280 INFO L78 Accepts]: Start accepts. Automaton has 4101 states and 5471 transitions. Word has length 150 [2018-11-23 00:56:21,280 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:21,280 INFO L480 AbstractCegarLoop]: Abstraction has 4101 states and 5471 transitions. [2018-11-23 00:56:21,281 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 00:56:21,281 INFO L276 IsEmpty]: Start isEmpty. Operand 4101 states and 5471 transitions. [2018-11-23 00:56:21,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:21,282 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:21,282 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:21,282 INFO L423 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:21,282 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:21,282 INFO L82 PathProgramCache]: Analyzing trace with hash -1625040308, now seen corresponding path program 1 times [2018-11-23 00:56:21,283 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:21,283 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:21,283 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:21,283 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:21,283 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:21,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:21,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:21,345 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:21,345 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 00:56:21,345 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 00:56:21,345 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 00:56:21,346 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:21,346 INFO L87 Difference]: Start difference. First operand 4101 states and 5471 transitions. Second operand 6 states. [2018-11-23 00:56:21,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:21,619 INFO L93 Difference]: Finished difference Result 8289 states and 11327 transitions. [2018-11-23 00:56:21,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 00:56:21,619 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 150 [2018-11-23 00:56:21,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:21,633 INFO L225 Difference]: With dead ends: 8289 [2018-11-23 00:56:21,633 INFO L226 Difference]: Without dead ends: 4213 [2018-11-23 00:56:21,641 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 00:56:21,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4213 states. [2018-11-23 00:56:21,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4213 to 4181. [2018-11-23 00:56:21,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4181 states. [2018-11-23 00:56:21,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4181 states to 4181 states and 5551 transitions. [2018-11-23 00:56:21,863 INFO L78 Accepts]: Start accepts. Automaton has 4181 states and 5551 transitions. Word has length 150 [2018-11-23 00:56:21,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:21,863 INFO L480 AbstractCegarLoop]: Abstraction has 4181 states and 5551 transitions. [2018-11-23 00:56:21,863 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 00:56:21,863 INFO L276 IsEmpty]: Start isEmpty. Operand 4181 states and 5551 transitions. [2018-11-23 00:56:21,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:21,864 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:21,864 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:21,864 INFO L423 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:21,865 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:21,865 INFO L82 PathProgramCache]: Analyzing trace with hash -731553970, now seen corresponding path program 1 times [2018-11-23 00:56:21,865 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:21,865 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:21,865 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:21,866 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:21,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:21,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:21,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:21,928 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:21,928 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:21,928 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:21,928 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:21,928 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:21,929 INFO L87 Difference]: Start difference. First operand 4181 states and 5551 transitions. Second operand 5 states. [2018-11-23 00:56:22,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:22,782 INFO L93 Difference]: Finished difference Result 10280 states and 13864 transitions. [2018-11-23 00:56:22,783 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 00:56:22,783 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:22,783 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:22,796 INFO L225 Difference]: With dead ends: 10280 [2018-11-23 00:56:22,796 INFO L226 Difference]: Without dead ends: 6125 [2018-11-23 00:56:22,803 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 00:56:22,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6125 states. [2018-11-23 00:56:23,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6125 to 5757. [2018-11-23 00:56:23,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5757 states. [2018-11-23 00:56:23,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5757 states to 5757 states and 7407 transitions. [2018-11-23 00:56:23,096 INFO L78 Accepts]: Start accepts. Automaton has 5757 states and 7407 transitions. Word has length 150 [2018-11-23 00:56:23,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:23,096 INFO L480 AbstractCegarLoop]: Abstraction has 5757 states and 7407 transitions. [2018-11-23 00:56:23,097 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:23,097 INFO L276 IsEmpty]: Start isEmpty. Operand 5757 states and 7407 transitions. [2018-11-23 00:56:23,097 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:23,097 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:23,098 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:23,098 INFO L423 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:23,098 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:23,098 INFO L82 PathProgramCache]: Analyzing trace with hash -307907248, now seen corresponding path program 1 times [2018-11-23 00:56:23,098 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:23,098 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:23,099 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:23,099 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:23,099 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:23,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:23,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:23,156 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:23,156 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:23,157 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:23,157 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:23,157 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:23,157 INFO L87 Difference]: Start difference. First operand 5757 states and 7407 transitions. Second operand 5 states. [2018-11-23 00:56:23,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:23,741 INFO L93 Difference]: Finished difference Result 11488 states and 14827 transitions. [2018-11-23 00:56:23,741 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 00:56:23,741 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:23,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:23,759 INFO L225 Difference]: With dead ends: 11488 [2018-11-23 00:56:23,759 INFO L226 Difference]: Without dead ends: 5757 [2018-11-23 00:56:23,770 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:23,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5757 states. [2018-11-23 00:56:24,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5757 to 5757. [2018-11-23 00:56:24,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5757 states. [2018-11-23 00:56:24,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5757 states to 5757 states and 7367 transitions. [2018-11-23 00:56:24,171 INFO L78 Accepts]: Start accepts. Automaton has 5757 states and 7367 transitions. Word has length 150 [2018-11-23 00:56:24,171 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:24,171 INFO L480 AbstractCegarLoop]: Abstraction has 5757 states and 7367 transitions. [2018-11-23 00:56:24,171 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:24,171 INFO L276 IsEmpty]: Start isEmpty. Operand 5757 states and 7367 transitions. [2018-11-23 00:56:24,172 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:24,172 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:24,172 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:24,173 INFO L423 AbstractCegarLoop]: === Iteration 27 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:24,173 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:24,173 INFO L82 PathProgramCache]: Analyzing trace with hash -1679714546, now seen corresponding path program 1 times [2018-11-23 00:56:24,173 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:24,173 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:24,174 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:24,174 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:24,174 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:24,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:24,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:24,236 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:24,236 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:24,236 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:24,236 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:24,236 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:24,237 INFO L87 Difference]: Start difference. First operand 5757 states and 7367 transitions. Second operand 5 states. [2018-11-23 00:56:24,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:24,957 INFO L93 Difference]: Finished difference Result 11488 states and 14747 transitions. [2018-11-23 00:56:24,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 00:56:24,958 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:24,958 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:24,968 INFO L225 Difference]: With dead ends: 11488 [2018-11-23 00:56:24,968 INFO L226 Difference]: Without dead ends: 5757 [2018-11-23 00:56:24,976 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:24,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5757 states. [2018-11-23 00:56:25,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5757 to 5757. [2018-11-23 00:56:25,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5757 states. [2018-11-23 00:56:25,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5757 states to 5757 states and 7327 transitions. [2018-11-23 00:56:25,391 INFO L78 Accepts]: Start accepts. Automaton has 5757 states and 7327 transitions. Word has length 150 [2018-11-23 00:56:25,391 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:25,391 INFO L480 AbstractCegarLoop]: Abstraction has 5757 states and 7327 transitions. [2018-11-23 00:56:25,391 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:25,391 INFO L276 IsEmpty]: Start isEmpty. Operand 5757 states and 7327 transitions. [2018-11-23 00:56:25,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:25,393 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:25,393 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:25,393 INFO L423 AbstractCegarLoop]: === Iteration 28 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:25,394 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:25,394 INFO L82 PathProgramCache]: Analyzing trace with hash 1585893452, now seen corresponding path program 1 times [2018-11-23 00:56:25,394 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:25,394 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:25,395 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:25,395 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:25,395 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:25,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:25,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:25,470 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:25,470 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:25,471 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:25,471 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:25,471 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:25,471 INFO L87 Difference]: Start difference. First operand 5757 states and 7327 transitions. Second operand 5 states. [2018-11-23 00:56:26,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:26,096 INFO L93 Difference]: Finished difference Result 11488 states and 14667 transitions. [2018-11-23 00:56:26,096 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 00:56:26,096 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:26,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:26,106 INFO L225 Difference]: With dead ends: 11488 [2018-11-23 00:56:26,106 INFO L226 Difference]: Without dead ends: 5757 [2018-11-23 00:56:26,113 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:26,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5757 states. [2018-11-23 00:56:26,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5757 to 5757. [2018-11-23 00:56:26,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5757 states. [2018-11-23 00:56:26,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5757 states to 5757 states and 7287 transitions. [2018-11-23 00:56:26,427 INFO L78 Accepts]: Start accepts. Automaton has 5757 states and 7287 transitions. Word has length 150 [2018-11-23 00:56:26,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:26,427 INFO L480 AbstractCegarLoop]: Abstraction has 5757 states and 7287 transitions. [2018-11-23 00:56:26,427 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:26,427 INFO L276 IsEmpty]: Start isEmpty. Operand 5757 states and 7287 transitions. [2018-11-23 00:56:26,428 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:26,428 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:26,428 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:26,428 INFO L423 AbstractCegarLoop]: === Iteration 29 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:26,428 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:26,429 INFO L82 PathProgramCache]: Analyzing trace with hash -2049542322, now seen corresponding path program 1 times [2018-11-23 00:56:26,429 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:26,429 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:26,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:26,429 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:26,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:26,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:26,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:26,534 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:26,534 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:26,534 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:26,534 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:26,536 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:26,536 INFO L87 Difference]: Start difference. First operand 5757 states and 7287 transitions. Second operand 5 states. [2018-11-23 00:56:27,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:27,485 INFO L93 Difference]: Finished difference Result 13698 states and 17482 transitions. [2018-11-23 00:56:27,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 00:56:27,485 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:27,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:27,501 INFO L225 Difference]: With dead ends: 13698 [2018-11-23 00:56:27,501 INFO L226 Difference]: Without dead ends: 7967 [2018-11-23 00:56:27,510 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 00:56:27,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7967 states. [2018-11-23 00:56:27,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7967 to 7671. [2018-11-23 00:56:27,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7671 states. [2018-11-23 00:56:27,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7671 states to 7671 states and 9517 transitions. [2018-11-23 00:56:27,914 INFO L78 Accepts]: Start accepts. Automaton has 7671 states and 9517 transitions. Word has length 150 [2018-11-23 00:56:27,914 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:27,914 INFO L480 AbstractCegarLoop]: Abstraction has 7671 states and 9517 transitions. [2018-11-23 00:56:27,914 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:27,914 INFO L276 IsEmpty]: Start isEmpty. Operand 7671 states and 9517 transitions. [2018-11-23 00:56:27,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:27,915 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:27,915 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:27,915 INFO L423 AbstractCegarLoop]: === Iteration 30 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:27,915 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:27,915 INFO L82 PathProgramCache]: Analyzing trace with hash 1851058188, now seen corresponding path program 1 times [2018-11-23 00:56:27,915 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:27,915 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:27,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:27,916 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:27,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:27,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:27,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:27,987 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:27,988 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:27,988 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:27,988 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:27,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:27,988 INFO L87 Difference]: Start difference. First operand 7671 states and 9517 transitions. Second operand 5 states. [2018-11-23 00:56:28,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:28,787 INFO L93 Difference]: Finished difference Result 15314 states and 19075 transitions. [2018-11-23 00:56:28,788 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 00:56:28,788 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:28,788 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:28,799 INFO L225 Difference]: With dead ends: 15314 [2018-11-23 00:56:28,799 INFO L226 Difference]: Without dead ends: 7671 [2018-11-23 00:56:28,806 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:56:28,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7671 states. [2018-11-23 00:56:29,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7671 to 7671. [2018-11-23 00:56:29,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7671 states. [2018-11-23 00:56:29,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7671 states to 7671 states and 9461 transitions. [2018-11-23 00:56:29,191 INFO L78 Accepts]: Start accepts. Automaton has 7671 states and 9461 transitions. Word has length 150 [2018-11-23 00:56:29,191 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:29,191 INFO L480 AbstractCegarLoop]: Abstraction has 7671 states and 9461 transitions. [2018-11-23 00:56:29,191 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:29,191 INFO L276 IsEmpty]: Start isEmpty. Operand 7671 states and 9461 transitions. [2018-11-23 00:56:29,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:29,193 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:29,193 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:29,193 INFO L423 AbstractCegarLoop]: === Iteration 31 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:29,193 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:29,193 INFO L82 PathProgramCache]: Analyzing trace with hash 1007052686, now seen corresponding path program 1 times [2018-11-23 00:56:29,193 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:29,193 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:29,194 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:29,194 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:29,194 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:29,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:29,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:29,258 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:29,258 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:29,258 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:29,259 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:29,259 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:29,259 INFO L87 Difference]: Start difference. First operand 7671 states and 9461 transitions. Second operand 5 states. [2018-11-23 00:56:30,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:30,316 INFO L93 Difference]: Finished difference Result 16190 states and 20277 transitions. [2018-11-23 00:56:30,316 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 00:56:30,316 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:30,317 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:30,331 INFO L225 Difference]: With dead ends: 16190 [2018-11-23 00:56:30,331 INFO L226 Difference]: Without dead ends: 8547 [2018-11-23 00:56:30,341 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 00:56:30,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8547 states. [2018-11-23 00:56:30,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8547 to 8543. [2018-11-23 00:56:30,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8543 states. [2018-11-23 00:56:31,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8543 states to 8543 states and 10497 transitions. [2018-11-23 00:56:31,004 INFO L78 Accepts]: Start accepts. Automaton has 8543 states and 10497 transitions. Word has length 150 [2018-11-23 00:56:31,004 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:31,004 INFO L480 AbstractCegarLoop]: Abstraction has 8543 states and 10497 transitions. [2018-11-23 00:56:31,004 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:31,004 INFO L276 IsEmpty]: Start isEmpty. Operand 8543 states and 10497 transitions. [2018-11-23 00:56:31,005 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:31,005 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:31,005 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:31,005 INFO L423 AbstractCegarLoop]: === Iteration 32 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:31,005 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:31,005 INFO L82 PathProgramCache]: Analyzing trace with hash -1236930612, now seen corresponding path program 1 times [2018-11-23 00:56:31,005 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:31,005 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:31,006 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:31,006 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:31,006 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:31,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:31,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:31,115 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:31,115 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:31,115 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:31,115 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:31,116 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:31,116 INFO L87 Difference]: Start difference. First operand 8543 states and 10497 transitions. Second operand 5 states. [2018-11-23 00:56:32,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:32,231 INFO L93 Difference]: Finished difference Result 18174 states and 23002 transitions. [2018-11-23 00:56:32,231 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 00:56:32,231 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:32,231 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:32,248 INFO L225 Difference]: With dead ends: 18174 [2018-11-23 00:56:32,248 INFO L226 Difference]: Without dead ends: 9659 [2018-11-23 00:56:32,259 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 00:56:32,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9659 states. [2018-11-23 00:56:32,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9659 to 9167. [2018-11-23 00:56:32,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9167 states. [2018-11-23 00:56:32,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9167 states to 9167 states and 11093 transitions. [2018-11-23 00:56:32,914 INFO L78 Accepts]: Start accepts. Automaton has 9167 states and 11093 transitions. Word has length 150 [2018-11-23 00:56:32,915 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:32,915 INFO L480 AbstractCegarLoop]: Abstraction has 9167 states and 11093 transitions. [2018-11-23 00:56:32,915 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:32,915 INFO L276 IsEmpty]: Start isEmpty. Operand 9167 states and 11093 transitions. [2018-11-23 00:56:32,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:32,916 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:32,916 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:32,916 INFO L423 AbstractCegarLoop]: === Iteration 33 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:32,916 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:32,916 INFO L82 PathProgramCache]: Analyzing trace with hash -1309317170, now seen corresponding path program 1 times [2018-11-23 00:56:32,916 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:32,916 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:32,917 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:32,917 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:32,917 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:32,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:33,013 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:33,013 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:33,014 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:33,014 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:33,014 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:33,014 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:33,014 INFO L87 Difference]: Start difference. First operand 9167 states and 11093 transitions. Second operand 5 states. [2018-11-23 00:56:34,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:34,269 INFO L93 Difference]: Finished difference Result 19620 states and 24642 transitions. [2018-11-23 00:56:34,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 00:56:34,269 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:34,269 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:34,288 INFO L225 Difference]: With dead ends: 19620 [2018-11-23 00:56:34,288 INFO L226 Difference]: Without dead ends: 10479 [2018-11-23 00:56:34,302 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 00:56:34,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10479 states. [2018-11-23 00:56:34,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10479 to 9615. [2018-11-23 00:56:34,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9615 states. [2018-11-23 00:56:34,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9615 states to 9615 states and 11445 transitions. [2018-11-23 00:56:34,840 INFO L78 Accepts]: Start accepts. Automaton has 9615 states and 11445 transitions. Word has length 150 [2018-11-23 00:56:34,841 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:34,841 INFO L480 AbstractCegarLoop]: Abstraction has 9615 states and 11445 transitions. [2018-11-23 00:56:34,841 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:34,841 INFO L276 IsEmpty]: Start isEmpty. Operand 9615 states and 11445 transitions. [2018-11-23 00:56:34,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:34,841 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:34,841 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:34,842 INFO L423 AbstractCegarLoop]: === Iteration 34 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:34,842 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:34,842 INFO L82 PathProgramCache]: Analyzing trace with hash -1034557556, now seen corresponding path program 1 times [2018-11-23 00:56:34,842 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:34,842 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:34,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:34,842 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:34,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:34,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:34,902 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:34,902 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:34,902 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:34,903 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:34,903 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:34,903 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:34,903 INFO L87 Difference]: Start difference. First operand 9615 states and 11445 transitions. Second operand 5 states. [2018-11-23 00:56:36,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:36,162 INFO L93 Difference]: Finished difference Result 20240 states and 25054 transitions. [2018-11-23 00:56:36,163 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 00:56:36,163 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:36,163 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:36,183 INFO L225 Difference]: With dead ends: 20240 [2018-11-23 00:56:36,183 INFO L226 Difference]: Without dead ends: 10651 [2018-11-23 00:56:36,197 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 00:56:36,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10651 states. [2018-11-23 00:56:36,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10651 to 10003. [2018-11-23 00:56:36,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10003 states. [2018-11-23 00:56:36,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10003 states to 10003 states and 11713 transitions. [2018-11-23 00:56:36,760 INFO L78 Accepts]: Start accepts. Automaton has 10003 states and 11713 transitions. Word has length 150 [2018-11-23 00:56:36,760 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:36,760 INFO L480 AbstractCegarLoop]: Abstraction has 10003 states and 11713 transitions. [2018-11-23 00:56:36,761 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:36,761 INFO L276 IsEmpty]: Start isEmpty. Operand 10003 states and 11713 transitions. [2018-11-23 00:56:36,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:36,761 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:36,762 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:36,762 INFO L423 AbstractCegarLoop]: === Iteration 35 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:36,762 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:36,762 INFO L82 PathProgramCache]: Analyzing trace with hash -1011925302, now seen corresponding path program 1 times [2018-11-23 00:56:36,762 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:36,762 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:36,763 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:36,763 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:36,763 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:36,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:36,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:36,821 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:36,821 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:56:36,821 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:56:36,822 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:56:36,822 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:56:36,822 INFO L87 Difference]: Start difference. First operand 10003 states and 11713 transitions. Second operand 5 states. [2018-11-23 00:56:38,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:38,211 INFO L93 Difference]: Finished difference Result 22004 states and 27311 transitions. [2018-11-23 00:56:38,211 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 00:56:38,211 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-11-23 00:56:38,212 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:38,233 INFO L225 Difference]: With dead ends: 22004 [2018-11-23 00:56:38,233 INFO L226 Difference]: Without dead ends: 12027 [2018-11-23 00:56:38,247 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 00:56:38,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12027 states. [2018-11-23 00:56:38,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12027 to 10907. [2018-11-23 00:56:38,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10907 states. [2018-11-23 00:56:38,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10907 states to 10907 states and 12529 transitions. [2018-11-23 00:56:38,890 INFO L78 Accepts]: Start accepts. Automaton has 10907 states and 12529 transitions. Word has length 150 [2018-11-23 00:56:38,890 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:38,890 INFO L480 AbstractCegarLoop]: Abstraction has 10907 states and 12529 transitions. [2018-11-23 00:56:38,890 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:56:38,890 INFO L276 IsEmpty]: Start isEmpty. Operand 10907 states and 12529 transitions. [2018-11-23 00:56:38,891 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-11-23 00:56:38,891 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:38,891 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:38,891 INFO L423 AbstractCegarLoop]: === Iteration 36 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:38,891 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:38,891 INFO L82 PathProgramCache]: Analyzing trace with hash 374278092, now seen corresponding path program 1 times [2018-11-23 00:56:38,892 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:38,892 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:38,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:38,892 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:38,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:38,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:38,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:38,951 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:38,951 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:56:38,952 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 00:56:38,952 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:56:38,952 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:56:38,952 INFO L87 Difference]: Start difference. First operand 10907 states and 12529 transitions. Second operand 3 states. [2018-11-23 00:56:40,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:40,343 INFO L93 Difference]: Finished difference Result 31802 states and 36913 transitions. [2018-11-23 00:56:40,343 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:56:40,343 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 150 [2018-11-23 00:56:40,344 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:40,376 INFO L225 Difference]: With dead ends: 31802 [2018-11-23 00:56:40,376 INFO L226 Difference]: Without dead ends: 20923 [2018-11-23 00:56:40,390 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:56:40,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20923 states. [2018-11-23 00:56:41,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20923 to 20920. [2018-11-23 00:56:41,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20920 states. [2018-11-23 00:56:41,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20920 states to 20920 states and 24150 transitions. [2018-11-23 00:56:41,587 INFO L78 Accepts]: Start accepts. Automaton has 20920 states and 24150 transitions. Word has length 150 [2018-11-23 00:56:41,587 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:41,588 INFO L480 AbstractCegarLoop]: Abstraction has 20920 states and 24150 transitions. [2018-11-23 00:56:41,588 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 00:56:41,588 INFO L276 IsEmpty]: Start isEmpty. Operand 20920 states and 24150 transitions. [2018-11-23 00:56:41,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 152 [2018-11-23 00:56:41,589 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:41,589 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:41,589 INFO L423 AbstractCegarLoop]: === Iteration 37 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:41,589 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:41,589 INFO L82 PathProgramCache]: Analyzing trace with hash -333800920, now seen corresponding path program 1 times [2018-11-23 00:56:41,589 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:41,590 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:41,590 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:41,590 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:41,590 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:41,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:41,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:56:41,634 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:41,634 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:56:41,634 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 00:56:41,634 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:56:41,634 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:56:41,635 INFO L87 Difference]: Start difference. First operand 20920 states and 24150 transitions. Second operand 3 states. [2018-11-23 00:56:44,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:44,187 INFO L93 Difference]: Finished difference Result 62015 states and 74436 transitions. [2018-11-23 00:56:44,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:56:44,188 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 151 [2018-11-23 00:56:44,188 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:44,281 INFO L225 Difference]: With dead ends: 62015 [2018-11-23 00:56:44,281 INFO L226 Difference]: Without dead ends: 41132 [2018-11-23 00:56:44,321 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:56:44,350 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41132 states. [2018-11-23 00:56:46,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41132 to 41132. [2018-11-23 00:56:46,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41132 states. [2018-11-23 00:56:46,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41132 states to 41132 states and 48625 transitions. [2018-11-23 00:56:46,991 INFO L78 Accepts]: Start accepts. Automaton has 41132 states and 48625 transitions. Word has length 151 [2018-11-23 00:56:46,992 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:46,992 INFO L480 AbstractCegarLoop]: Abstraction has 41132 states and 48625 transitions. [2018-11-23 00:56:46,992 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 00:56:46,992 INFO L276 IsEmpty]: Start isEmpty. Operand 41132 states and 48625 transitions. [2018-11-23 00:56:46,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 176 [2018-11-23 00:56:46,996 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:46,996 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:46,996 INFO L423 AbstractCegarLoop]: === Iteration 38 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:46,997 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:46,997 INFO L82 PathProgramCache]: Analyzing trace with hash 1925200900, now seen corresponding path program 1 times [2018-11-23 00:56:46,997 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:46,997 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:46,997 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:46,997 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:46,998 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:47,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:47,049 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-23 00:56:47,049 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:47,050 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:56:47,050 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 00:56:47,050 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:56:47,050 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:56:47,050 INFO L87 Difference]: Start difference. First operand 41132 states and 48625 transitions. Second operand 3 states. [2018-11-23 00:56:52,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:56:52,377 INFO L93 Difference]: Finished difference Result 122877 states and 149180 transitions. [2018-11-23 00:56:52,377 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:56:52,377 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 175 [2018-11-23 00:56:52,377 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:56:52,526 INFO L225 Difference]: With dead ends: 122877 [2018-11-23 00:56:52,526 INFO L226 Difference]: Without dead ends: 61528 [2018-11-23 00:56:52,624 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:56:52,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61528 states. [2018-11-23 00:56:56,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61528 to 61528. [2018-11-23 00:56:56,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61528 states. [2018-11-23 00:56:56,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61528 states to 61528 states and 73148 transitions. [2018-11-23 00:56:56,569 INFO L78 Accepts]: Start accepts. Automaton has 61528 states and 73148 transitions. Word has length 175 [2018-11-23 00:56:56,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:56:56,570 INFO L480 AbstractCegarLoop]: Abstraction has 61528 states and 73148 transitions. [2018-11-23 00:56:56,570 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 00:56:56,570 INFO L276 IsEmpty]: Start isEmpty. Operand 61528 states and 73148 transitions. [2018-11-23 00:56:56,607 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 256 [2018-11-23 00:56:56,607 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:56:56,607 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:56:56,607 INFO L423 AbstractCegarLoop]: === Iteration 39 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:56:56,608 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:56:56,608 INFO L82 PathProgramCache]: Analyzing trace with hash 51667787, now seen corresponding path program 1 times [2018-11-23 00:56:56,608 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:56:56,608 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:56:56,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:56,609 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:56:56,609 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:56:56,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:56:56,685 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-11-23 00:56:56,685 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:56:56,685 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:56:56,685 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 00:56:56,686 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:56:56,686 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:56:56,686 INFO L87 Difference]: Start difference. First operand 61528 states and 73148 transitions. Second operand 3 states. [2018-11-23 00:57:03,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:57:03,621 INFO L93 Difference]: Finished difference Result 166880 states and 206719 transitions. [2018-11-23 00:57:03,621 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:57:03,621 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 255 [2018-11-23 00:57:03,621 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:57:03,870 INFO L225 Difference]: With dead ends: 166880 [2018-11-23 00:57:03,870 INFO L226 Difference]: Without dead ends: 105393 [2018-11-23 00:57:03,991 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:57:04,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105393 states. [2018-11-23 00:57:12,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105393 to 105390. [2018-11-23 00:57:12,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105390 states. [2018-11-23 00:57:12,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105390 states to 105390 states and 128474 transitions. [2018-11-23 00:57:12,668 INFO L78 Accepts]: Start accepts. Automaton has 105390 states and 128474 transitions. Word has length 255 [2018-11-23 00:57:12,668 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:57:12,668 INFO L480 AbstractCegarLoop]: Abstraction has 105390 states and 128474 transitions. [2018-11-23 00:57:12,668 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 00:57:12,668 INFO L276 IsEmpty]: Start isEmpty. Operand 105390 states and 128474 transitions. [2018-11-23 00:57:12,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 257 [2018-11-23 00:57:12,715 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:57:12,715 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:57:12,715 INFO L423 AbstractCegarLoop]: === Iteration 40 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:57:12,715 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:57:12,715 INFO L82 PathProgramCache]: Analyzing trace with hash 253056944, now seen corresponding path program 1 times [2018-11-23 00:57:12,715 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:57:12,715 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:57:12,716 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:57:12,716 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:57:12,716 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:57:12,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:57:12,791 INFO L134 CoverageAnalysis]: Checked inductivity of 86 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 71 trivial. 0 not checked. [2018-11-23 00:57:12,791 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 00:57:12,791 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 00:57:12,797 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:57:12,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:57:12,978 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 00:57:13,068 INFO L134 CoverageAnalysis]: Checked inductivity of 86 backedges. 69 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-23 00:57:13,095 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 00:57:13,095 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-11-23 00:57:13,095 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 00:57:13,096 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 00:57:13,096 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:57:13,096 INFO L87 Difference]: Start difference. First operand 105390 states and 128474 transitions. Second operand 6 states. [2018-11-23 00:57:24,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:57:24,923 INFO L93 Difference]: Finished difference Result 258377 states and 334262 transitions. [2018-11-23 00:57:24,923 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 00:57:24,923 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 256 [2018-11-23 00:57:24,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:57:25,224 INFO L225 Difference]: With dead ends: 258377 [2018-11-23 00:57:25,225 INFO L226 Difference]: Without dead ends: 118160 [2018-11-23 00:57:25,544 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 265 GetRequests, 259 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-11-23 00:57:25,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118160 states. [2018-11-23 00:57:33,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118160 to 118160. [2018-11-23 00:57:33,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118160 states. [2018-11-23 00:57:34,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118160 states to 118160 states and 145204 transitions. [2018-11-23 00:57:34,030 INFO L78 Accepts]: Start accepts. Automaton has 118160 states and 145204 transitions. Word has length 256 [2018-11-23 00:57:34,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:57:34,031 INFO L480 AbstractCegarLoop]: Abstraction has 118160 states and 145204 transitions. [2018-11-23 00:57:34,031 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 00:57:34,031 INFO L276 IsEmpty]: Start isEmpty. Operand 118160 states and 145204 transitions. [2018-11-23 00:57:34,159 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 512 [2018-11-23 00:57:34,160 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:57:34,160 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:57:34,160 INFO L423 AbstractCegarLoop]: === Iteration 41 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:57:34,160 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:57:34,161 INFO L82 PathProgramCache]: Analyzing trace with hash 894928890, now seen corresponding path program 1 times [2018-11-23 00:57:34,161 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:57:34,161 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:57:34,162 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:57:34,162 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:57:34,162 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:57:34,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:57:34,312 INFO L134 CoverageAnalysis]: Checked inductivity of 569 backedges. 39 proven. 26 refuted. 0 times theorem prover too weak. 504 trivial. 0 not checked. [2018-11-23 00:57:34,312 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 00:57:34,312 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 00:57:34,320 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:57:34,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:57:34,501 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 00:57:34,648 INFO L134 CoverageAnalysis]: Checked inductivity of 569 backedges. 330 proven. 0 refuted. 0 times theorem prover too weak. 239 trivial. 0 not checked. [2018-11-23 00:57:34,667 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 00:57:34,668 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [8] total 9 [2018-11-23 00:57:34,669 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 00:57:34,669 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 00:57:34,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-11-23 00:57:34,669 INFO L87 Difference]: Start difference. First operand 118160 states and 145204 transitions. Second operand 9 states. [2018-11-23 00:57:48,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:57:48,489 INFO L93 Difference]: Finished difference Result 278018 states and 351660 transitions. [2018-11-23 00:57:48,489 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-23 00:57:48,489 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 511 [2018-11-23 00:57:48,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:57:48,929 INFO L225 Difference]: With dead ends: 278018 [2018-11-23 00:57:48,930 INFO L226 Difference]: Without dead ends: 136577 [2018-11-23 00:57:49,184 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 534 GetRequests, 515 SyntacticMatches, 2 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=81, Invalid=261, Unknown=0, NotChecked=0, Total=342 [2018-11-23 00:57:49,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136577 states. [2018-11-23 00:57:58,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136577 to 128880. [2018-11-23 00:57:58,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128880 states. [2018-11-23 00:57:59,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128880 states to 128880 states and 154959 transitions. [2018-11-23 00:57:59,040 INFO L78 Accepts]: Start accepts. Automaton has 128880 states and 154959 transitions. Word has length 511 [2018-11-23 00:57:59,040 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:57:59,040 INFO L480 AbstractCegarLoop]: Abstraction has 128880 states and 154959 transitions. [2018-11-23 00:57:59,040 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 00:57:59,040 INFO L276 IsEmpty]: Start isEmpty. Operand 128880 states and 154959 transitions. [2018-11-23 00:57:59,180 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 518 [2018-11-23 00:57:59,180 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:57:59,180 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:57:59,180 INFO L423 AbstractCegarLoop]: === Iteration 42 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:57:59,181 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:57:59,181 INFO L82 PathProgramCache]: Analyzing trace with hash 1942627625, now seen corresponding path program 1 times [2018-11-23 00:57:59,181 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:57:59,181 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:57:59,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:57:59,182 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:57:59,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:57:59,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:57:59,287 INFO L134 CoverageAnalysis]: Checked inductivity of 569 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 533 trivial. 0 not checked. [2018-11-23 00:57:59,287 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:57:59,287 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 00:57:59,288 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 00:57:59,288 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 00:57:59,288 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 00:57:59,288 INFO L87 Difference]: Start difference. First operand 128880 states and 154959 transitions. Second operand 4 states. [2018-11-23 00:58:06,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:58:06,380 INFO L93 Difference]: Finished difference Result 220879 states and 262187 transitions. [2018-11-23 00:58:06,380 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 00:58:06,380 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 517 [2018-11-23 00:58:06,380 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:58:06,601 INFO L225 Difference]: With dead ends: 220879 [2018-11-23 00:58:06,602 INFO L226 Difference]: Without dead ends: 92154 [2018-11-23 00:58:06,772 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 00:58:06,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92154 states. [2018-11-23 00:58:12,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92154 to 89890. [2018-11-23 00:58:12,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89890 states. [2018-11-23 00:58:12,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89890 states to 89890 states and 104987 transitions. [2018-11-23 00:58:12,978 INFO L78 Accepts]: Start accepts. Automaton has 89890 states and 104987 transitions. Word has length 517 [2018-11-23 00:58:12,979 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:58:12,979 INFO L480 AbstractCegarLoop]: Abstraction has 89890 states and 104987 transitions. [2018-11-23 00:58:12,979 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 00:58:12,979 INFO L276 IsEmpty]: Start isEmpty. Operand 89890 states and 104987 transitions. [2018-11-23 00:58:13,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 434 [2018-11-23 00:58:13,061 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:58:13,062 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:58:13,062 INFO L423 AbstractCegarLoop]: === Iteration 43 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:58:13,062 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:58:13,062 INFO L82 PathProgramCache]: Analyzing trace with hash 387919428, now seen corresponding path program 1 times [2018-11-23 00:58:13,062 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:58:13,062 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:58:13,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:58:13,063 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:58:13,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:58:13,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:58:13,356 INFO L134 CoverageAnalysis]: Checked inductivity of 436 backedges. 19 proven. 10 refuted. 0 times theorem prover too weak. 407 trivial. 0 not checked. [2018-11-23 00:58:13,356 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 00:58:13,356 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 00:58:13,365 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:58:13,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:58:13,506 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 00:58:13,578 INFO L134 CoverageAnalysis]: Checked inductivity of 436 backedges. 277 proven. 0 refuted. 0 times theorem prover too weak. 159 trivial. 0 not checked. [2018-11-23 00:58:13,593 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 00:58:13,593 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-11-23 00:58:13,594 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:58:13,594 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:58:13,594 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:58:13,595 INFO L87 Difference]: Start difference. First operand 89890 states and 104987 transitions. Second operand 5 states. [2018-11-23 00:58:36,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:58:36,046 INFO L93 Difference]: Finished difference Result 367935 states and 460710 transitions. [2018-11-23 00:58:36,046 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 00:58:36,046 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 433 [2018-11-23 00:58:36,047 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:58:36,694 INFO L225 Difference]: With dead ends: 367935 [2018-11-23 00:58:36,694 INFO L226 Difference]: Without dead ends: 278200 [2018-11-23 00:58:36,928 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 447 GetRequests, 440 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-23 00:58:37,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278200 states. [2018-11-23 00:58:55,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278200 to 269019. [2018-11-23 00:58:55,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 269019 states. [2018-11-23 00:58:56,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 269019 states to 269019 states and 322257 transitions. [2018-11-23 00:58:56,413 INFO L78 Accepts]: Start accepts. Automaton has 269019 states and 322257 transitions. Word has length 433 [2018-11-23 00:58:56,413 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:58:56,414 INFO L480 AbstractCegarLoop]: Abstraction has 269019 states and 322257 transitions. [2018-11-23 00:58:56,414 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:58:56,414 INFO L276 IsEmpty]: Start isEmpty. Operand 269019 states and 322257 transitions. [2018-11-23 00:58:56,713 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 435 [2018-11-23 00:58:56,713 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:58:56,713 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:58:56,713 INFO L423 AbstractCegarLoop]: === Iteration 44 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:58:56,713 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:58:56,713 INFO L82 PathProgramCache]: Analyzing trace with hash 422412106, now seen corresponding path program 1 times [2018-11-23 00:58:56,713 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:58:56,713 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:58:56,714 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:58:56,714 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:58:56,714 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:58:56,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:58:56,858 INFO L134 CoverageAnalysis]: Checked inductivity of 437 backedges. 26 proven. 30 refuted. 0 times theorem prover too weak. 381 trivial. 0 not checked. [2018-11-23 00:58:56,858 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 00:58:56,858 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 00:58:56,864 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:58:56,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:58:57,001 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 00:58:57,144 INFO L134 CoverageAnalysis]: Checked inductivity of 437 backedges. 260 proven. 0 refuted. 0 times theorem prover too weak. 177 trivial. 0 not checked. [2018-11-23 00:58:57,171 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 00:58:57,171 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2018-11-23 00:58:57,172 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 00:58:57,172 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 00:58:57,172 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:58:57,172 INFO L87 Difference]: Start difference. First operand 269019 states and 322257 transitions. Second operand 6 states. [2018-11-23 00:59:13,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:59:13,727 INFO L93 Difference]: Finished difference Result 438399 states and 534940 transitions. [2018-11-23 00:59:13,727 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 00:59:13,728 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 434 [2018-11-23 00:59:13,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:59:14,117 INFO L225 Difference]: With dead ends: 438399 [2018-11-23 00:59:14,117 INFO L226 Difference]: Without dead ends: 169932 [2018-11-23 00:59:14,575 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 442 GetRequests, 435 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 00:59:14,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169932 states. [2018-11-23 00:59:31,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169932 to 165689. [2018-11-23 00:59:31,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165689 states. [2018-11-23 00:59:32,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165689 states to 165689 states and 189217 transitions. [2018-11-23 00:59:32,226 INFO L78 Accepts]: Start accepts. Automaton has 165689 states and 189217 transitions. Word has length 434 [2018-11-23 00:59:32,226 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:59:32,227 INFO L480 AbstractCegarLoop]: Abstraction has 165689 states and 189217 transitions. [2018-11-23 00:59:32,227 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 00:59:32,227 INFO L276 IsEmpty]: Start isEmpty. Operand 165689 states and 189217 transitions. [2018-11-23 00:59:32,402 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 441 [2018-11-23 00:59:32,402 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:59:32,403 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:59:32,403 INFO L423 AbstractCegarLoop]: === Iteration 45 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:59:32,403 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:59:32,403 INFO L82 PathProgramCache]: Analyzing trace with hash 1315021661, now seen corresponding path program 1 times [2018-11-23 00:59:32,403 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:59:32,403 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:59:32,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:59:32,404 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:59:32,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:59:32,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:59:32,513 INFO L134 CoverageAnalysis]: Checked inductivity of 446 backedges. 1 proven. 54 refuted. 0 times theorem prover too weak. 391 trivial. 0 not checked. [2018-11-23 00:59:32,513 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 00:59:32,513 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 00:59:32,519 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:59:32,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:59:32,634 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 00:59:32,722 INFO L134 CoverageAnalysis]: Checked inductivity of 446 backedges. 93 proven. 0 refuted. 0 times theorem prover too weak. 353 trivial. 0 not checked. [2018-11-23 00:59:32,739 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 00:59:32,739 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-11-23 00:59:32,740 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 00:59:32,740 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:59:32,740 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:59:32,740 INFO L87 Difference]: Start difference. First operand 165689 states and 189217 transitions. Second operand 5 states. [2018-11-23 00:59:44,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:59:44,765 INFO L93 Difference]: Finished difference Result 266837 states and 303044 transitions. [2018-11-23 00:59:44,765 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 00:59:44,765 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 440 [2018-11-23 00:59:44,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 00:59:45,011 INFO L225 Difference]: With dead ends: 266837 [2018-11-23 00:59:45,011 INFO L226 Difference]: Without dead ends: 117928 [2018-11-23 00:59:45,192 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 445 GetRequests, 439 SyntacticMatches, 3 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:59:45,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117928 states. [2018-11-23 00:59:53,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117928 to 117760. [2018-11-23 00:59:53,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117760 states. [2018-11-23 00:59:53,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117760 states to 117760 states and 132430 transitions. [2018-11-23 00:59:53,924 INFO L78 Accepts]: Start accepts. Automaton has 117760 states and 132430 transitions. Word has length 440 [2018-11-23 00:59:53,924 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 00:59:53,924 INFO L480 AbstractCegarLoop]: Abstraction has 117760 states and 132430 transitions. [2018-11-23 00:59:53,924 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 00:59:53,924 INFO L276 IsEmpty]: Start isEmpty. Operand 117760 states and 132430 transitions. [2018-11-23 00:59:54,019 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 540 [2018-11-23 00:59:54,019 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 00:59:54,020 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:59:54,020 INFO L423 AbstractCegarLoop]: === Iteration 46 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 00:59:54,020 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:59:54,020 INFO L82 PathProgramCache]: Analyzing trace with hash -807980157, now seen corresponding path program 1 times [2018-11-23 00:59:54,020 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:59:54,020 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:59:54,021 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:59:54,021 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:59:54,021 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:59:54,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:59:54,148 INFO L134 CoverageAnalysis]: Checked inductivity of 740 backedges. 23 proven. 17 refuted. 0 times theorem prover too weak. 700 trivial. 0 not checked. [2018-11-23 00:59:54,148 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 00:59:54,149 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 00:59:54,156 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:59:54,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:59:54,334 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 00:59:54,719 INFO L134 CoverageAnalysis]: Checked inductivity of 740 backedges. 308 proven. 0 refuted. 0 times theorem prover too weak. 432 trivial. 0 not checked. [2018-11-23 00:59:54,744 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 00:59:54,745 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2018-11-23 00:59:54,746 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 00:59:54,746 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 00:59:54,746 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 00:59:54,746 INFO L87 Difference]: Start difference. First operand 117760 states and 132430 transitions. Second operand 6 states. [2018-11-23 01:00:10,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:00:10,545 INFO L93 Difference]: Finished difference Result 311894 states and 352601 transitions. [2018-11-23 01:00:10,546 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 01:00:10,546 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 539 [2018-11-23 01:00:10,546 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 01:00:10,877 INFO L225 Difference]: With dead ends: 311894 [2018-11-23 01:00:10,877 INFO L226 Difference]: Without dead ends: 163969 [2018-11-23 01:00:11,065 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 551 GetRequests, 545 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2018-11-23 01:00:11,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163969 states. [2018-11-23 01:00:23,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163969 to 160851. [2018-11-23 01:00:23,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160851 states. [2018-11-23 01:00:23,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160851 states to 160851 states and 181497 transitions. [2018-11-23 01:00:23,311 INFO L78 Accepts]: Start accepts. Automaton has 160851 states and 181497 transitions. Word has length 539 [2018-11-23 01:00:23,311 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 01:00:23,311 INFO L480 AbstractCegarLoop]: Abstraction has 160851 states and 181497 transitions. [2018-11-23 01:00:23,311 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 01:00:23,311 INFO L276 IsEmpty]: Start isEmpty. Operand 160851 states and 181497 transitions. [2018-11-23 01:00:23,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 636 [2018-11-23 01:00:23,405 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 01:00:23,406 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:00:23,406 INFO L423 AbstractCegarLoop]: === Iteration 47 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 01:00:23,406 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:00:23,406 INFO L82 PathProgramCache]: Analyzing trace with hash 2032291581, now seen corresponding path program 1 times [2018-11-23 01:00:23,406 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:00:23,406 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:00:23,407 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:00:23,407 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:00:23,407 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:00:23,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:00:23,554 INFO L134 CoverageAnalysis]: Checked inductivity of 1110 backedges. 25 proven. 22 refuted. 0 times theorem prover too weak. 1063 trivial. 0 not checked. [2018-11-23 01:00:23,554 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 01:00:23,554 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 01:00:23,560 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:00:23,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:00:23,714 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 01:00:23,840 INFO L134 CoverageAnalysis]: Checked inductivity of 1110 backedges. 380 proven. 0 refuted. 0 times theorem prover too weak. 730 trivial. 0 not checked. [2018-11-23 01:00:23,856 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 01:00:23,856 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2018-11-23 01:00:23,857 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 01:00:23,857 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 01:00:23,857 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 01:00:23,857 INFO L87 Difference]: Start difference. First operand 160851 states and 181497 transitions. Second operand 6 states. [2018-11-23 01:00:31,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:00:31,127 INFO L93 Difference]: Finished difference Result 224606 states and 253962 transitions. [2018-11-23 01:00:31,128 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 01:00:31,128 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 635 [2018-11-23 01:00:31,128 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 01:00:31,189 INFO L225 Difference]: With dead ends: 224606 [2018-11-23 01:00:31,189 INFO L226 Difference]: Without dead ends: 17262 [2018-11-23 01:00:31,403 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 649 GetRequests, 643 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2018-11-23 01:00:31,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17262 states. [2018-11-23 01:00:32,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17262 to 17257. [2018-11-23 01:00:32,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17257 states. [2018-11-23 01:00:32,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17257 states to 17257 states and 18919 transitions. [2018-11-23 01:00:32,944 INFO L78 Accepts]: Start accepts. Automaton has 17257 states and 18919 transitions. Word has length 635 [2018-11-23 01:00:32,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 01:00:32,944 INFO L480 AbstractCegarLoop]: Abstraction has 17257 states and 18919 transitions. [2018-11-23 01:00:32,944 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 01:00:32,944 INFO L276 IsEmpty]: Start isEmpty. Operand 17257 states and 18919 transitions. [2018-11-23 01:00:32,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 725 [2018-11-23 01:00:32,958 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 01:00:32,958 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:00:32,958 INFO L423 AbstractCegarLoop]: === Iteration 48 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 01:00:32,958 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:00:32,959 INFO L82 PathProgramCache]: Analyzing trace with hash -2115959492, now seen corresponding path program 1 times [2018-11-23 01:00:32,959 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:00:32,959 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:00:32,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:00:32,959 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:00:32,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:00:32,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:00:33,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:00:33,313 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] CALL call ULTIMATE.init(); VAL [|old(~E_1~0)|=34, |old(~E_2~0)|=25, |old(~E_3~0)|=24, |old(~E_4~0)|=8, |old(~E_5~0)|=4, |old(~E_6~0)|=15, |old(~M_E~0)|=14, |old(~m_i~0)|=7, |old(~m_pc~0)|=30, |old(~m_st~0)|=12, |old(~T1_E~0)|=3, |old(~t1_i~0)|=31, |old(~t1_pc~0)|=28, |old(~t1_st~0)|=5, |old(~T2_E~0)|=32, |old(~t2_i~0)|=6, |old(~t2_pc~0)|=27, |old(~t2_st~0)|=10, |old(~T3_E~0)|=23, |old(~t3_i~0)|=35, |old(~t3_pc~0)|=26, |old(~t3_st~0)|=11, |old(~T4_E~0)|=36, |old(~t4_i~0)|=17, |old(~t4_pc~0)|=22, |old(~t4_st~0)|=9, |old(~T5_E~0)|=20, |old(~t5_i~0)|=33, |old(~t5_pc~0)|=18, |old(~t5_st~0)|=19, |old(~T6_E~0)|=13, |old(~t6_i~0)|=29, |old(~t6_pc~0)|=21, |old(~t6_st~0)|=16, ~E_1~0=34, ~E_2~0=25, ~E_3~0=24, ~E_4~0=8, ~E_5~0=4, ~E_6~0=15, ~M_E~0=14, ~m_i~0=7, ~m_pc~0=30, ~m_st~0=12, ~T1_E~0=3, ~t1_i~0=31, ~t1_pc~0=28, ~t1_st~0=5, ~T2_E~0=32, ~t2_i~0=6, ~t2_pc~0=27, ~t2_st~0=10, ~T3_E~0=23, ~t3_i~0=35, ~t3_pc~0=26, ~t3_st~0=11, ~T4_E~0=36, ~t4_i~0=17, ~t4_pc~0=22, ~t4_st~0=9, ~T5_E~0=20, ~t5_i~0=33, ~t5_pc~0=18, ~t5_st~0=19, ~T6_E~0=13, ~t6_i~0=29, ~t6_pc~0=21, ~t6_st~0=16] [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; VAL [|old(~E_1~0)|=34, |old(~E_2~0)|=25, |old(~E_3~0)|=24, |old(~E_4~0)|=8, |old(~E_5~0)|=4, |old(~E_6~0)|=15, |old(~M_E~0)|=14, |old(~m_i~0)|=7, |old(~m_pc~0)|=30, |old(~m_st~0)|=12, |old(~T1_E~0)|=3, |old(~t1_i~0)|=31, |old(~t1_pc~0)|=28, |old(~t1_st~0)|=5, |old(~T2_E~0)|=32, |old(~t2_i~0)|=6, |old(~t2_pc~0)|=27, |old(~t2_st~0)|=10, |old(~T3_E~0)|=23, |old(~t3_i~0)|=35, |old(~t3_pc~0)|=26, |old(~t3_st~0)|=11, |old(~T4_E~0)|=36, |old(~t4_i~0)|=17, |old(~t4_pc~0)|=22, |old(~t4_st~0)|=9, |old(~T5_E~0)|=20, |old(~t5_i~0)|=33, |old(~t5_pc~0)|=18, |old(~t5_st~0)|=19, |old(~T6_E~0)|=13, |old(~t6_i~0)|=29, |old(~t6_pc~0)|=21, |old(~t6_st~0)|=16, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=0, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=34, |old(~E_2~0)|=25, |old(~E_3~0)|=24, |old(~E_4~0)|=8, |old(~E_5~0)|=4, |old(~E_6~0)|=15, |old(~M_E~0)|=14, |old(~m_i~0)|=7, |old(~m_pc~0)|=30, |old(~m_st~0)|=12, |old(~T1_E~0)|=3, |old(~t1_i~0)|=31, |old(~t1_pc~0)|=28, |old(~t1_st~0)|=5, |old(~T2_E~0)|=32, |old(~t2_i~0)|=6, |old(~t2_pc~0)|=27, |old(~t2_st~0)|=10, |old(~T3_E~0)|=23, |old(~t3_i~0)|=35, |old(~t3_pc~0)|=26, |old(~t3_st~0)|=11, |old(~T4_E~0)|=36, |old(~t4_i~0)|=17, |old(~t4_pc~0)|=22, |old(~t4_st~0)|=9, |old(~T5_E~0)|=20, |old(~t5_i~0)|=33, |old(~t5_pc~0)|=18, |old(~t5_st~0)|=19, |old(~T6_E~0)|=13, |old(~t6_i~0)|=29, |old(~t6_pc~0)|=21, |old(~t6_st~0)|=16, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=0, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #977#return; VAL [~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=0, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call #t~ret18 := main(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=0, ~t6_pc~0=0, ~t6_st~0=0] [?] havoc ~__retres1~8; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=0, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call init_model(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=0, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=0, ~t6_pc~0=0, ~t6_st~0=0] [?] ~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #907#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call start_simulation(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] havoc ~kernel_st~0;havoc ~tmp~3;havoc ~tmp___0~1;~kernel_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call update_channels(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #947#return; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call init_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 1 == ~m_i~0;~m_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #949#return; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call fire_delta_events(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 == ~T1_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 == ~T2_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 == ~T3_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 == ~T4_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 == ~T5_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 == ~T6_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 == ~E_5~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 == ~E_6~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #951#return; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0;havoc ~tmp___4~0;havoc ~tmp___5~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call #t~ret8 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~m_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #913#return; VAL [|activate_threads_#t~ret8|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp~1 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call #t~ret9 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~t1_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] ~__retres1~1 := 0; VAL [is_transmit1_triggered_~__retres1~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #915#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___0~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 != ~tmp___0~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call #t~ret10 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~t2_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] ~__retres1~2 := 0; VAL [is_transmit2_triggered_~__retres1~2=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #917#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___1~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 != ~tmp___1~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call #t~ret11 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~t3_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] ~__retres1~3 := 0; VAL [is_transmit3_triggered_~__retres1~3=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #919#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret11|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647;~tmp___2~0 := #t~ret11;havoc #t~ret11; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 != ~tmp___2~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call #t~ret12 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~t4_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] ~__retres1~4 := 0; VAL [is_transmit4_triggered_~__retres1~4=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #921#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret12|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647;~tmp___3~0 := #t~ret12;havoc #t~ret12; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 != ~tmp___3~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call #t~ret13 := is_transmit5_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] havoc ~__retres1~5; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~t5_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] ~__retres1~5 := 0; VAL [is_transmit5_triggered_~__retres1~5=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] #res := ~__retres1~5; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #923#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret13|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume -2147483648 <= #t~ret13 && #t~ret13 <= 2147483647;~tmp___4~0 := #t~ret13;havoc #t~ret13; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 != ~tmp___4~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call #t~ret14 := is_transmit6_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] havoc ~__retres1~6; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~t6_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] ~__retres1~6 := 0; VAL [is_transmit6_triggered_~__retres1~6=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] #res := ~__retres1~6; VAL [is_transmit6_triggered_~__retres1~6=0, |is_transmit6_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [is_transmit6_triggered_~__retres1~6=0, |is_transmit6_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #925#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret14|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume -2147483648 <= #t~ret14 && #t~ret14 <= 2147483647;~tmp___5~0 := #t~ret14;havoc #t~ret14; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 != ~tmp___5~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #953#return; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call reset_delta_events(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~T1_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~T2_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~T3_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~T4_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~T5_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~T6_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~E_5~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(1 == ~E_6~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #955#return; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !false; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] ~kernel_st~0 := 1; VAL [start_simulation_~kernel_st~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call eval(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] havoc ~tmp~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call #t~ret0 := exists_runnable_thread(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] havoc ~__retres1~7; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 == ~m_st~0;~__retres1~7 := 1; VAL [exists_runnable_thread_~__retres1~7=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] #res := ~__retres1~7; VAL [exists_runnable_thread_~__retres1~7=1, |exists_runnable_thread_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [exists_runnable_thread_~__retres1~7=1, |exists_runnable_thread_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #931#return; VAL [|eval_#t~ret0|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647;~tmp~0 := #t~ret0;havoc #t~ret0; VAL [eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 != ~tmp~0; VAL [eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 == ~m_st~0;havoc ~tmp_ndt_1~0;assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647;~tmp_ndt_1~0 := #t~nondet1;havoc #t~nondet1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !(0 != ~tmp_ndt_1~0); VAL [eval_~tmp_ndt_1~0=0, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 == ~t1_st~0;havoc ~tmp_ndt_2~0;assume -2147483648 <= #t~nondet2 && #t~nondet2 <= 2147483647;~tmp_ndt_2~0 := #t~nondet2;havoc #t~nondet2; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 != ~tmp_ndt_2~0;~t1_st~0 := 1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call transmit1(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] ~t1_pc~0 := 1;~t1_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #935#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 == ~t2_st~0;havoc ~tmp_ndt_3~0;assume -2147483648 <= #t~nondet3 && #t~nondet3 <= 2147483647;~tmp_ndt_3~0 := #t~nondet3;havoc #t~nondet3; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 != ~tmp_ndt_3~0;~t2_st~0 := 1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call transmit2(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] ~t2_pc~0 := 1;~t2_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #937#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 == ~t3_st~0;havoc ~tmp_ndt_4~0;assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647;~tmp_ndt_4~0 := #t~nondet4;havoc #t~nondet4; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 != ~tmp_ndt_4~0;~t3_st~0 := 1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call transmit3(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] ~t3_pc~0 := 1;~t3_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #939#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 == ~t4_st~0;havoc ~tmp_ndt_5~0;assume -2147483648 <= #t~nondet5 && #t~nondet5 <= 2147483647;~tmp_ndt_5~0 := #t~nondet5;havoc #t~nondet5; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 != ~tmp_ndt_5~0;~t4_st~0 := 1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call transmit4(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] ~t4_pc~0 := 1;~t4_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #941#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 == ~t5_st~0;havoc ~tmp_ndt_6~0;assume -2147483648 <= #t~nondet6 && #t~nondet6 <= 2147483647;~tmp_ndt_6~0 := #t~nondet6;havoc #t~nondet6; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 != ~tmp_ndt_6~0;~t5_st~0 := 1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] CALL call transmit5(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=1, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 == ~t5_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=1, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=1, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=0, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] ~t5_pc~0 := 1;~t5_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=1, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=1, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] RET #943#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 == ~t6_st~0;havoc ~tmp_ndt_7~0;assume -2147483648 <= #t~nondet7 && #t~nondet7 <= 2147483647;~tmp_ndt_7~0 := #t~nondet7;havoc #t~nondet7; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=0] [?] assume 0 != ~tmp_ndt_7~0;~t6_st~0 := 1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=1] [?] CALL call transmit6(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=1] [?] assume 0 == ~t6_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=1] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=0, ~t6_st~0=1] [?] ~t6_pc~0 := 1;~t6_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #945#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !false; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret0 := exists_runnable_thread(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~7; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 == ~m_st~0;~__retres1~7 := 1; VAL [exists_runnable_thread_~__retres1~7=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~7; VAL [exists_runnable_thread_~__retres1~7=1, |exists_runnable_thread_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [exists_runnable_thread_~__retres1~7=1, |exists_runnable_thread_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #931#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |eval_#t~ret0|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647;~tmp~0 := #t~ret0;havoc #t~ret0; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 != ~tmp~0; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 == ~m_st~0;havoc ~tmp_ndt_1~0;assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647;~tmp_ndt_1~0 := #t~nondet1;havoc #t~nondet1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 != ~tmp_ndt_1~0;~m_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call master(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 == ~m_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~E_1~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call immediate_notify(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0;havoc ~tmp___4~0;havoc ~tmp___5~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret8 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~m_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #913#return; VAL [|activate_threads_#t~ret8|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp~1 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret9 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~E_1~0;~__retres1~1 := 1; VAL [is_transmit1_triggered_~__retres1~1=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=1, |is_transmit1_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=1, |is_transmit1_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #915#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___0~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 != ~tmp___0~0;~t1_st~0 := 0; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret10 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~2 := 0; VAL [is_transmit2_triggered_~__retres1~2=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #917#return; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___1~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___1~0); VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret11 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~3 := 0; VAL [is_transmit3_triggered_~__retres1~3=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #919#return; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret11|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647;~tmp___2~0 := #t~ret11;havoc #t~ret11; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___2~0); VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret12 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~4 := 0; VAL [is_transmit4_triggered_~__retres1~4=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #921#return; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret12|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647;~tmp___3~0 := #t~ret12;havoc #t~ret12; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___3~0); VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret13 := is_transmit5_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~5; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t5_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_5~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~5 := 0; VAL [is_transmit5_triggered_~__retres1~5=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~5; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #923#return; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret13|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret13 && #t~ret13 <= 2147483647;~tmp___4~0 := #t~ret13;havoc #t~ret13; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___4~0); VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret14 := is_transmit6_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~6; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t6_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_6~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~6 := 0; VAL [is_transmit6_triggered_~__retres1~6=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~6; VAL [is_transmit6_triggered_~__retres1~6=0, |is_transmit6_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit6_triggered_~__retres1~6=0, |is_transmit6_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #925#return; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret14|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret14 && #t~ret14 <= 2147483647;~tmp___5~0 := #t~ret14;havoc #t~ret14; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___5~0); VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #927#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #929#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~E_1~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~m_pc~0 := 1;~m_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #933#return; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 == ~t1_st~0;havoc ~tmp_ndt_2~0;assume -2147483648 <= #t~nondet2 && #t~nondet2 <= 2147483647;~tmp_ndt_2~0 := #t~nondet2;havoc #t~nondet2; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 != ~tmp_ndt_2~0;~t1_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call transmit1(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 == ~t1_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~E_2~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call immediate_notify(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0;havoc ~tmp___4~0;havoc ~tmp___5~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret8 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~m_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #913#return; VAL [|activate_threads_#t~ret8|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp~1 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret9 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~1 := 0; VAL [is_transmit1_triggered_~__retres1~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #915#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___0~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___0~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret10 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~E_2~0;~__retres1~2 := 1; VAL [is_transmit2_triggered_~__retres1~2=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=1, |is_transmit2_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=1, |is_transmit2_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #917#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___1~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 != ~tmp___1~0;~t2_st~0 := 0; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret11 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~3 := 0; VAL [is_transmit3_triggered_~__retres1~3=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #919#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp~1=0, |activate_threads_#t~ret11|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647;~tmp___2~0 := #t~ret11;havoc #t~ret11; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___2~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret12 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~4 := 0; VAL [is_transmit4_triggered_~__retres1~4=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #921#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret12|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647;~tmp___3~0 := #t~ret12;havoc #t~ret12; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___3~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret13 := is_transmit5_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~5; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t5_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_5~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~5 := 0; VAL [is_transmit5_triggered_~__retres1~5=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~5; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #923#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret13|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret13 && #t~ret13 <= 2147483647;~tmp___4~0 := #t~ret13;havoc #t~ret13; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___4~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret14 := is_transmit6_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~6; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t6_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_6~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~6 := 0; VAL [is_transmit6_triggered_~__retres1~6=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~6; VAL [is_transmit6_triggered_~__retres1~6=0, |is_transmit6_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit6_triggered_~__retres1~6=0, |is_transmit6_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #925#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret14|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret14 && #t~ret14 <= 2147483647;~tmp___5~0 := #t~ret14;havoc #t~ret14; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___5~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #927#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #895#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~E_2~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~t1_pc~0 := 1;~t1_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #935#return; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 == ~t2_st~0;havoc ~tmp_ndt_3~0;assume -2147483648 <= #t~nondet3 && #t~nondet3 <= 2147483647;~tmp_ndt_3~0 := #t~nondet3;havoc #t~nondet3; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 != ~tmp_ndt_3~0;~t2_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call transmit2(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 == ~t2_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~E_3~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call immediate_notify(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0;havoc ~tmp___4~0;havoc ~tmp___5~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret8 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~m_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #913#return; VAL [|activate_threads_#t~ret8|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp~1 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret9 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~1 := 0; VAL [is_transmit1_triggered_~__retres1~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #915#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___0~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___0~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret10 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~2 := 0; VAL [is_transmit2_triggered_~__retres1~2=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #917#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___1~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___1~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret11 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~E_3~0;~__retres1~3 := 1; VAL [is_transmit3_triggered_~__retres1~3=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=1, |is_transmit3_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=1, |is_transmit3_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #919#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret11|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647;~tmp___2~0 := #t~ret11;havoc #t~ret11; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 != ~tmp___2~0;~t3_st~0 := 0; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret12 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~4 := 0; VAL [is_transmit4_triggered_~__retres1~4=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #921#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp~1=0, |activate_threads_#t~ret12|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647;~tmp___3~0 := #t~ret12;havoc #t~ret12; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___3~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret13 := is_transmit5_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~5; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t5_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_5~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~5 := 0; VAL [is_transmit5_triggered_~__retres1~5=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~5; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #923#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret13|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret13 && #t~ret13 <= 2147483647;~tmp___4~0 := #t~ret13;havoc #t~ret13; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___4~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret14 := is_transmit6_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~6; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t6_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_6~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~6 := 0; VAL [is_transmit6_triggered_~__retres1~6=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~6; VAL [is_transmit6_triggered_~__retres1~6=0, |is_transmit6_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit6_triggered_~__retres1~6=0, |is_transmit6_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #925#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret14|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret14 && #t~ret14 <= 2147483647;~tmp___5~0 := #t~ret14;havoc #t~ret14; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___5~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=0, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #927#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #899#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~E_3~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~t2_pc~0 := 1;~t2_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #937#return; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 == ~t3_st~0;havoc ~tmp_ndt_4~0;assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647;~tmp_ndt_4~0 := #t~nondet4;havoc #t~nondet4; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 != ~tmp_ndt_4~0;~t3_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call transmit3(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 == ~t3_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~E_4~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call immediate_notify(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0;havoc ~tmp___4~0;havoc ~tmp___5~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret8 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~m_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #913#return; VAL [|activate_threads_#t~ret8|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp~1 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret9 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~1 := 0; VAL [is_transmit1_triggered_~__retres1~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #915#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___0~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___0~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret10 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~2 := 0; VAL [is_transmit2_triggered_~__retres1~2=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #917#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___1~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___1~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret11 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~3 := 0; VAL [is_transmit3_triggered_~__retres1~3=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #919#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret11|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647;~tmp___2~0 := #t~ret11;havoc #t~ret11; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___2~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret12 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~E_4~0;~__retres1~4 := 1; VAL [is_transmit4_triggered_~__retres1~4=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=1, |is_transmit4_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=1, |is_transmit4_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #921#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret12|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647;~tmp___3~0 := #t~ret12;havoc #t~ret12; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 != ~tmp___3~0;~t4_st~0 := 0; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret13 := is_transmit5_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~5; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t5_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_5~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~5 := 0; VAL [is_transmit5_triggered_~__retres1~5=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~5; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit5_triggered_~__retres1~5=0, |is_transmit5_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #923#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp~1=0, |activate_threads_#t~ret13|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret13 && #t~ret13 <= 2147483647;~tmp___4~0 := #t~ret13;havoc #t~ret13; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___4~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret14 := is_transmit6_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~6; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t6_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_6~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~6 := 0; VAL [is_transmit6_triggered_~__retres1~6=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~6; VAL [is_transmit6_triggered_~__retres1~6=0, |is_transmit6_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit6_triggered_~__retres1~6=0, |is_transmit6_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #925#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp___4~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret14|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret14 && #t~ret14 <= 2147483647;~tmp___5~0 := #t~ret14;havoc #t~ret14; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp___4~0=0, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___5~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp___4~0=0, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp___4~0=0, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #927#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #897#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~E_4~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~t3_pc~0 := 1;~t3_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #939#return; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 == ~t4_st~0;havoc ~tmp_ndt_5~0;assume -2147483648 <= #t~nondet5 && #t~nondet5 <= 2147483647;~tmp_ndt_5~0 := #t~nondet5;havoc #t~nondet5; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 != ~tmp_ndt_5~0;~t4_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call transmit4(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 == ~t4_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~E_5~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call immediate_notify(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0;havoc ~tmp___4~0;havoc ~tmp___5~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret8 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~m_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #913#return; VAL [|activate_threads_#t~ret8|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp~1 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret9 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~1 := 0; VAL [is_transmit1_triggered_~__retres1~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #915#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___0~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___0~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret10 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~2 := 0; VAL [is_transmit2_triggered_~__retres1~2=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #917#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___1~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___1~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret11 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~3 := 0; VAL [is_transmit3_triggered_~__retres1~3=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #919#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret11|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret11 && #t~ret11 <= 2147483647;~tmp___2~0 := #t~ret11;havoc #t~ret11; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___2~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret12 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~4 := 0; VAL [is_transmit4_triggered_~__retres1~4=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #921#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret12|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret12 && #t~ret12 <= 2147483647;~tmp___3~0 := #t~ret12;havoc #t~ret12; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___3~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret13 := is_transmit5_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~5; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t5_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~E_5~0;~__retres1~5 := 1; VAL [is_transmit5_triggered_~__retres1~5=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~5; VAL [is_transmit5_triggered_~__retres1~5=1, |is_transmit5_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit5_triggered_~__retres1~5=1, |is_transmit5_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #923#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret13|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret13 && #t~ret13 <= 2147483647;~tmp___4~0 := #t~ret13;havoc #t~ret13; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 != ~tmp___4~0;~t5_st~0 := 0; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret14 := is_transmit6_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~__retres1~6; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t6_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(1 == ~E_6~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~__retres1~6 := 0; VAL [is_transmit6_triggered_~__retres1~6=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] #res := ~__retres1~6; VAL [is_transmit6_triggered_~__retres1~6=0, |is_transmit6_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [is_transmit6_triggered_~__retres1~6=0, |is_transmit6_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #925#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=1, activate_threads_~tmp~1=0, |activate_threads_#t~ret14|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume -2147483648 <= #t~ret14 && #t~ret14 <= 2147483647;~tmp___5~0 := #t~ret14;havoc #t~ret14; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=1, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 != ~tmp___5~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=1, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp___4~0=1, activate_threads_~tmp___5~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #927#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #903#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=1, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~E_5~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~t4_pc~0 := 1;~t4_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=2, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] RET #941#return; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 == ~t5_st~0;havoc ~tmp_ndt_6~0;assume -2147483648 <= #t~nondet6 && #t~nondet6 <= 2147483647;~tmp_ndt_6~0 := #t~nondet6;havoc #t~nondet6; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=0, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 0 != ~tmp_ndt_6~0;~t5_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp_ndt_6~0=1, eval_~tmp_ndt_7~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=0, |old(~t5_st~0)|=0, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call transmit5(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=1, |old(~t5_st~0)|=1, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume !(0 == ~t5_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=1, |old(~t5_st~0)|=1, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] assume 1 == ~t5_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=1, |old(~t5_st~0)|=1, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] ~E_6~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=1, |old(~t5_st~0)|=1, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call immediate_notify(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=1, |old(~t5_st~0)|=1, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=1, |old(~t5_st~0)|=1, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0;havoc ~tmp___4~0;havoc ~tmp___5~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=1, |old(~t5_st~0)|=1, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [?] CALL call #t~ret8 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~E_5~0)|=2, |old(~E_6~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, |old(~T5_E~0)|=2, |old(~t5_i~0)|=0, |old(~t5_pc~0)|=1, |old(~t5_st~0)|=1, |old(~T6_E~0)|=2, |old(~t6_i~0)|=0, |old(~t6_pc~0)|=0, |old(~t6_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] WARNING: YOUR LOGFILE WAS TOO LONG, SOME LINES IN THE MIDDLE WERE REMOVED. [L861] CALL call #t~ret14 := is_transmit6_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=0, old(~t6_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [L421] havoc ~__retres1~6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=0, old(~t6_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [L424] COND TRUE 1 == ~t6_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=0, old(~t6_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [L425] COND TRUE 1 == ~E_6~0 [L426] ~__retres1~6 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=0, old(~t6_st~0)=2, ~__retres1~6=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [L436] #res := ~__retres1~6; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=0, old(~t6_st~0)=2, ~__retres1~6=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2] [L861] RET call #t~ret14 := is_transmit6_triggered(); VAL [#t~ret14=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=0, old(~t6_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp___4~0=0, ~tmp~1=0] [L861] assume -2147483648 <= #t~ret14 && #t~ret14 <= 2147483647; [L861] ~tmp___5~0 := #t~ret14; [L861] havoc #t~ret14; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=0, old(~t6_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp___4~0=0, ~tmp___5~0=1, ~tmp~1=0] [L863-L867] COND TRUE 0 != ~tmp___5~0 [L864] ~t6_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=0, old(~t6_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp___4~0=0, ~tmp___5~0=1, ~tmp~1=0] [L877] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=0, old(~t6_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=0] [L262] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=0, old(~t6_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=0] [L263] ~E_6~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=0, old(~t6_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=0] [L253-L265] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=0, old(~t6_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=1, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=0] [L255] ~t5_pc~0 := 1; [L256] ~t5_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=1, old(~t5_st~0)=1, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=0, old(~t6_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=0] [L627] RET call transmit5(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=0, old(~t6_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=0, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp_ndt_7~0=1, ~tmp~0=1] [L635] COND TRUE 0 == ~t6_st~0 [L636] havoc ~tmp_ndt_7~0; [L637] assume -2147483648 <= #t~nondet7 && #t~nondet7 <= 2147483647; [L637] ~tmp_ndt_7~0 := #t~nondet7; [L637] havoc #t~nondet7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=0, old(~t6_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=0, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp_ndt_7~0=1, ~tmp~0=1] [L638-L645] COND TRUE 0 != ~tmp_ndt_7~0 [L640] ~t6_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=0, old(~t6_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=1, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp_ndt_6~0=1, ~tmp_ndt_7~0=1, ~tmp~0=1] [L641] CALL call transmit6(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=1, old(~t6_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=1] [L277] COND FALSE !(0 == ~t6_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=1, old(~t6_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=1] [L280] COND TRUE 1 == ~t6_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=1, old(~t6_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=1] [L296] CALL call error(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=1, old(~t6_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=1] [L11] assert false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~E_5~0)=2, old(~E_6~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, old(~T5_E~0)=2, old(~t5_i~0)=0, old(~t5_pc~0)=0, old(~t5_st~0)=0, old(~T6_E~0)=2, old(~t6_i~0)=0, old(~t6_pc~0)=1, old(~t6_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~E_5~0=2, ~E_6~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~T5_E~0=2, ~t5_i~0=1, ~t5_pc~0=1, ~t5_st~0=2, ~T6_E~0=2, ~t6_i~0=1, ~t6_pc~0=1, ~t6_st~0=1] [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int t6_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int t2_i ; [L32] int t3_i ; [L33] int t4_i ; [L34] int t5_i ; [L35] int t6_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int T4_E = 2; [L41] int T5_E = 2; [L42] int T6_E = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; VAL [\old(E_1)=34, \old(E_2)=25, \old(E_3)=24, \old(E_4)=8, \old(E_5)=4, \old(E_6)=15, \old(M_E)=14, \old(m_i)=7, \old(m_pc)=30, \old(m_st)=12, \old(T1_E)=3, \old(t1_i)=31, \old(t1_pc)=28, \old(t1_st)=5, \old(T2_E)=32, \old(t2_i)=6, \old(t2_pc)=27, \old(t2_st)=10, \old(T3_E)=23, \old(t3_i)=35, \old(t3_pc)=26, \old(t3_st)=11, \old(T4_E)=36, \old(t4_i)=17, \old(t4_pc)=22, \old(t4_st)=9, \old(T5_E)=20, \old(t5_i)=33, \old(t5_pc)=18, \old(t5_st)=19, \old(T6_E)=13, \old(t6_i)=29, \old(t6_pc)=21, \old(t6_st)=16, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, T6_E=2, t6_i=0, t6_pc=0, t6_st=0] [L1059] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, T6_E=2, t6_i=0, t6_pc=0, t6_st=0] [L1063] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, T6_E=2, t6_i=0, t6_pc=0, t6_st=0] [L969] m_i = 1 [L970] t1_i = 1 [L971] t2_i = 1 [L972] t3_i = 1 [L973] t4_i = 1 [L974] t5_i = 1 [L975] t6_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1063] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1064] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1000] int kernel_st ; [L1001] int tmp ; [L1002] int tmp___0 ; [L1006] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1007] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1008] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L451] COND TRUE m_i == 1 [L452] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L456] COND TRUE t1_i == 1 [L457] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L461] COND TRUE t2_i == 1 [L462] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L466] COND TRUE t3_i == 1 [L467] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L471] COND TRUE t4_i == 1 [L472] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L476] COND TRUE t5_i == 1 [L477] t5_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L481] COND TRUE t6_i == 1 [L482] t6_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1008] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1009] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L660] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L665] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L670] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L675] COND FALSE !(T3_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L680] COND FALSE !(T4_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L685] COND FALSE !(T5_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L690] COND FALSE !(T6_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L695] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L700] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L705] COND FALSE !(E_3 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L710] COND FALSE !(E_4 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L715] COND FALSE !(E_5 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L720] COND FALSE !(E_6 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1009] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1010] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L310] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L329] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L348] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L367] COND FALSE !(t3_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L386] COND FALSE !(t4_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L405] COND FALSE !(t5_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L424] COND FALSE !(t6_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L1010] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1011] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L733] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L738] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L743] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L748] COND FALSE !(T3_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L753] COND FALSE !(T4_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L758] COND FALSE !(T5_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L763] COND FALSE !(T6_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L768] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L773] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L778] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L783] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L788] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L793] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1011] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1014] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1017] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1018] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L537] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L541] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L544] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L491] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L494] COND TRUE m_st == 0 [L495] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L532] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L544] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L544] tmp = exists_runnable_thread() [L546] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1] [L551] COND TRUE m_st == 0 [L552] int tmp_ndt_1; [L553] tmp_ndt_1 = __VERIFIER_nondet_int() [L554] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0] [L565] COND TRUE t1_st == 0 [L566] int tmp_ndt_2; [L567] tmp_ndt_2 = __VERIFIER_nondet_int() [L568] COND TRUE \read(tmp_ndt_2) [L570] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L571] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L102] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L113] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L115] t1_pc = 1 [L116] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L571] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L579] COND TRUE t2_st == 0 [L580] int tmp_ndt_3; [L581] tmp_ndt_3 = __VERIFIER_nondet_int() [L582] COND TRUE \read(tmp_ndt_3) [L584] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L585] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L137] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L148] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L150] t2_pc = 1 [L151] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L585] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L593] COND TRUE t3_st == 0 [L594] int tmp_ndt_4; [L595] tmp_ndt_4 = __VERIFIER_nondet_int() [L596] COND TRUE \read(tmp_ndt_4) [L598] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L599] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L172] COND TRUE t3_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L183] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L185] t3_pc = 1 [L186] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L599] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L607] COND TRUE t4_st == 0 [L608] int tmp_ndt_5; [L609] tmp_ndt_5 = __VERIFIER_nondet_int() [L610] COND TRUE \read(tmp_ndt_5) [L612] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L613] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L207] COND TRUE t4_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L218] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L220] t4_pc = 1 [L221] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L613] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L621] COND TRUE t5_st == 0 [L622] int tmp_ndt_6; [L623] tmp_ndt_6 = __VERIFIER_nondet_int() [L624] COND TRUE \read(tmp_ndt_6) [L626] t5_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L627] CALL transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L242] COND TRUE t5_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L253] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L255] t5_pc = 1 [L256] t5_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L627] RET transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L635] COND TRUE t6_st == 0 [L636] int tmp_ndt_7; [L637] tmp_ndt_7 = __VERIFIER_nondet_int() [L638] COND TRUE \read(tmp_ndt_7) [L640] t6_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L641] CALL transmit6() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=1] [L277] COND TRUE t6_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=1] [L288] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=1] [L290] t6_pc = 1 [L291] t6_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L641] RET transmit6() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L541] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L544] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L491] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L494] COND TRUE m_st == 0 [L495] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L532] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L544] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L544] tmp = exists_runnable_thread() [L546] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L551] COND TRUE m_st == 0 [L552] int tmp_ndt_1; [L553] tmp_ndt_1 = __VERIFIER_nondet_int() [L554] COND TRUE \read(tmp_ndt_1) [L556] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L557] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L61] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L72] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L75] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L76] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND TRUE E_1 == 1 [L331] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND TRUE \read(tmp___0) [L824] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L76] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L77] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L80] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L82] m_pc = 1 [L83] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L557] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L565] COND TRUE t1_st == 0 [L566] int tmp_ndt_2; [L567] tmp_ndt_2 = __VERIFIER_nondet_int() [L568] COND TRUE \read(tmp_ndt_2) [L570] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L571] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L102] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L105] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L121] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L122] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L311] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND TRUE E_2 == 1 [L350] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND TRUE \read(tmp___1) [L832] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L122] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L123] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L113] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L115] t1_pc = 1 [L116] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L571] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L579] COND TRUE t2_st == 0 [L580] int tmp_ndt_3; [L581] tmp_ndt_3 = __VERIFIER_nondet_int() [L582] COND TRUE \read(tmp_ndt_3) [L584] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L585] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L137] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L140] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L156] E_3 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L157] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L311] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND TRUE E_3 == 1 [L369] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit3_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND TRUE \read(tmp___2) [L840] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0, tmp___4=0, tmp___5=0] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L157] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L158] E_3 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L148] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L150] t2_pc = 1 [L151] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L585] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L593] COND TRUE t3_st == 0 [L594] int tmp_ndt_4; [L595] tmp_ndt_4 = __VERIFIER_nondet_int() [L596] COND TRUE \read(tmp_ndt_4) [L598] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L599] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L172] COND FALSE !(t3_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L175] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L191] E_4 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L192] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L311] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND TRUE E_4 == 1 [L388] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit4_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND TRUE \read(tmp___3) [L848] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1, tmp___4=0, tmp___5=0] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L192] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L193] E_4 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L183] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L185] t3_pc = 1 [L186] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L599] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L607] COND TRUE t4_st == 0 [L608] int tmp_ndt_5; [L609] tmp_ndt_5 = __VERIFIER_nondet_int() [L610] COND TRUE \read(tmp_ndt_5) [L612] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L613] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L207] COND FALSE !(t4_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L210] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L226] E_5 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L227] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L311] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND TRUE E_5 == 1 [L407] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit5_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND TRUE \read(tmp___4) [L856] t5_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=1] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=1] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=1, tmp___5=0] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L227] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L228] E_5 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L218] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L220] t4_pc = 1 [L221] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L613] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L621] COND TRUE t5_st == 0 [L622] int tmp_ndt_6; [L623] tmp_ndt_6 = __VERIFIER_nondet_int() [L624] COND TRUE \read(tmp_ndt_6) [L626] t5_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L627] CALL transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L242] COND FALSE !(t5_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L245] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L261] E_6 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L262] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L311] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND TRUE E_6 == 1 [L426] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit6_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND TRUE \read(tmp___5) [L864] t6_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=1] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=0] [L262] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=0] [L263] E_6 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=0] [L253] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=0] [L255] t5_pc = 1 [L256] t5_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=0] [L627] RET transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L635] COND TRUE t6_st == 0 [L636] int tmp_ndt_7; [L637] tmp_ndt_7 = __VERIFIER_nondet_int() [L638] COND TRUE \read(tmp_ndt_7) [L640] t6_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L641] CALL transmit6() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=1, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1] [L277] COND FALSE !(t6_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=1, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1] [L280] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=1, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1] [L296] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=1, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=1, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1] ----- [2018-11-23 01:04:21,909 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_6d7d3a13-c8e5-49b9-8928-f1fa2abbca4f/bin-2019/uautomizer/witness.graphml [2018-11-23 01:04:21,909 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 01:04:21,910 INFO L168 Benchmark]: Toolchain (without parser) took 494424.86 ms. Allocated memory was 1.0 GB in the beginning and 7.6 GB in the end (delta: 6.6 GB). Free memory was 959.3 MB in the beginning and 490.4 MB in the end (delta: 468.9 MB). Peak memory consumption was 7.1 GB. Max. memory is 11.5 GB. [2018-11-23 01:04:21,911 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 01:04:21,911 INFO L168 Benchmark]: CACSL2BoogieTranslator took 238.89 ms. Allocated memory is still 1.0 GB. Free memory was 959.3 MB in the beginning and 937.8 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. [2018-11-23 01:04:21,911 INFO L168 Benchmark]: Boogie Procedure Inliner took 65.44 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 159.4 MB). Free memory was 937.8 MB in the beginning and 1.2 GB in the end (delta: -215.8 MB). Peak memory consumption was 15.0 MB. Max. memory is 11.5 GB. [2018-11-23 01:04:21,912 INFO L168 Benchmark]: Boogie Preprocessor took 40.75 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 3.4 MB). Peak memory consumption was 3.4 MB. Max. memory is 11.5 GB. [2018-11-23 01:04:21,912 INFO L168 Benchmark]: RCFGBuilder took 637.64 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 67.6 MB). Peak memory consumption was 67.6 MB. Max. memory is 11.5 GB. [2018-11-23 01:04:21,912 INFO L168 Benchmark]: TraceAbstraction took 321922.17 ms. Allocated memory was 1.2 GB in the beginning and 7.6 GB in the end (delta: 6.4 GB). Free memory was 1.1 GB in the beginning and 1.4 GB in the end (delta: -357.7 MB). Peak memory consumption was 6.1 GB. Max. memory is 11.5 GB. [2018-11-23 01:04:21,983 INFO L168 Benchmark]: Witness Printer took 171516.47 ms. Allocated memory is still 7.6 GB. Free memory was 1.4 GB in the beginning and 490.4 MB in the end (delta: 949.9 MB). Peak memory consumption was 949.9 MB. Max. memory is 11.5 GB. [2018-11-23 01:04:21,985 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 238.89 ms. Allocated memory is still 1.0 GB. Free memory was 959.3 MB in the beginning and 937.8 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 65.44 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 159.4 MB). Free memory was 937.8 MB in the beginning and 1.2 GB in the end (delta: -215.8 MB). Peak memory consumption was 15.0 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 40.75 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 3.4 MB). Peak memory consumption was 3.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 637.64 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 67.6 MB). Peak memory consumption was 67.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 321922.17 ms. Allocated memory was 1.2 GB in the beginning and 7.6 GB in the end (delta: 6.4 GB). Free memory was 1.1 GB in the beginning and 1.4 GB in the end (delta: -357.7 MB). Peak memory consumption was 6.1 GB. Max. memory is 11.5 GB. * Witness Printer took 171516.47 ms. Allocated memory is still 7.6 GB. Free memory was 1.4 GB in the beginning and 490.4 MB in the end (delta: 949.9 MB). Peak memory consumption was 949.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int t6_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int t2_i ; [L32] int t3_i ; [L33] int t4_i ; [L34] int t5_i ; [L35] int t6_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int T4_E = 2; [L41] int T5_E = 2; [L42] int T6_E = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; VAL [\old(E_1)=34, \old(E_2)=25, \old(E_3)=24, \old(E_4)=8, \old(E_5)=4, \old(E_6)=15, \old(M_E)=14, \old(m_i)=7, \old(m_pc)=30, \old(m_st)=12, \old(T1_E)=3, \old(t1_i)=31, \old(t1_pc)=28, \old(t1_st)=5, \old(T2_E)=32, \old(t2_i)=6, \old(t2_pc)=27, \old(t2_st)=10, \old(T3_E)=23, \old(t3_i)=35, \old(t3_pc)=26, \old(t3_st)=11, \old(T4_E)=36, \old(t4_i)=17, \old(t4_pc)=22, \old(t4_st)=9, \old(T5_E)=20, \old(t5_i)=33, \old(t5_pc)=18, \old(t5_st)=19, \old(T6_E)=13, \old(t6_i)=29, \old(t6_pc)=21, \old(t6_st)=16, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, T6_E=2, t6_i=0, t6_pc=0, t6_st=0] [L1059] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, T6_E=2, t6_i=0, t6_pc=0, t6_st=0] [L1063] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, T6_E=2, t6_i=0, t6_pc=0, t6_st=0] [L969] m_i = 1 [L970] t1_i = 1 [L971] t2_i = 1 [L972] t3_i = 1 [L973] t4_i = 1 [L974] t5_i = 1 [L975] t6_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1063] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1064] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1000] int kernel_st ; [L1001] int tmp ; [L1002] int tmp___0 ; [L1006] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1007] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1008] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L451] COND TRUE m_i == 1 [L452] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L456] COND TRUE t1_i == 1 [L457] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L461] COND TRUE t2_i == 1 [L462] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L466] COND TRUE t3_i == 1 [L467] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L471] COND TRUE t4_i == 1 [L472] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L476] COND TRUE t5_i == 1 [L477] t5_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L481] COND TRUE t6_i == 1 [L482] t6_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1008] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1009] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L660] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L665] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L670] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L675] COND FALSE !(T3_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L680] COND FALSE !(T4_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L685] COND FALSE !(T5_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L690] COND FALSE !(T6_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L695] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L700] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L705] COND FALSE !(E_3 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L710] COND FALSE !(E_4 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L715] COND FALSE !(E_5 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L720] COND FALSE !(E_6 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1009] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1010] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L310] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L329] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L348] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L367] COND FALSE !(t3_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L386] COND FALSE !(t4_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L405] COND FALSE !(t5_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L424] COND FALSE !(t6_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L1010] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1011] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L733] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L738] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L743] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L748] COND FALSE !(T3_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L753] COND FALSE !(T4_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L758] COND FALSE !(T5_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L763] COND FALSE !(T6_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L768] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L773] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L778] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L783] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L788] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L793] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1011] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1014] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1017] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1018] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L537] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L541] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L544] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L491] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L494] COND TRUE m_st == 0 [L495] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L532] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L544] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L544] tmp = exists_runnable_thread() [L546] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1] [L551] COND TRUE m_st == 0 [L552] int tmp_ndt_1; [L553] tmp_ndt_1 = __VERIFIER_nondet_int() [L554] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0] [L565] COND TRUE t1_st == 0 [L566] int tmp_ndt_2; [L567] tmp_ndt_2 = __VERIFIER_nondet_int() [L568] COND TRUE \read(tmp_ndt_2) [L570] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L571] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L102] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L113] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L115] t1_pc = 1 [L116] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L571] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L579] COND TRUE t2_st == 0 [L580] int tmp_ndt_3; [L581] tmp_ndt_3 = __VERIFIER_nondet_int() [L582] COND TRUE \read(tmp_ndt_3) [L584] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L585] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L137] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L148] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L150] t2_pc = 1 [L151] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L585] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L593] COND TRUE t3_st == 0 [L594] int tmp_ndt_4; [L595] tmp_ndt_4 = __VERIFIER_nondet_int() [L596] COND TRUE \read(tmp_ndt_4) [L598] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L599] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L172] COND TRUE t3_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L183] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L185] t3_pc = 1 [L186] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L599] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L607] COND TRUE t4_st == 0 [L608] int tmp_ndt_5; [L609] tmp_ndt_5 = __VERIFIER_nondet_int() [L610] COND TRUE \read(tmp_ndt_5) [L612] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L613] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L207] COND TRUE t4_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L218] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L220] t4_pc = 1 [L221] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L613] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L621] COND TRUE t5_st == 0 [L622] int tmp_ndt_6; [L623] tmp_ndt_6 = __VERIFIER_nondet_int() [L624] COND TRUE \read(tmp_ndt_6) [L626] t5_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L627] CALL transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L242] COND TRUE t5_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L253] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L255] t5_pc = 1 [L256] t5_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L627] RET transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L635] COND TRUE t6_st == 0 [L636] int tmp_ndt_7; [L637] tmp_ndt_7 = __VERIFIER_nondet_int() [L638] COND TRUE \read(tmp_ndt_7) [L640] t6_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L641] CALL transmit6() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=1] [L277] COND TRUE t6_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=1] [L288] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=1] [L290] t6_pc = 1 [L291] t6_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L641] RET transmit6() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L541] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L544] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L491] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L494] COND TRUE m_st == 0 [L495] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L532] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L544] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L544] tmp = exists_runnable_thread() [L546] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L551] COND TRUE m_st == 0 [L552] int tmp_ndt_1; [L553] tmp_ndt_1 = __VERIFIER_nondet_int() [L554] COND TRUE \read(tmp_ndt_1) [L556] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L557] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L61] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L72] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L75] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L76] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND TRUE E_1 == 1 [L331] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND TRUE \read(tmp___0) [L824] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L76] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L77] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L80] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L82] m_pc = 1 [L83] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L557] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L565] COND TRUE t1_st == 0 [L566] int tmp_ndt_2; [L567] tmp_ndt_2 = __VERIFIER_nondet_int() [L568] COND TRUE \read(tmp_ndt_2) [L570] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L571] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L102] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L105] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L121] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L122] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L311] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND TRUE E_2 == 1 [L350] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND TRUE \read(tmp___1) [L832] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L122] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L123] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L113] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L115] t1_pc = 1 [L116] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L571] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L579] COND TRUE t2_st == 0 [L580] int tmp_ndt_3; [L581] tmp_ndt_3 = __VERIFIER_nondet_int() [L582] COND TRUE \read(tmp_ndt_3) [L584] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L585] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L137] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L140] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L156] E_3 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L157] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L311] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND TRUE E_3 == 1 [L369] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit3_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND TRUE \read(tmp___2) [L840] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0, tmp___4=0, tmp___5=0] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L157] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L158] E_3 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L148] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L150] t2_pc = 1 [L151] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L585] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L593] COND TRUE t3_st == 0 [L594] int tmp_ndt_4; [L595] tmp_ndt_4 = __VERIFIER_nondet_int() [L596] COND TRUE \read(tmp_ndt_4) [L598] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L599] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L172] COND FALSE !(t3_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L175] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L191] E_4 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L192] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L311] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND TRUE E_4 == 1 [L388] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit4_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND TRUE \read(tmp___3) [L848] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1, tmp___4=0, tmp___5=0] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L192] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L193] E_4 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L183] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L185] t3_pc = 1 [L186] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L599] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L607] COND TRUE t4_st == 0 [L608] int tmp_ndt_5; [L609] tmp_ndt_5 = __VERIFIER_nondet_int() [L610] COND TRUE \read(tmp_ndt_5) [L612] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L613] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L207] COND FALSE !(t4_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L210] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L226] E_5 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L227] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L311] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND TRUE E_5 == 1 [L407] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit5_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND TRUE \read(tmp___4) [L856] t5_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=1] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=1] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=1, tmp___5=0] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L227] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L228] E_5 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L218] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L220] t4_pc = 1 [L221] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L613] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L621] COND TRUE t5_st == 0 [L622] int tmp_ndt_6; [L623] tmp_ndt_6 = __VERIFIER_nondet_int() [L624] COND TRUE \read(tmp_ndt_6) [L626] t5_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L627] CALL transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L242] COND FALSE !(t5_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L245] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L261] E_6 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L262] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L311] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND TRUE E_6 == 1 [L426] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit6_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND TRUE \read(tmp___5) [L864] t6_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=1] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=0] [L262] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=0] [L263] E_6 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=0] [L253] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=0] [L255] t5_pc = 1 [L256] t5_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=0] [L627] RET transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L635] COND TRUE t6_st == 0 [L636] int tmp_ndt_7; [L637] tmp_ndt_7 = __VERIFIER_nondet_int() [L638] COND TRUE \read(tmp_ndt_7) [L640] t6_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L641] CALL transmit6() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=1, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1] [L277] COND FALSE !(t6_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=1, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1] [L280] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=1, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1] [L296] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=1, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=1, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 31 procedures, 289 locations, 1 error locations. UNSAFE Result, 321.8s OverallTime, 48 OverallIterations, 7 TraceHistogramMax, 148.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 21449 SDtfs, 25770 SDslu, 24945 SDs, 0 SdLazy, 14795 SolverSat, 5469 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 13.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 3671 GetRequests, 3398 SyntacticMatches, 71 SemanticMatches, 202 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 1.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=269019occurred in iteration=43, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 107.9s AutomataMinimizationTime, 47 MinimizatonAttempts, 31480 StatesRemovedByMinimization, 39 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.4s SsaConstructionTime, 1.1s SatisfiabilityAnalysisTime, 3.4s InterpolantComputationTime, 13718 NumberOfCodeBlocks, 13718 NumberOfCodeBlocksAsserted, 55 NumberOfCheckSat, 12940 ConstructedInterpolants, 0 QuantifiedInterpolants, 5471663 SizeOfPredicates, 8 NumberOfNonLiveVariables, 14299 ConjunctsInSsa, 44 ConjunctsInUnsatCore, 54 InterpolantComputations, 47 PerfectInterpolantSequences, 8152/8322 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...